Lines Matching +full:refclk +full:- +full:ext
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
317 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
322 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_icc_set()
333 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
335 * transitioning to Gen-2 speed in apply_bad_link_workaround()
337 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
340 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
341 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
342 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
346 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
349 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
352 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
361 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
362 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
370 if (!pcie->of_data->has_sbr_reset_fix && in tegra_pcie_rp_irq_handler()
396 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
399 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
406 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
408 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
417 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
421 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
425 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
430 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
465 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_irq_thread()
466 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
469 if (test_and_clear_bit(0, &pcie->link_status)) in tegra_pcie_ep_irq_thread()
474 if (pcie->of_data->has_ltr_req_fix) in tegra_pcie_ep_irq_thread()
478 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
487 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
511 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
534 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
535 set_bit(0, &pcie->link_status); in tegra_pcie_ep_hard_irq()
554 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
565 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_rd_own_conf()
572 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
575 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_rd_own_conf()
587 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_wr_own_conf()
594 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
597 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_wr_own_conf()
615 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
617 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
624 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
626 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
633 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
639 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
641 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
650 dev_get_drvdata(s->private); in aspm_state_cnt()
669 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
673 /* Re-enable counting */ in aspm_state_cnt()
676 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
684 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
688 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
690 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci, in init_host_aspm()
696 dw_pcie_writel_dbi(pci, pcie->ras_des_cap + in init_host_aspm()
700 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
702 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
703 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
704 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
709 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
716 struct device *dev = pcie->dev; in init_debugfs()
719 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in init_debugfs()
723 pcie->debugfs = debugfs_create_dir(name, NULL); in init_debugfs()
725 debugfs_create_devm_seqfile(dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
746 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_enable_system_interrupts()
752 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
754 val |= pcie->of_data->cdm_chk_int_en_bit; in tegra_pcie_enable_system_interrupts()
763 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
765 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); in tegra_pcie_enable_system_interrupts()
767 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
770 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
838 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
842 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
881 pcie->of_data->gen4_preset_vec); in config_gen3_gen4_eq_presets()
897 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
899 if (!pcie->pcie_cap_base) in tegra_pcie_dw_host_init()
900 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_dw_host_init()
922 if (pcie->enable_srns) { in tegra_pcie_dw_host_init()
923 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_dw_host_init()
926 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in tegra_pcie_dw_host_init()
934 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
935 if (!pcie->supports_clkreq) { in tegra_pcie_dw_host_init()
940 if (!pcie->of_data->has_l1ss_exit_fix) { in tegra_pcie_dw_host_init()
946 if (pcie->update_fc_fixup) { in tegra_pcie_dw_host_init()
952 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_dw_host_init()
960 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_dw_start_link()
964 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_start_link()
965 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
982 /* De-assert RST */ in tegra_pcie_dw_start_link()
1010 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_start_link()
1011 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_start_link()
1017 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_start_link()
1018 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_start_link()
1042 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1051 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1066 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1068 while (phy_count--) { in tegra_pcie_disable_phy()
1069 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1070 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1079 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1080 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1084 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1092 while (i--) { in tegra_pcie_enable_phy()
1093 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1095 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1103 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_dw_parse_dt()
1104 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1107 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in tegra_pcie_dw_parse_dt()
1108 if (!pcie->dbi_res) { in tegra_pcie_dw_parse_dt()
1109 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); in tegra_pcie_dw_parse_dt()
1110 return -ENODEV; in tegra_pcie_dw_parse_dt()
1113 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1115 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1119 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1120 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1122 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1125 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1126 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1128 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1131 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1133 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1137 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1139 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1143 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1145 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1149 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1151 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1152 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1154 /* RP using an external REFCLK is supported only in Tegra234 */ in tegra_pcie_dw_parse_dt()
1155 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) { in tegra_pcie_dw_parse_dt()
1156 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) in tegra_pcie_dw_parse_dt()
1157 pcie->enable_ext_refclk = true; in tegra_pcie_dw_parse_dt()
1159 pcie->enable_ext_refclk = in tegra_pcie_dw_parse_dt()
1160 of_property_read_bool(pcie->dev->of_node, in tegra_pcie_dw_parse_dt()
1161 "nvidia,enable-ext-refclk"); in tegra_pcie_dw_parse_dt()
1164 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1165 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1167 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1168 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1170 if (pcie->of_data->version == TEGRA234_DWC_IP_VER) in tegra_pcie_dw_parse_dt()
1171 pcie->enable_srns = in tegra_pcie_dw_parse_dt()
1172 of_property_read_bool(np, "nvidia,enable-srns"); in tegra_pcie_dw_parse_dt()
1174 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1178 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1179 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1180 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1183 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1186 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1192 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1193 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1195 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1196 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1199 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1202 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1203 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"), in tegra_pcie_dw_parse_dt()
1205 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1220 * Controller-5 doesn't need to have its state set by BPMP-FW in in tegra_pcie_bpmp_set_ctrl_state()
1223 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1230 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1240 err = tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1244 return -EINVAL; in tegra_pcie_bpmp_set_ctrl_state()
1262 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1265 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1275 err = tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1279 return -EINVAL; in tegra_pcie_bpmp_set_pll_state()
1286 struct dw_pcie_rp *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1295 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1299 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1300 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1307 dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n"); in tegra_pcie_downstream_dev_to_D0()
1312 list_for_each_entry(pdev, &root_port_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1313 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1315 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1317 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1324 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1325 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1326 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1327 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1329 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1332 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1333 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1334 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1335 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1337 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1347 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1348 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1350 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1356 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1357 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1359 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1367 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1370 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1376 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1377 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1383 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1384 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1385 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1386 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1397 dev_err(pcie->dev, in tegra_pcie_config_controller()
1398 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1402 if (pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1405 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret); in tegra_pcie_config_controller()
1414 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1416 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1420 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1422 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1426 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1428 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1433 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_config_controller()
1446 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1451 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1466 if (pcie->enable_srns || pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1470 * REFCLK out pads when RP & EP are using separate clocks or RP in tegra_pcie_config_controller()
1471 * is using an external REFCLK. in tegra_pcie_config_controller()
1479 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1488 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1491 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1496 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1498 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1500 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1504 if (pcie->enable_ext_refclk) in tegra_pcie_config_controller()
1516 ret = reset_control_assert(pcie->core_rst); in tegra_pcie_unconfig_controller()
1518 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1522 ret = reset_control_assert(pcie->core_apb_rst); in tegra_pcie_unconfig_controller()
1524 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1526 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_unconfig_controller()
1528 ret = regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_unconfig_controller()
1530 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in tegra_pcie_unconfig_controller()
1534 if (pcie->enable_ext_refclk) { in tegra_pcie_unconfig_controller()
1537 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret); in tegra_pcie_unconfig_controller()
1542 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in tegra_pcie_unconfig_controller()
1543 pcie->cid, ret); in tegra_pcie_unconfig_controller()
1548 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1549 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_init_controller()
1556 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1560 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1575 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1582 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1592 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1593 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1608 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1620 * Some cards do not go to detect state even after de-asserting in tegra_pcie_dw_pme_turnoff()
1621 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1623 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1625 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1627 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1635 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1638 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1643 /* Cut REFCLK to slot */ in tegra_pcie_dw_pme_turnoff()
1652 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1659 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1683 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1684 if (!pcie->link_state) { in tegra_pcie_config_rp()
1685 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1706 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1714 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1720 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1722 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1726 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1728 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1730 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1732 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_assert()
1735 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", in pex_ep_event_pex_rst_assert()
1741 dev_err(pcie->dev, "Failed to disable controller: %d\n", ret); in pex_ep_event_pex_rst_assert()
1743 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1744 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1749 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1750 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1751 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1756 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1768 dev_err(pcie->dev, "Failed to enable controller %u: %d\n", in pex_ep_event_pex_rst_deassert()
1769 pcie->cid, ret); in pex_ep_event_pex_rst_deassert()
1773 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_deassert()
1782 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1788 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1800 /* Perform cleanup that requires refclk */ in pex_ep_event_pex_rst_deassert()
1801 pci_epc_deinit_notify(pcie->pci.ep.epc); in pex_ep_event_pex_rst_deassert()
1802 dw_pcie_ep_cleanup(&pcie->pci.ep); in pex_ep_event_pex_rst_deassert()
1844 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1847 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1862 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1864 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1874 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1875 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1880 if (!pcie->of_data->has_l1ss_exit_fix) { in pex_ep_event_pex_rst_deassert()
1886 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1890 if (pcie->enable_srns) { in pex_ep_event_pex_rst_deassert()
1891 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in pex_ep_event_pex_rst_deassert()
1894 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in pex_ep_event_pex_rst_deassert()
1898 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1900 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1903 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1912 pci_epc_init_notify(ep->epc); in pex_ep_event_pex_rst_deassert()
1915 if (pcie->of_data->has_ltr_req_fix) { in pex_ep_event_pex_rst_deassert()
1926 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1932 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1935 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1937 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1950 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1971 return -EINVAL; in tegra_pcie_ep_raise_intx_irq()
1982 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1984 appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1); in tegra_pcie_ep_raise_msi_irq()
1991 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1993 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
2015 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
2016 return -EPERM; in tegra_pcie_ep_raise_irq()
2050 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
2051 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
2056 ep = &pci->ep; in tegra_pcie_config_ep()
2057 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
2059 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
2061 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
2068 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
2073 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
2076 pcie->cid); in tegra_pcie_config_ep()
2079 return -ENOMEM; in tegra_pcie_config_ep()
2082 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
2084 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
2086 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
2112 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
2126 return -ENOMEM; in tegra_pcie_dw_probe()
2128 pci = &pcie->pci; in tegra_pcie_dw_probe()
2129 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
2130 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
2131 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
2132 pcie->of_data = (struct tegra_pcie_dw_of_data *)data; in tegra_pcie_dw_probe()
2133 pci->n_fts[0] = pcie->of_data->n_fts[0]; in tegra_pcie_dw_probe()
2134 pci->n_fts[1] = pcie->of_data->n_fts[1]; in tegra_pcie_dw_probe()
2135 pp = &pci->pp; in tegra_pcie_dw_probe()
2136 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_dw_probe()
2142 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2155 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2164 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2165 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2167 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2168 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2169 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2170 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2172 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2176 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2177 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2179 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2180 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2183 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2185 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2187 return -ENODEV; in tegra_pcie_dw_probe()
2190 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2191 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2192 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2194 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2195 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2197 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2198 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2201 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2203 return -ENOMEM; in tegra_pcie_dw_probe()
2205 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2206 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2209 return -ENOMEM; in tegra_pcie_dw_probe()
2215 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2221 pcie->phys = phys; in tegra_pcie_dw_probe()
2227 return -ENODEV; in tegra_pcie_dw_probe()
2229 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2231 pci->atu_size = resource_size(atu_dma_res); in tegra_pcie_dw_probe()
2232 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2233 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2234 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2236 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2237 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2239 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2240 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2243 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2244 if (pp->irq < 0) in tegra_pcie_dw_probe()
2245 return pp->irq; in tegra_pcie_dw_probe()
2247 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2248 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2249 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2253 pcie->icc_path = devm_of_icc_get(&pdev->dev, "write"); in tegra_pcie_dw_probe()
2254 ret = PTR_ERR_OR_ZERO(pcie->icc_path); in tegra_pcie_dw_probe()
2256 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2257 dev_err_probe(&pdev->dev, ret, "failed to get write interconnect\n"); in tegra_pcie_dw_probe()
2261 switch (pcie->of_data->mode) { in tegra_pcie_dw_probe()
2263 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2264 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2266 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2272 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2279 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2283 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2285 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2299 pcie->of_data->mode); in tegra_pcie_dw_probe()
2300 ret = -EINVAL; in tegra_pcie_dw_probe()
2304 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2312 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_remove()
2313 if (!pcie->link_state) in tegra_pcie_dw_remove()
2316 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2318 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2320 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_remove()
2324 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2325 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2326 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2327 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2335 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_suspend_late()
2337 return -EPERM; in tegra_pcie_dw_suspend_late()
2340 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2344 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_suspend_late()
2359 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2374 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2381 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2387 dw_pcie_setup_rc(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2389 ret = tegra_pcie_dw_start_link(&pcie->pci); in tegra_pcie_dw_resume_noirq()
2405 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_resume_early()
2407 return -ENOTSUPP; in tegra_pcie_dw_resume_early()
2410 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2414 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_resume_early()
2431 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_shutdown()
2432 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2435 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2438 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2440 disable_irq(pcie->pci.pp.msi_irq[0]); in tegra_pcie_dw_shutdown()
2444 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_shutdown()
2446 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_shutdown()
2455 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2464 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2476 /* Gen4 - 6, 8 and 9 presets enabled */
2487 /* Gen4 - 6, 8 and 9 presets enabled */
2494 .compatible = "nvidia,tegra194-pcie",
2498 .compatible = "nvidia,tegra194-pcie-ep",
2502 .compatible = "nvidia,tegra234-pcie",
2506 .compatible = "nvidia,tegra234-pcie-ep",
2524 .name = "tegra194-pcie",