278 	void __iomem *parf;			/* DT parf */  member
374 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_base()
376 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_base()
391 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
393 		writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
397 			writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
399 			writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
403 		writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);  in qcom_pcie_configure_dbi_atu_base()
404 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
469 	writel(1, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
514 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
516 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
527 		       pcie->parf + PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
530 		       pcie->parf + PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
531 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
536 		val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
539 		writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
543 	val = readl(pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
548 	writel(val, pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
633 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
636 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
661 	val = readl(pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
663 	writel(val, pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
725 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
727 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
732 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
734 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
736 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
738 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
740 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
742 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
911 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
913 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
920 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
921 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
1004 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
1007 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1009 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1014 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1016 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1018 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1020 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1023 	val = readl(pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1025 	writel(val, pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1029 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
1031 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
1048 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);  in qcom_pcie_post_init_2_7_0()
1092 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_1_9_0()
1104 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1106 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1221 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1223 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1227 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1229 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1237 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1239 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1255 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1643 	u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);  in qcom_pcie_global_irq_thread()
1645 	writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);  in qcom_pcie_global_irq_thread()
1878 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1879 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1880 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()
1988 			       pcie->parf + PARF_INT_ALL_MASK);  in qcom_pcie_probe()