Lines Matching +full:pcie +full:- +full:sc8180x
1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/pci-ecam.h>
30 #include <linux/phy/pcie.h>
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
41 #include "pcie-qcom-common.h"
247 int (*get_resources)(struct qcom_pcie *pcie);
248 int (*init)(struct qcom_pcie *pcie);
249 int (*post_init)(struct qcom_pcie *pcie);
250 void (*host_post_init)(struct qcom_pcie *pcie);
251 void (*deinit)(struct qcom_pcie *pcie);
252 void (*ltssm_enable)(struct qcom_pcie *pcie);
253 int (*config_sid)(struct qcom_pcie *pcie);
257 * struct qcom_pcie_cfg - Per SoC config struct
258 * @ops: qcom PCIe ops structure
290 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
292 static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) in qcom_perst_assert() argument
297 list_for_each_entry(port, &pcie->ports, list) in qcom_perst_assert()
298 gpiod_set_value_cansleep(port->reset, val); in qcom_perst_assert()
303 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
305 qcom_perst_assert(pcie, true); in qcom_ep_reset_assert()
308 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
312 qcom_perst_assert(pcie, false); in qcom_ep_reset_deassert()
317 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_start_link() local
321 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) in qcom_pcie_start_link()
325 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
326 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
333 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_clear_aspm_l0s() local
337 if (!pcie->cfg->no_l0s) in qcom_pcie_clear_aspm_l0s()
344 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
346 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
358 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
360 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
365 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_base() argument
367 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_base()
369 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_base()
374 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_base()
376 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_base()
381 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_atu_base() argument
383 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_atu_base()
385 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
391 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
393 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
396 if (pci->atu_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
397 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
399 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
403 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); in qcom_pcie_configure_dbi_atu_base()
404 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_atu_base()
409 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_1_0_ltssm_enable() argument
411 struct dw_pcie *pci = pcie->pci; in qcom_pcie_2_1_0_ltssm_enable()
414 if (!pci->elbi_base) { in qcom_pcie_2_1_0_ltssm_enable()
415 dev_err(pci->dev, "ELBI is not present\n"); in qcom_pcie_2_1_0_ltssm_enable()
419 val = readl(pci->elbi_base + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
421 writel(val, pci->elbi_base + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
424 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_1_0() argument
426 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
427 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
428 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_1_0()
429 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
432 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_1_0()
433 res->supplies[1].supply = "vdda_phy"; in qcom_pcie_get_resources_2_1_0()
434 res->supplies[2].supply = "vdda_refclk"; in qcom_pcie_get_resources_2_1_0()
435 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_1_0()
436 res->supplies); in qcom_pcie_get_resources_2_1_0()
440 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_1_0()
441 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_1_0()
443 return res->num_clks; in qcom_pcie_get_resources_2_1_0()
446 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
447 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
448 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
449 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
450 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
451 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
454 res->num_resets = is_apq ? 5 : 6; in qcom_pcie_get_resources_2_1_0()
455 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_1_0()
462 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_1_0() argument
464 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
466 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_1_0()
467 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_1_0()
469 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
471 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_1_0()
474 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_1_0() argument
476 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
477 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
478 struct device *dev = pci->dev; in qcom_pcie_init_2_1_0()
481 /* reset the PCIe interface as uboot can leave it undefined state */ in qcom_pcie_init_2_1_0()
482 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
488 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
494 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
497 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
504 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_1_0() argument
506 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
507 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
508 struct device *dev = pci->dev; in qcom_pcie_post_init_2_1_0()
509 struct device_node *node = dev->of_node; in qcom_pcie_post_init_2_1_0()
513 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_1_0()
514 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
516 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
518 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_post_init_2_1_0()
522 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
523 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
527 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
530 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
531 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
534 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
536 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
539 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
543 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
545 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
548 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
555 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_post_init_2_1_0()
557 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_post_init_2_1_0()
559 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
564 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_1_0_0() argument
566 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
567 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
568 struct device *dev = pci->dev; in qcom_pcie_get_resources_1_0_0()
570 res->vdda = devm_regulator_get(dev, "vdda"); in qcom_pcie_get_resources_1_0_0()
571 if (IS_ERR(res->vdda)) in qcom_pcie_get_resources_1_0_0()
572 return PTR_ERR(res->vdda); in qcom_pcie_get_resources_1_0_0()
574 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_1_0_0()
575 if (res->num_clks < 0) { in qcom_pcie_get_resources_1_0_0()
577 return res->num_clks; in qcom_pcie_get_resources_1_0_0()
580 res->core = devm_reset_control_get_exclusive(dev, "core"); in qcom_pcie_get_resources_1_0_0()
581 return PTR_ERR_OR_ZERO(res->core); in qcom_pcie_get_resources_1_0_0()
584 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_1_0_0() argument
586 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
588 reset_control_assert(res->core); in qcom_pcie_deinit_1_0_0()
589 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_1_0_0()
590 regulator_disable(res->vdda); in qcom_pcie_deinit_1_0_0()
593 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_init_1_0_0() argument
595 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
596 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
597 struct device *dev = pci->dev; in qcom_pcie_init_1_0_0()
600 ret = reset_control_deassert(res->core); in qcom_pcie_init_1_0_0()
606 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
612 ret = regulator_enable(res->vdda); in qcom_pcie_init_1_0_0()
621 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
623 reset_control_assert(res->core); in qcom_pcie_init_1_0_0()
628 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_1_0_0() argument
630 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_1_0_0()
633 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
636 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
639 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
644 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_3_2_ltssm_enable() argument
649 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
651 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
654 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_2() argument
656 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
657 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
658 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_2()
661 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_3_2()
662 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_3_2()
663 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_3_2()
664 res->supplies); in qcom_pcie_get_resources_2_3_2()
668 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_2()
669 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_2()
671 return res->num_clks; in qcom_pcie_get_resources_2_3_2()
677 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_2() argument
679 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
681 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_2()
682 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_3_2()
685 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_2() argument
687 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
688 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
689 struct device *dev = pci->dev; in qcom_pcie_init_2_3_2()
692 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
698 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_2()
701 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
708 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_2() argument
712 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_3_2()
713 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
715 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
717 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_2_3_2()
720 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
722 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
724 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
726 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
728 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
730 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
732 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
737 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_4_0() argument
739 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
740 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
741 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_4_0()
742 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
745 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_4_0()
746 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_4_0()
748 return res->num_clks; in qcom_pcie_get_resources_2_4_0()
751 res->resets[0].id = "axi_m"; in qcom_pcie_get_resources_2_4_0()
752 res->resets[1].id = "axi_s"; in qcom_pcie_get_resources_2_4_0()
753 res->resets[2].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_4_0()
754 res->resets[3].id = "pipe_sticky"; in qcom_pcie_get_resources_2_4_0()
755 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
756 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
757 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
758 res->resets[7].id = "axi_m_vmid"; in qcom_pcie_get_resources_2_4_0()
759 res->resets[8].id = "axi_s_xpu"; in qcom_pcie_get_resources_2_4_0()
760 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
761 res->resets[10].id = "phy"; in qcom_pcie_get_resources_2_4_0()
762 res->resets[11].id = "phy_ahb"; in qcom_pcie_get_resources_2_4_0()
764 res->num_resets = is_ipq ? 12 : 6; in qcom_pcie_get_resources_2_4_0()
766 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_4_0()
773 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_4_0() argument
775 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
777 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_4_0()
778 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_4_0()
781 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_4_0() argument
783 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
784 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
785 struct device *dev = pci->dev; in qcom_pcie_init_2_4_0()
788 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
796 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
804 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_4_0()
806 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
813 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_3() argument
815 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
816 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
817 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_3()
820 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_3()
821 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_3()
823 return res->num_clks; in qcom_pcie_get_resources_2_3_3()
826 res->rst[0].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
827 res->rst[1].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
828 res->rst[2].id = "pipe"; in qcom_pcie_get_resources_2_3_3()
829 res->rst[3].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_3_3()
830 res->rst[4].id = "sticky"; in qcom_pcie_get_resources_2_3_3()
831 res->rst[5].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
832 res->rst[6].id = "sleep"; in qcom_pcie_get_resources_2_3_3()
834 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_get_resources_2_3_3()
841 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_3() argument
843 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
845 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_3()
848 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_3() argument
850 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
851 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
852 struct device *dev = pci->dev; in qcom_pcie_init_2_3_3()
855 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
863 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
875 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_3()
888 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
893 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_3() argument
895 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
899 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
901 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
903 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_3_3()
908 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
909 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
911 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
915 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
917 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
919 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
921 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
929 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_7_0() argument
931 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
932 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
933 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_7_0()
936 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_7_0()
937 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_7_0()
938 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_7_0()
940 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_7_0()
941 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_7_0()
942 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_7_0()
943 res->supplies); in qcom_pcie_get_resources_2_7_0()
947 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_7_0()
948 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_7_0()
950 return res->num_clks; in qcom_pcie_get_resources_2_7_0()
956 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_7_0() argument
958 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
959 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
960 struct device *dev = pci->dev; in qcom_pcie_init_2_7_0()
964 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
970 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
974 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_7_0()
982 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_7_0()
991 /* configure PCIe to RC mode */ in qcom_pcie_init_2_7_0()
992 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
994 /* enable PCIe clocks and resets */ in qcom_pcie_init_2_7_0()
995 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
997 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
999 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_init_2_7_0()
1002 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
1004 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
1006 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
1008 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
1011 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
1013 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
1015 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1017 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1021 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
1023 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
1028 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_7_0() argument
1030 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; in qcom_pcie_post_init_2_7_0()
1032 if (pcie_cfg->override_no_snoop) in qcom_pcie_post_init_2_7_0()
1034 pcie->parf + PARF_NO_SNOOP_OVERRIDE); in qcom_pcie_post_init_2_7_0()
1036 qcom_pcie_clear_aspm_l0s(pcie->pci); in qcom_pcie_post_init_2_7_0()
1037 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
1054 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_host_post_init_2_7_0() argument
1056 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_host_post_init_2_7_0()
1058 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); in qcom_pcie_host_post_init_2_7_0()
1061 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_7_0() argument
1063 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
1065 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_7_0()
1067 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_7_0()
1070 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) in qcom_pcie_config_sid_1_9_0() argument
1079 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
1080 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
1086 of_get_property(dev->of_node, "iommu-map", &size); in qcom_pcie_config_sid_1_9_0()
1091 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1093 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1097 return -ENOMEM; in qcom_pcie_config_sid_1_9_0()
1099 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, in qcom_pcie_config_sid_1_9_0()
1109 /* Extract the SMMU SID base from the first entry of iommu-map */ in qcom_pcie_config_sid_1_9_0()
1137 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; in qcom_pcie_config_sid_1_9_0()
1146 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_9_0() argument
1148 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1149 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1150 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_9_0()
1152 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_9_0()
1153 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_9_0()
1155 return res->num_clks; in qcom_pcie_get_resources_2_9_0()
1158 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_9_0()
1159 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_9_0()
1160 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_9_0()
1165 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_9_0() argument
1167 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1169 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_9_0()
1172 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_9_0() argument
1174 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1175 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1178 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_9_0()
1190 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_9_0()
1198 return clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_9_0()
1201 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_9_0() argument
1203 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1208 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1210 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1212 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_9_0()
1214 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1216 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1219 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()
1224 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1226 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1230 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_9_0()
1232 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1234 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1236 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_9_0()
1242 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1250 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1255 static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) in qcom_pcie_phy_power_off() argument
1259 list_for_each_entry(port, &pcie->ports, list) in qcom_pcie_phy_power_off()
1260 phy_power_off(port->phy); in qcom_pcie_phy_power_off()
1263 static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) in qcom_pcie_phy_power_on() argument
1268 list_for_each_entry(port, &pcie->ports, list) { in qcom_pcie_phy_power_on()
1269 ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_phy_power_on()
1273 ret = phy_power_on(port->phy); in qcom_pcie_phy_power_on()
1275 qcom_pcie_phy_power_off(pcie); in qcom_pcie_phy_power_on()
1286 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_init() local
1289 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1291 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1295 ret = qcom_pcie_phy_power_on(pcie); in qcom_pcie_host_init()
1299 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1300 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1305 qcom_ep_reset_deassert(pcie); in qcom_pcie_host_init()
1307 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1308 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1316 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1318 qcom_pcie_phy_power_off(pcie); in qcom_pcie_host_init()
1320 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1328 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_deinit() local
1330 qcom_ep_reset_assert(pcie); in qcom_pcie_host_deinit()
1331 qcom_pcie_phy_power_off(pcie); in qcom_pcie_host_deinit()
1332 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1338 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_post_init() local
1340 if (pcie->cfg->ops->host_post_init) in qcom_pcie_host_post_init()
1341 pcie->cfg->ops->host_post_init(pcie); in qcom_pcie_host_post_init()
1485 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) in qcom_pcie_icc_init() argument
1487 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1490 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1491 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1492 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1494 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); in qcom_pcie_icc_init()
1495 if (IS_ERR(pcie->icc_cpu)) in qcom_pcie_icc_init()
1496 return PTR_ERR(pcie->icc_cpu); in qcom_pcie_icc_init()
1501 * Set an initial peak bandwidth corresponding to single-lane Gen 1 in qcom_pcie_icc_init()
1502 * for the pcie-mem path. in qcom_pcie_icc_init()
1504 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); in qcom_pcie_icc_init()
1506 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_init()
1512 * Since the CPU-PCIe path is only used for activities like register in qcom_pcie_icc_init()
1517 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); in qcom_pcie_icc_init()
1519 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", in qcom_pcie_icc_init()
1521 icc_set_bw(pcie->icc_mem, 0, 0); in qcom_pcie_icc_init()
1528 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) in qcom_pcie_icc_opp_update() argument
1531 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_opp_update()
1537 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_icc_opp_update()
1546 if (pcie->icc_mem) { in qcom_pcie_icc_opp_update()
1547 ret = icc_set_bw(pcie->icc_mem, 0, in qcom_pcie_icc_opp_update()
1550 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_opp_update()
1553 } else if (pcie->use_pm_opp) { in qcom_pcie_icc_opp_update()
1559 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, in qcom_pcie_icc_opp_update()
1562 ret = dev_pm_opp_set_opp(pci->dev, opp); in qcom_pcie_icc_opp_update()
1564 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", in qcom_pcie_icc_opp_update()
1573 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count() local
1576 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1579 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1582 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1585 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1588 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1593 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) in qcom_pcie_init_debugfs() argument
1595 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1596 struct device *dev = pci->dev; in qcom_pcie_init_debugfs()
1599 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in qcom_pcie_init_debugfs()
1603 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1604 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1610 struct qcom_pcie *pcie = data; in qcom_pcie_global_irq_thread() local
1611 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_global_irq_thread()
1612 struct device *dev = pcie->pci->dev; in qcom_pcie_global_irq_thread()
1613 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); in qcom_pcie_global_irq_thread()
1615 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); in qcom_pcie_global_irq_thread()
1622 pci_rescan_bus(pp->bridge->bus); in qcom_pcie_global_irq_thread()
1625 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_global_irq_thread()
1638 if (pp && pp->has_msi_ctrl) in qcom_pci_free_msi()
1644 struct device *dev = cfg->parent; in qcom_pcie_ecam_host_init()
1651 return -ENOMEM; in qcom_pcie_ecam_host_init()
1653 pci->dev = dev; in qcom_pcie_ecam_host_init()
1654 pp = &pci->pp; in qcom_pcie_ecam_host_init()
1655 pci->dbi_base = cfg->win; in qcom_pcie_ecam_host_init()
1656 pp->num_vectors = MSI_DEF_NUM_VECTORS; in qcom_pcie_ecam_host_init()
1662 pp->has_msi_ctrl = true; in qcom_pcie_ecam_host_init()
1677 static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node) in qcom_pcie_parse_port() argument
1679 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_port()
1696 return -ENOMEM; in qcom_pcie_parse_port()
1702 port->reset = reset; in qcom_pcie_parse_port()
1703 port->phy = phy; in qcom_pcie_parse_port()
1704 INIT_LIST_HEAD(&port->list); in qcom_pcie_parse_port()
1705 list_add_tail(&port->list, &pcie->ports); in qcom_pcie_parse_port()
1710 static int qcom_pcie_parse_ports(struct qcom_pcie *pcie) in qcom_pcie_parse_ports() argument
1712 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_ports()
1714 int ret = -ENOENT; in qcom_pcie_parse_ports()
1716 for_each_available_child_of_node_scoped(dev->of_node, of_port) { in qcom_pcie_parse_ports()
1719 ret = qcom_pcie_parse_port(pcie, of_port); in qcom_pcie_parse_ports()
1727 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in qcom_pcie_parse_ports()
1728 phy_exit(port->phy); in qcom_pcie_parse_ports()
1729 list_del(&port->list); in qcom_pcie_parse_ports()
1735 static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) in qcom_pcie_parse_legacy_binding() argument
1737 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_legacy_binding()
1757 return -ENOMEM; in qcom_pcie_parse_legacy_binding()
1759 port->reset = reset; in qcom_pcie_parse_legacy_binding()
1760 port->phy = phy; in qcom_pcie_parse_legacy_binding()
1761 INIT_LIST_HEAD(&port->list); in qcom_pcie_parse_legacy_binding()
1762 list_add_tail(&port->list, &pcie->ports); in qcom_pcie_parse_legacy_binding()
1772 struct device *dev = &pdev->dev; in qcom_pcie_probe()
1774 struct qcom_pcie *pcie; in qcom_pcie_probe() local
1784 return -ENODATA; in qcom_pcie_probe()
1787 if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) { in qcom_pcie_probe()
1789 return -ENODATA; in qcom_pcie_probe()
1797 if (pcie_cfg->firmware_managed) { in qcom_pcie_probe()
1803 ret = -ENOMEM; in qcom_pcie_probe()
1815 bridge->sysdata = cfg; in qcom_pcie_probe()
1816 bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops; in qcom_pcie_probe()
1817 bridge->msi_domain = true; in qcom_pcie_probe()
1826 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in qcom_pcie_probe()
1827 if (!pcie) { in qcom_pcie_probe()
1828 ret = -ENOMEM; in qcom_pcie_probe()
1834 ret = -ENOMEM; in qcom_pcie_probe()
1838 INIT_LIST_HEAD(&pcie->ports); in qcom_pcie_probe()
1840 pci->dev = dev; in qcom_pcie_probe()
1841 pci->ops = &dw_pcie_ops; in qcom_pcie_probe()
1842 pp = &pci->pp; in qcom_pcie_probe()
1844 pcie->pci = pci; in qcom_pcie_probe()
1846 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1848 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1849 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1850 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1857 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1858 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1859 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1866 if (ret && ret != -ENODEV) { in qcom_pcie_probe()
1872 * Before the PCIe link is initialized, vote for highest OPP in the OPP in qcom_pcie_probe()
1881 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1890 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1896 pcie->use_pm_opp = true; in qcom_pcie_probe()
1899 ret = qcom_pcie_icc_init(pcie); in qcom_pcie_probe()
1904 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1908 pp->ops = &qcom_pcie_dw_ops; in qcom_pcie_probe()
1910 ret = qcom_pcie_parse_ports(pcie); in qcom_pcie_probe()
1912 if (ret != -ENOENT) { in qcom_pcie_probe()
1913 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1923 ret = qcom_pcie_parse_legacy_binding(pcie); in qcom_pcie_probe()
1928 platform_set_drvdata(pdev, pcie); in qcom_pcie_probe()
1932 pp->use_linkup_irq = true; in qcom_pcie_probe()
1941 pci_domain_nr(pp->bridge->bus)); in qcom_pcie_probe()
1943 ret = -ENOMEM; in qcom_pcie_probe()
1948 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in qcom_pcie_probe()
1950 IRQF_ONESHOT, name, pcie); in qcom_pcie_probe()
1952 dev_err_probe(&pdev->dev, ret, in qcom_pcie_probe()
1958 pcie->parf + PARF_INT_ALL_MASK); in qcom_pcie_probe()
1961 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_probe()
1963 if (pcie->mhi) in qcom_pcie_probe()
1964 qcom_pcie_init_debugfs(pcie); in qcom_pcie_probe()
1971 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in qcom_pcie_probe()
1972 phy_exit(port->phy); in qcom_pcie_probe()
1973 list_del(&port->list); in qcom_pcie_probe()
1984 struct qcom_pcie *pcie; in qcom_pcie_suspend_noirq() local
1987 pcie = dev_get_drvdata(dev); in qcom_pcie_suspend_noirq()
1988 if (!pcie) in qcom_pcie_suspend_noirq()
1995 if (pcie->icc_mem) { in qcom_pcie_suspend_noirq()
1996 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
1999 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_suspend_noirq()
2006 * Turn OFF the resources only for controllers without active PCIe in qcom_pcie_suspend_noirq()
2010 * Turning OFF the resources for controllers with active PCIe devices in qcom_pcie_suspend_noirq()
2012 * as kernel tries to access the PCIe devices config space for masking in qcom_pcie_suspend_noirq()
2020 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
2021 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
2022 pcie->suspended = true; in qcom_pcie_suspend_noirq()
2026 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. in qcom_pcie_suspend_noirq()
2028 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC in qcom_pcie_suspend_noirq()
2032 ret = icc_disable(pcie->icc_cpu); in qcom_pcie_suspend_noirq()
2034 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_suspend_noirq()
2036 if (pcie->use_pm_opp) in qcom_pcie_suspend_noirq()
2037 dev_pm_opp_set_opp(pcie->pci->dev, NULL); in qcom_pcie_suspend_noirq()
2044 struct qcom_pcie *pcie; in qcom_pcie_resume_noirq() local
2047 pcie = dev_get_drvdata(dev); in qcom_pcie_resume_noirq()
2048 if (!pcie) in qcom_pcie_resume_noirq()
2052 ret = icc_enable(pcie->icc_cpu); in qcom_pcie_resume_noirq()
2054 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_resume_noirq()
2059 if (pcie->suspended) { in qcom_pcie_resume_noirq()
2060 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
2064 pcie->suspended = false; in qcom_pcie_resume_noirq()
2067 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_resume_noirq()
2073 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
2074 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
2075 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
2076 { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
2077 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
2078 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
2079 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
2080 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
2081 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
2082 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
2083 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
2084 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
2085 { .compatible = "qcom,pcie-sa8255p", .data = &cfg_fw_managed },
2086 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
2087 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
2088 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
2089 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
2090 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
2091 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
2092 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
2093 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
2094 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
2095 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
2096 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
2097 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
2098 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
2099 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
2105 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in qcom_fixup_class()
2122 .name = "qcom-pcie",