Lines Matching +full:pcie +full:- +full:sa8255p
1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/pci-ecam.h>
30 #include <linux/phy/pcie.h>
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
41 #include "pcie-qcom-common.h"
247 int (*get_resources)(struct qcom_pcie *pcie);
248 int (*init)(struct qcom_pcie *pcie);
249 int (*post_init)(struct qcom_pcie *pcie);
250 void (*host_post_init)(struct qcom_pcie *pcie);
251 void (*deinit)(struct qcom_pcie *pcie);
252 void (*ltssm_enable)(struct qcom_pcie *pcie);
253 int (*config_sid)(struct qcom_pcie *pcie);
257 * struct qcom_pcie_cfg - Per SoC config struct
258 * @ops: qcom PCIe ops structure
293 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
295 static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) in qcom_perst_assert() argument
300 if (list_empty(&pcie->ports)) in qcom_perst_assert()
301 gpiod_set_value_cansleep(pcie->reset, val); in qcom_perst_assert()
303 list_for_each_entry(port, &pcie->ports, list) in qcom_perst_assert()
304 gpiod_set_value_cansleep(port->reset, val); in qcom_perst_assert()
309 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
311 qcom_perst_assert(pcie, true); in qcom_ep_reset_assert()
314 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
318 qcom_perst_assert(pcie, false); in qcom_ep_reset_deassert()
323 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_start_link() local
325 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { in qcom_pcie_start_link()
331 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
332 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
339 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_clear_aspm_l0s() local
343 if (!pcie->cfg->no_l0s) in qcom_pcie_clear_aspm_l0s()
350 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
352 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
364 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
366 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
371 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_base() argument
373 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_base()
375 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_base()
380 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_base()
382 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_base()
387 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) in qcom_pcie_configure_dbi_atu_base() argument
389 struct dw_pcie *pci = pcie->pci; in qcom_pcie_configure_dbi_atu_base()
391 if (pci->dbi_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
397 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
399 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
402 if (pci->atu_phys_addr) { in qcom_pcie_configure_dbi_atu_base()
403 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
405 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
409 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); in qcom_pcie_configure_dbi_atu_base()
410 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_atu_base()
415 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_1_0_ltssm_enable() argument
420 val = readl(pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
422 writel(val, pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
425 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_1_0() argument
427 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
428 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
429 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_1_0()
430 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
433 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_1_0()
434 res->supplies[1].supply = "vdda_phy"; in qcom_pcie_get_resources_2_1_0()
435 res->supplies[2].supply = "vdda_refclk"; in qcom_pcie_get_resources_2_1_0()
436 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_1_0()
437 res->supplies); in qcom_pcie_get_resources_2_1_0()
441 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_1_0()
442 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_1_0()
444 return res->num_clks; in qcom_pcie_get_resources_2_1_0()
447 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
448 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
449 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
450 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
451 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
452 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
455 res->num_resets = is_apq ? 5 : 6; in qcom_pcie_get_resources_2_1_0()
456 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_1_0()
463 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_1_0() argument
465 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
467 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_1_0()
468 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_1_0()
470 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
472 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_1_0()
475 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_1_0() argument
477 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
478 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
479 struct device *dev = pci->dev; in qcom_pcie_init_2_1_0()
482 /* reset the PCIe interface as uboot can leave it undefined state */ in qcom_pcie_init_2_1_0()
483 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
489 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
495 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
498 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
505 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_1_0() argument
507 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
508 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
509 struct device *dev = pci->dev; in qcom_pcie_post_init_2_1_0()
510 struct device_node *node = dev->of_node; in qcom_pcie_post_init_2_1_0()
514 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_1_0()
515 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
517 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
519 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_post_init_2_1_0()
523 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
524 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
528 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
531 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
532 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
535 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
537 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
540 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
544 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
546 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
549 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
556 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_post_init_2_1_0()
558 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_post_init_2_1_0()
560 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
565 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_1_0_0() argument
567 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
568 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
569 struct device *dev = pci->dev; in qcom_pcie_get_resources_1_0_0()
571 res->vdda = devm_regulator_get(dev, "vdda"); in qcom_pcie_get_resources_1_0_0()
572 if (IS_ERR(res->vdda)) in qcom_pcie_get_resources_1_0_0()
573 return PTR_ERR(res->vdda); in qcom_pcie_get_resources_1_0_0()
575 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_1_0_0()
576 if (res->num_clks < 0) { in qcom_pcie_get_resources_1_0_0()
578 return res->num_clks; in qcom_pcie_get_resources_1_0_0()
581 res->core = devm_reset_control_get_exclusive(dev, "core"); in qcom_pcie_get_resources_1_0_0()
582 return PTR_ERR_OR_ZERO(res->core); in qcom_pcie_get_resources_1_0_0()
585 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_1_0_0() argument
587 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
589 reset_control_assert(res->core); in qcom_pcie_deinit_1_0_0()
590 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_1_0_0()
591 regulator_disable(res->vdda); in qcom_pcie_deinit_1_0_0()
594 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_init_1_0_0() argument
596 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
597 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
598 struct device *dev = pci->dev; in qcom_pcie_init_1_0_0()
601 ret = reset_control_deassert(res->core); in qcom_pcie_init_1_0_0()
607 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
613 ret = regulator_enable(res->vdda); in qcom_pcie_init_1_0_0()
622 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_1_0_0()
624 reset_control_assert(res->core); in qcom_pcie_init_1_0_0()
629 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_1_0_0() argument
631 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_1_0_0()
634 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
637 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
640 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
645 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_3_2_ltssm_enable() argument
650 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
652 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
655 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_2() argument
657 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
658 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
659 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_2()
662 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_3_2()
663 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_3_2()
664 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_3_2()
665 res->supplies); in qcom_pcie_get_resources_2_3_2()
669 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_2()
670 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_2()
672 return res->num_clks; in qcom_pcie_get_resources_2_3_2()
678 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_2() argument
680 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
682 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_2()
683 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_3_2()
686 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_2() argument
688 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
689 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
690 struct device *dev = pci->dev; in qcom_pcie_init_2_3_2()
693 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
699 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_2()
702 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
709 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_2() argument
713 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_3_2()
714 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
716 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
718 qcom_pcie_configure_dbi_base(pcie); in qcom_pcie_post_init_2_3_2()
721 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
723 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
725 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
727 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
729 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
731 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
733 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
738 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_4_0() argument
740 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
741 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
742 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_4_0()
743 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
746 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_4_0()
747 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_4_0()
749 return res->num_clks; in qcom_pcie_get_resources_2_4_0()
752 res->resets[0].id = "axi_m"; in qcom_pcie_get_resources_2_4_0()
753 res->resets[1].id = "axi_s"; in qcom_pcie_get_resources_2_4_0()
754 res->resets[2].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_4_0()
755 res->resets[3].id = "pipe_sticky"; in qcom_pcie_get_resources_2_4_0()
756 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
757 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
758 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
759 res->resets[7].id = "axi_m_vmid"; in qcom_pcie_get_resources_2_4_0()
760 res->resets[8].id = "axi_s_xpu"; in qcom_pcie_get_resources_2_4_0()
761 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
762 res->resets[10].id = "phy"; in qcom_pcie_get_resources_2_4_0()
763 res->resets[11].id = "phy_ahb"; in qcom_pcie_get_resources_2_4_0()
765 res->num_resets = is_ipq ? 12 : 6; in qcom_pcie_get_resources_2_4_0()
767 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_4_0()
774 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_4_0() argument
776 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
778 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_4_0()
779 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_4_0()
782 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_4_0() argument
784 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
785 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
786 struct device *dev = pci->dev; in qcom_pcie_init_2_4_0()
789 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
797 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
805 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_4_0()
807 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
814 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_3() argument
816 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
817 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
818 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_3()
821 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_3_3()
822 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_3_3()
824 return res->num_clks; in qcom_pcie_get_resources_2_3_3()
827 res->rst[0].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
828 res->rst[1].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
829 res->rst[2].id = "pipe"; in qcom_pcie_get_resources_2_3_3()
830 res->rst[3].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_3_3()
831 res->rst[4].id = "sticky"; in qcom_pcie_get_resources_2_3_3()
832 res->rst[5].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
833 res->rst[6].id = "sleep"; in qcom_pcie_get_resources_2_3_3()
835 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_get_resources_2_3_3()
842 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_3() argument
844 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
846 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_3_3()
849 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_3() argument
851 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
852 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
853 struct device *dev = pci->dev; in qcom_pcie_init_2_3_3()
856 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
864 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
876 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_3_3()
889 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
894 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_3() argument
896 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
900 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
902 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
904 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_3_3()
909 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
910 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
912 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
916 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
918 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
920 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
922 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
930 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_7_0() argument
932 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
933 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
934 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_7_0()
937 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_7_0()
938 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_7_0()
939 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_7_0()
941 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_7_0()
942 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_7_0()
943 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_7_0()
944 res->supplies); in qcom_pcie_get_resources_2_7_0()
948 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_7_0()
949 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_7_0()
951 return res->num_clks; in qcom_pcie_get_resources_2_7_0()
957 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_7_0() argument
959 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
960 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
961 struct device *dev = pci->dev; in qcom_pcie_init_2_7_0()
965 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
971 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
975 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_7_0()
983 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_7_0()
992 /* configure PCIe to RC mode */ in qcom_pcie_init_2_7_0()
993 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
995 /* enable PCIe clocks and resets */ in qcom_pcie_init_2_7_0()
996 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
998 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
1000 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_init_2_7_0()
1003 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
1005 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
1007 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
1009 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
1012 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
1014 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
1016 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1018 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1022 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
1024 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
1029 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_7_0() argument
1031 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; in qcom_pcie_post_init_2_7_0()
1033 if (pcie_cfg->override_no_snoop) in qcom_pcie_post_init_2_7_0()
1035 pcie->parf + PARF_NO_SNOOP_OVERRIDE); in qcom_pcie_post_init_2_7_0()
1037 qcom_pcie_clear_aspm_l0s(pcie->pci); in qcom_pcie_post_init_2_7_0()
1038 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
1055 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_host_post_init_2_7_0() argument
1057 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_host_post_init_2_7_0()
1059 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); in qcom_pcie_host_post_init_2_7_0()
1062 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_7_0() argument
1064 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
1066 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_7_0()
1068 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_7_0()
1071 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) in qcom_pcie_config_sid_1_9_0() argument
1080 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
1081 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
1087 of_get_property(dev->of_node, "iommu-map", &size); in qcom_pcie_config_sid_1_9_0()
1092 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1094 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1098 return -ENOMEM; in qcom_pcie_config_sid_1_9_0()
1100 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, in qcom_pcie_config_sid_1_9_0()
1110 /* Extract the SMMU SID base from the first entry of iommu-map */ in qcom_pcie_config_sid_1_9_0()
1138 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; in qcom_pcie_config_sid_1_9_0()
1147 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_9_0() argument
1149 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1150 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1151 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_9_0()
1153 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); in qcom_pcie_get_resources_2_9_0()
1154 if (res->num_clks < 0) { in qcom_pcie_get_resources_2_9_0()
1156 return res->num_clks; in qcom_pcie_get_resources_2_9_0()
1159 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_9_0()
1160 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_9_0()
1161 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_9_0()
1166 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_9_0() argument
1168 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1170 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_9_0()
1173 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_9_0() argument
1175 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1176 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1179 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_9_0()
1191 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_9_0()
1199 return clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_9_0()
1202 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_9_0() argument
1204 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1209 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1211 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1213 qcom_pcie_configure_dbi_atu_base(pcie); in qcom_pcie_post_init_2_9_0()
1215 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1217 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1220 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()
1225 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1227 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1231 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_9_0()
1233 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1235 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1237 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_9_0()
1243 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1251 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1256 static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) in qcom_pcie_phy_exit() argument
1260 if (list_empty(&pcie->ports)) in qcom_pcie_phy_exit()
1261 phy_exit(pcie->phy); in qcom_pcie_phy_exit()
1263 list_for_each_entry(port, &pcie->ports, list) in qcom_pcie_phy_exit()
1264 phy_exit(port->phy); in qcom_pcie_phy_exit()
1267 static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) in qcom_pcie_phy_power_off() argument
1271 if (list_empty(&pcie->ports)) { in qcom_pcie_phy_power_off()
1272 phy_power_off(pcie->phy); in qcom_pcie_phy_power_off()
1274 list_for_each_entry(port, &pcie->ports, list) in qcom_pcie_phy_power_off()
1275 phy_power_off(port->phy); in qcom_pcie_phy_power_off()
1279 static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) in qcom_pcie_phy_power_on() argument
1284 if (list_empty(&pcie->ports)) { in qcom_pcie_phy_power_on()
1285 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_phy_power_on()
1289 ret = phy_power_on(pcie->phy); in qcom_pcie_phy_power_on()
1293 list_for_each_entry(port, &pcie->ports, list) { in qcom_pcie_phy_power_on()
1294 ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_phy_power_on()
1298 ret = phy_power_on(port->phy); in qcom_pcie_phy_power_on()
1300 qcom_pcie_phy_power_off(pcie); in qcom_pcie_phy_power_on()
1312 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_init() local
1315 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1317 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1321 ret = qcom_pcie_phy_power_on(pcie); in qcom_pcie_host_init()
1325 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1326 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1331 qcom_ep_reset_deassert(pcie); in qcom_pcie_host_init()
1333 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1334 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1342 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1344 qcom_pcie_phy_power_off(pcie); in qcom_pcie_host_init()
1346 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1354 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_deinit() local
1356 qcom_ep_reset_assert(pcie); in qcom_pcie_host_deinit()
1357 qcom_pcie_phy_power_off(pcie); in qcom_pcie_host_deinit()
1358 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1364 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_post_init() local
1366 if (pcie->cfg->ops->host_post_init) in qcom_pcie_host_post_init()
1367 pcie->cfg->ops->host_post_init(pcie); in qcom_pcie_host_post_init()
1511 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) in qcom_pcie_icc_init() argument
1513 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1516 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1517 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1518 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1520 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); in qcom_pcie_icc_init()
1521 if (IS_ERR(pcie->icc_cpu)) in qcom_pcie_icc_init()
1522 return PTR_ERR(pcie->icc_cpu); in qcom_pcie_icc_init()
1527 * Set an initial peak bandwidth corresponding to single-lane Gen 1 in qcom_pcie_icc_init()
1528 * for the pcie-mem path. in qcom_pcie_icc_init()
1530 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); in qcom_pcie_icc_init()
1532 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_init()
1538 * Since the CPU-PCIe path is only used for activities like register in qcom_pcie_icc_init()
1543 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); in qcom_pcie_icc_init()
1545 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", in qcom_pcie_icc_init()
1547 icc_set_bw(pcie->icc_mem, 0, 0); in qcom_pcie_icc_init()
1554 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) in qcom_pcie_icc_opp_update() argument
1557 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_opp_update()
1563 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_icc_opp_update()
1572 if (pcie->icc_mem) { in qcom_pcie_icc_opp_update()
1573 ret = icc_set_bw(pcie->icc_mem, 0, in qcom_pcie_icc_opp_update()
1576 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_icc_opp_update()
1579 } else if (pcie->use_pm_opp) { in qcom_pcie_icc_opp_update()
1585 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, in qcom_pcie_icc_opp_update()
1588 ret = dev_pm_opp_set_opp(pci->dev, opp); in qcom_pcie_icc_opp_update()
1590 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", in qcom_pcie_icc_opp_update()
1599 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count() local
1602 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1605 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1608 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1611 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1614 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1619 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) in qcom_pcie_init_debugfs() argument
1621 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1622 struct device *dev = pci->dev; in qcom_pcie_init_debugfs()
1625 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in qcom_pcie_init_debugfs()
1629 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1630 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1636 struct qcom_pcie *pcie = data; in qcom_pcie_global_irq_thread() local
1637 struct dw_pcie_rp *pp = &pcie->pci->pp; in qcom_pcie_global_irq_thread()
1638 struct device *dev = pcie->pci->dev; in qcom_pcie_global_irq_thread()
1639 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); in qcom_pcie_global_irq_thread()
1641 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); in qcom_pcie_global_irq_thread()
1648 pci_rescan_bus(pp->bridge->bus); in qcom_pcie_global_irq_thread()
1651 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_global_irq_thread()
1664 if (pp && pp->has_msi_ctrl) in qcom_pci_free_msi()
1670 struct device *dev = cfg->parent; in qcom_pcie_ecam_host_init()
1677 return -ENOMEM; in qcom_pcie_ecam_host_init()
1679 pci->dev = dev; in qcom_pcie_ecam_host_init()
1680 pp = &pci->pp; in qcom_pcie_ecam_host_init()
1681 pci->dbi_base = cfg->win; in qcom_pcie_ecam_host_init()
1682 pp->num_vectors = MSI_DEF_NUM_VECTORS; in qcom_pcie_ecam_host_init()
1688 pp->has_msi_ctrl = true; in qcom_pcie_ecam_host_init()
1703 static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node) in qcom_pcie_parse_port() argument
1705 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_port()
1722 return -ENOMEM; in qcom_pcie_parse_port()
1728 port->reset = reset; in qcom_pcie_parse_port()
1729 port->phy = phy; in qcom_pcie_parse_port()
1730 INIT_LIST_HEAD(&port->list); in qcom_pcie_parse_port()
1731 list_add_tail(&port->list, &pcie->ports); in qcom_pcie_parse_port()
1736 static int qcom_pcie_parse_ports(struct qcom_pcie *pcie) in qcom_pcie_parse_ports() argument
1738 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_ports()
1740 int ret = -ENOENT; in qcom_pcie_parse_ports()
1742 for_each_available_child_of_node_scoped(dev->of_node, of_port) { in qcom_pcie_parse_ports()
1743 ret = qcom_pcie_parse_port(pcie, of_port); in qcom_pcie_parse_ports()
1751 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in qcom_pcie_parse_ports()
1752 list_del(&port->list); in qcom_pcie_parse_ports()
1757 static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) in qcom_pcie_parse_legacy_binding() argument
1759 struct device *dev = pcie->pci->dev; in qcom_pcie_parse_legacy_binding()
1762 pcie->phy = devm_phy_optional_get(dev, "pciephy"); in qcom_pcie_parse_legacy_binding()
1763 if (IS_ERR(pcie->phy)) in qcom_pcie_parse_legacy_binding()
1764 return PTR_ERR(pcie->phy); in qcom_pcie_parse_legacy_binding()
1766 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); in qcom_pcie_parse_legacy_binding()
1767 if (IS_ERR(pcie->reset)) in qcom_pcie_parse_legacy_binding()
1768 return PTR_ERR(pcie->reset); in qcom_pcie_parse_legacy_binding()
1770 ret = phy_init(pcie->phy); in qcom_pcie_parse_legacy_binding()
1782 struct device *dev = &pdev->dev; in qcom_pcie_probe()
1784 struct qcom_pcie *pcie; in qcom_pcie_probe() local
1794 return -ENODATA; in qcom_pcie_probe()
1797 if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) { in qcom_pcie_probe()
1799 return -ENODATA; in qcom_pcie_probe()
1807 if (pcie_cfg->firmware_managed) { in qcom_pcie_probe()
1813 ret = -ENOMEM; in qcom_pcie_probe()
1825 bridge->sysdata = cfg; in qcom_pcie_probe()
1826 bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops; in qcom_pcie_probe()
1827 bridge->msi_domain = true; in qcom_pcie_probe()
1836 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in qcom_pcie_probe()
1837 if (!pcie) { in qcom_pcie_probe()
1838 ret = -ENOMEM; in qcom_pcie_probe()
1844 ret = -ENOMEM; in qcom_pcie_probe()
1848 INIT_LIST_HEAD(&pcie->ports); in qcom_pcie_probe()
1850 pci->dev = dev; in qcom_pcie_probe()
1851 pci->ops = &dw_pcie_ops; in qcom_pcie_probe()
1852 pp = &pci->pp; in qcom_pcie_probe()
1854 pcie->pci = pci; in qcom_pcie_probe()
1856 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1858 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1859 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1860 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1864 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); in qcom_pcie_probe()
1865 if (IS_ERR(pcie->elbi)) { in qcom_pcie_probe()
1866 ret = PTR_ERR(pcie->elbi); in qcom_pcie_probe()
1873 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1874 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1875 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1882 if (ret && ret != -ENODEV) { in qcom_pcie_probe()
1888 * Before the PCIe link is initialized, vote for highest OPP in the OPP in qcom_pcie_probe()
1897 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1906 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1912 pcie->use_pm_opp = true; in qcom_pcie_probe()
1915 ret = qcom_pcie_icc_init(pcie); in qcom_pcie_probe()
1920 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1924 pp->ops = &qcom_pcie_dw_ops; in qcom_pcie_probe()
1926 ret = qcom_pcie_parse_ports(pcie); in qcom_pcie_probe()
1928 if (ret != -ENOENT) { in qcom_pcie_probe()
1929 dev_err_probe(pci->dev, ret, in qcom_pcie_probe()
1939 ret = qcom_pcie_parse_legacy_binding(pcie); in qcom_pcie_probe()
1944 platform_set_drvdata(pdev, pcie); in qcom_pcie_probe()
1948 pp->use_linkup_irq = true; in qcom_pcie_probe()
1957 pci_domain_nr(pp->bridge->bus)); in qcom_pcie_probe()
1959 ret = -ENOMEM; in qcom_pcie_probe()
1964 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in qcom_pcie_probe()
1966 IRQF_ONESHOT, name, pcie); in qcom_pcie_probe()
1968 dev_err_probe(&pdev->dev, ret, in qcom_pcie_probe()
1974 pcie->parf + PARF_INT_ALL_MASK); in qcom_pcie_probe()
1977 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_probe()
1979 if (pcie->mhi) in qcom_pcie_probe()
1980 qcom_pcie_init_debugfs(pcie); in qcom_pcie_probe()
1987 qcom_pcie_phy_exit(pcie); in qcom_pcie_probe()
1988 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in qcom_pcie_probe()
1989 list_del(&port->list); in qcom_pcie_probe()
1999 struct qcom_pcie *pcie; in qcom_pcie_suspend_noirq() local
2002 pcie = dev_get_drvdata(dev); in qcom_pcie_suspend_noirq()
2003 if (!pcie) in qcom_pcie_suspend_noirq()
2010 if (pcie->icc_mem) { in qcom_pcie_suspend_noirq()
2011 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
2014 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", in qcom_pcie_suspend_noirq()
2021 * Turn OFF the resources only for controllers without active PCIe in qcom_pcie_suspend_noirq()
2025 * Turning OFF the resources for controllers with active PCIe devices in qcom_pcie_suspend_noirq()
2027 * as kernel tries to access the PCIe devices config space for masking in qcom_pcie_suspend_noirq()
2035 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
2036 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
2037 pcie->suspended = true; in qcom_pcie_suspend_noirq()
2041 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. in qcom_pcie_suspend_noirq()
2043 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC in qcom_pcie_suspend_noirq()
2047 ret = icc_disable(pcie->icc_cpu); in qcom_pcie_suspend_noirq()
2049 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_suspend_noirq()
2051 if (pcie->use_pm_opp) in qcom_pcie_suspend_noirq()
2052 dev_pm_opp_set_opp(pcie->pci->dev, NULL); in qcom_pcie_suspend_noirq()
2059 struct qcom_pcie *pcie; in qcom_pcie_resume_noirq() local
2062 pcie = dev_get_drvdata(dev); in qcom_pcie_resume_noirq()
2063 if (!pcie) in qcom_pcie_resume_noirq()
2067 ret = icc_enable(pcie->icc_cpu); in qcom_pcie_resume_noirq()
2069 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); in qcom_pcie_resume_noirq()
2074 if (pcie->suspended) { in qcom_pcie_resume_noirq()
2075 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
2079 pcie->suspended = false; in qcom_pcie_resume_noirq()
2082 qcom_pcie_icc_opp_update(pcie); in qcom_pcie_resume_noirq()
2088 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
2089 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
2090 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
2091 { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
2092 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
2093 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
2094 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
2095 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
2096 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
2097 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
2098 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
2099 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
2100 { .compatible = "qcom,pcie-sa8255p", .data = &cfg_fw_managed },
2101 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
2102 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
2103 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
2104 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
2105 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
2106 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
2107 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
2108 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
2109 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
2110 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
2111 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
2112 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
2113 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
2114 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
2120 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in qcom_fixup_class()
2137 .name = "qcom-pcie",