43 /* PARF registers */
292 	void __iomem *parf;			/* DT parf */  member
336 	writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);  in qcom_pci_config_ecam()
337 	writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);  in qcom_pci_config_ecam()
351 	writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);  in qcom_pci_config_ecam()
352 	writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);  in qcom_pci_config_ecam()
354 	writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);  in qcom_pci_config_ecam()
355 	writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);  in qcom_pci_config_ecam()
359 	writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);  in qcom_pci_config_ecam()
360 	writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);  in qcom_pci_config_ecam()
362 	writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);  in qcom_pci_config_ecam()
363 	writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);  in qcom_pci_config_ecam()
365 	val = readl_relaxed(pcie->parf + PARF_SYS_CTRL);  in qcom_pci_config_ecam()
367 	writel_relaxed(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pci_config_ecam()
429 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_base()
431 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_base()
446 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
448 		writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
452 			writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
454 			writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
458 		writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);  in qcom_pcie_configure_dbi_atu_base()
459 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
524 	writel(1, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
569 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
571 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
582 		       pcie->parf + PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
585 		       pcie->parf + PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
586 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
591 		val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
594 		writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
598 	val = readl(pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
603 	writel(val, pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
688 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
691 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
704 	val = readl(pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
706 	writel(val, pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
768 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
770 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
775 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
777 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
779 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
781 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
783 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
785 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
815 	res->resets[9].id = "parf";  in qcom_pcie_get_resources_2_4_0()
954 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
956 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
963 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
964 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
1047 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
1050 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1052 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
1057 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1059 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
1061 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1063 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
1066 	val = readl(pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1068 	writel(val, pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
1070 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
1072 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
1089 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);  in qcom_pcie_post_init_2_7_0()
1115 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_1_9_0()
1127 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1129 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1244 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1246 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1250 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1252 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1260 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1262 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1278 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1337 		offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));  in qcom_pcie_host_init()
1649 	u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);  in qcom_pcie_global_irq_thread()
1651 	writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);  in qcom_pcie_global_irq_thread()
1884 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1885 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1886 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()
1994 			       pcie->parf + PARF_INT_ALL_MASK);  in qcom_pcie_probe()