1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT	(SZ_128 - 1)
68 	struct clk		*core_clk;
86 	writel(val, pcie->app_base + ofs);  in pcie_app_wr()
92 	pcie_update_bits(pcie->app_base, ofs, mask, val);  in pcie_app_wr_mask()
97 	return dw_pcie_readl_dbi(&pcie->pci, ofs);  in pcie_rc_cfg_rd()
102 	dw_pcie_writel_dbi(&pcie->pci, ofs, val);  in pcie_rc_cfg_wr()
108 	pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val);  in pcie_rc_cfg_wr_mask()
125 	u8 offset = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP);  in intel_pcie_link_setup()
135 	switch (pci->max_link_speed) {  in intel_pcie_init_n_fts()
137 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;  in intel_pcie_init_n_fts()
140 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN4;  in intel_pcie_init_n_fts()
143 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
146 	pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
151 	struct device *dev = pcie->pci.dev;  in intel_pcie_ep_rst_init()
154 	pcie->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);  in intel_pcie_ep_rst_init()
155 	if (IS_ERR(pcie->reset_gpio)) {  in intel_pcie_ep_rst_init()
156 		ret = PTR_ERR(pcie->reset_gpio);  in intel_pcie_ep_rst_init()
157 		if (ret != -EPROBE_DEFER)  in intel_pcie_ep_rst_init()
170 	reset_control_assert(pcie->core_rst);  in intel_pcie_core_rst_assert()
176 	 * One micro-second delay to make sure the reset pulse  in intel_pcie_core_rst_deassert()
180 	reset_control_deassert(pcie->core_rst);  in intel_pcie_core_rst_deassert()
191 	gpiod_set_value_cansleep(pcie->reset_gpio, 1);  in intel_pcie_device_rst_assert()
196 	msleep(pcie->rst_intrvl);  in intel_pcie_device_rst_deassert()
197 	gpiod_set_value_cansleep(pcie->reset_gpio, 0);  in intel_pcie_device_rst_deassert()
209 	struct dw_pcie *pci = &pcie->pci;  in intel_pcie_get_resources()
210 	struct device *dev = pci->dev;  in intel_pcie_get_resources()
213 	pcie->core_clk = devm_clk_get(dev, NULL);  in intel_pcie_get_resources()
214 	if (IS_ERR(pcie->core_clk)) {  in intel_pcie_get_resources()
215 		ret = PTR_ERR(pcie->core_clk);  in intel_pcie_get_resources()
216 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
221 	pcie->core_rst = devm_reset_control_get(dev, NULL);  in intel_pcie_get_resources()
222 	if (IS_ERR(pcie->core_rst)) {  in intel_pcie_get_resources()
223 		ret = PTR_ERR(pcie->core_rst);  in intel_pcie_get_resources()
224 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
229 	ret = device_property_read_u32(dev, "reset-assert-ms",  in intel_pcie_get_resources()
230 				       &pcie->rst_intrvl);  in intel_pcie_get_resources()
232 		pcie->rst_intrvl = RESET_INTERVAL_MS;  in intel_pcie_get_resources()
234 	pcie->app_base = devm_platform_ioremap_resource_byname(pdev, "app");  in intel_pcie_get_resources()
235 	if (IS_ERR(pcie->app_base))  in intel_pcie_get_resources()
236 		return PTR_ERR(pcie->app_base);  in intel_pcie_get_resources()
238 	pcie->phy = devm_phy_get(dev, "pcie");  in intel_pcie_get_resources()
239 	if (IS_ERR(pcie->phy)) {  in intel_pcie_get_resources()
240 		ret = PTR_ERR(pcie->phy);  in intel_pcie_get_resources()
241 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
242 			dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);  in intel_pcie_get_resources()
253 	struct dw_pcie *pci = &pcie->pci;  in intel_pcie_wait_l2()
255 	if (pci->max_link_speed < 3)  in intel_pcie_wait_l2()
263 	ret = readl_poll_timeout(pcie->app_base + PCIE_APP_PMC, value,  in intel_pcie_wait_l2()
267 		dev_err(pcie->pci.dev, "PCIe link enter L2 timeout!\n");  in intel_pcie_wait_l2()
274 	if (dw_pcie_link_up(&pcie->pci))  in intel_pcie_turn_off()
285 	struct dw_pcie *pci = &pcie->pci;  in intel_pcie_host_setup()
290 	ret = phy_init(pcie->phy);  in intel_pcie_host_setup()
296 	ret = clk_prepare_enable(pcie->core_clk);  in intel_pcie_host_setup()
298 		dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);  in intel_pcie_host_setup()
302 	pci->atu_base = pci->dbi_base + 0xC0000;  in intel_pcie_host_setup()
308 	ret = dw_pcie_setup_rc(&pci->pp);  in intel_pcie_host_setup()
328 	clk_disable_unprepare(pcie->core_clk);  in intel_pcie_host_setup()
331 	phy_exit(pcie->phy);  in intel_pcie_host_setup()
340 	clk_disable_unprepare(pcie->core_clk);  in __intel_pcie_remove()
342 	phy_exit(pcie->phy);  in __intel_pcie_remove()
348 	struct dw_pcie_rp *pp = &pcie->pci.pp;  in intel_pcie_remove()
364 	phy_exit(pcie->phy);  in intel_pcie_suspend_noirq()
365 	clk_disable_unprepare(pcie->core_clk);  in intel_pcie_suspend_noirq()
379 	struct intel_pcie *pcie = dev_get_drvdata(pci->dev);  in intel_pcie_rc_init()
399 	struct device *dev = &pdev->dev;  in intel_pcie_probe()
407 		return -ENOMEM;  in intel_pcie_probe()
410 	pci = &pcie->pci;  in intel_pcie_probe()
411 	pci->dev = dev;  in intel_pcie_probe()
412 	pp = &pci->pp;  in intel_pcie_probe()
422 	pci->ops = &intel_pcie_ops;  in intel_pcie_probe()
423 	pp->ops = &intel_pcie_dw_ops;  in intel_pcie_probe()
440 	{ .compatible = "intel,lgm-pcie" },
448 		.name = "intel-gw-pcie",