34 	void __iomem *mgmt_base;  member
85 	writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);  in fu740_pcie_assert_reset()
91 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);  in fu740_pcie_deassert_reset()
126 		phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;  in fu740_phyregwrite()
127 		phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;  in fu740_phyregwrite()
128 		phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;  in fu740_phyregwrite()
129 		phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;  in fu740_phyregwrite()
131 		phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;  in fu740_phyregwrite()
132 		phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;  in fu740_phyregwrite()
133 		phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;  in fu740_phyregwrite()
134 		phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;  in fu740_phyregwrite()
158 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);  in fu740_pcie_init_phy()
159 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);  in fu740_pcie_init_phy()
203 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);  in fu740_pcie_start_link()
258 	writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);  in fu740_pcie_host_init()
272 	writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);  in fu740_pcie_host_init()
276 	writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);  in fu740_pcie_host_init()
305 	afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");  in fu740_pcie_probe()
306 	if (IS_ERR(afp->mgmt_base))  in fu740_pcie_probe()
307 		return PTR_ERR(afp->mgmt_base);  in fu740_pcie_probe()