Lines Matching +full:max +full:- +full:retries
1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pcie-dwc.h>
26 #include "pcie-designware.h"
48 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
70 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
73 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
76 pci->app_clks); in dw_pcie_get_clocks()
80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, in dw_pcie_get_clocks()
81 pci->core_clks); in dw_pcie_get_clocks()
89 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; in dw_pcie_get_resets()
92 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; in dw_pcie_get_resets()
94 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, in dw_pcie_get_resets()
96 pci->app_rsts); in dw_pcie_get_resets()
100 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, in dw_pcie_get_resets()
102 pci->core_rsts); in dw_pcie_get_resets()
106 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); in dw_pcie_get_resets()
107 if (IS_ERR(pci->pe_rst)) in dw_pcie_get_resets()
108 return PTR_ERR(pci->pe_rst); in dw_pcie_get_resets()
115 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_get_resources()
116 struct device_node *np = dev_of_node(pci->dev); in dw_pcie_get_resources()
120 if (!pci->dbi_base) { in dw_pcie_get_resources()
122 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
123 if (IS_ERR(pci->dbi_base)) in dw_pcie_get_resources()
124 return PTR_ERR(pci->dbi_base); in dw_pcie_get_resources()
125 pci->dbi_phys_addr = res->start; in dw_pcie_get_resources()
129 if (!pci->dbi_base2) { in dw_pcie_get_resources()
132 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); in dw_pcie_get_resources()
133 if (IS_ERR(pci->dbi_base2)) in dw_pcie_get_resources()
134 return PTR_ERR(pci->dbi_base2); in dw_pcie_get_resources()
136 pci->dbi_base2 = pci->dbi_base + SZ_4K; in dw_pcie_get_resources()
140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
141 if (!pci->atu_base) { in dw_pcie_get_resources()
144 pci->atu_size = resource_size(res); in dw_pcie_get_resources()
145 pci->atu_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
146 if (IS_ERR(pci->atu_base)) in dw_pcie_get_resources()
147 return PTR_ERR(pci->atu_base); in dw_pcie_get_resources()
148 pci->atu_phys_addr = res->start; in dw_pcie_get_resources()
150 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_get_resources()
155 if (!pci->atu_size) in dw_pcie_get_resources()
156 pci->atu_size = SZ_4K; in dw_pcie_get_resources()
159 if (!pci->edma.reg_base) { in dw_pcie_get_resources()
162 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
163 if (IS_ERR(pci->edma.reg_base)) in dw_pcie_get_resources()
164 return PTR_ERR(pci->edma.reg_base); in dw_pcie_get_resources()
165 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { in dw_pcie_get_resources()
166 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; in dw_pcie_get_resources()
173 pci->elbi_base = devm_ioremap_resource(pci->dev, res); in dw_pcie_get_resources()
174 if (IS_ERR(pci->elbi_base)) in dw_pcie_get_resources()
175 return PTR_ERR(pci->elbi_base); in dw_pcie_get_resources()
189 if (pci->max_link_speed < 1) in dw_pcie_get_resources()
190 pci->max_link_speed = of_pci_get_max_link_speed(np); in dw_pcie_get_resources()
192 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_get_resources()
194 if (of_property_read_bool(np, "snps,enable-cdm-check")) in dw_pcie_get_resources()
209 if (pci->version && pci->version != ver) in dw_pcie_version_detect()
210 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", in dw_pcie_version_detect()
211 pci->version, ver); in dw_pcie_version_detect()
213 pci->version = ver; in dw_pcie_version_detect()
217 if (pci->type && pci->type != ver) in dw_pcie_version_detect()
218 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", in dw_pcie_version_detect()
219 pci->type, ver); in dw_pcie_version_detect()
221 pci->type = ver; in dw_pcie_version_detect()
263 for (vid = vsec_ids; vid->vendor_id; vid++) { in dw_pcie_find_vsec_capability()
264 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, in dw_pcie_find_vsec_capability()
265 vid->vsec_id); in dw_pcie_find_vsec_capability()
268 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) in dw_pcie_find_vsec_capability()
333 if (pci->ops && pci->ops->read_dbi) in dw_pcie_read_dbi()
334 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
336 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
338 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
348 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_write_dbi()
349 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
353 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
355 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
363 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
364 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
368 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
370 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
378 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); in dw_pcie_select_atu()
381 return pci->atu_base; in dw_pcie_select_atu()
392 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_atu()
393 return pci->ops->read_dbi(pci, base, reg, 4); in dw_pcie_readl_atu()
397 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
410 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_writel_atu()
411 pci->ops->write_dbi(pci, base, reg, 4, val); in dw_pcie_writel_atu()
417 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
435 * bit in the Control register-1 of the ATU outbound region acts in dw_pcie_enable_ecrc()
454 * on Root Port:- TLP Digest (DWord size) gets appended to each packet in dw_pcie_enable_ecrc()
459 * on End Point:- TLP Digest is received for some/all the packets coming in dw_pcie_enable_ecrc()
475 u64 parent_bus_addr = atu->parent_bus_addr; in dw_pcie_prog_outbound_atu()
476 u32 retries, val; in dw_pcie_prog_outbound_atu() local
479 limit_addr = parent_bus_addr + atu->size - 1; in dw_pcie_prog_outbound_atu()
481 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || in dw_pcie_prog_outbound_atu()
482 !IS_ALIGNED(parent_bus_addr, pci->region_align) || in dw_pcie_prog_outbound_atu()
483 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { in dw_pcie_prog_outbound_atu()
484 return -EINVAL; in dw_pcie_prog_outbound_atu()
487 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, in dw_pcie_prog_outbound_atu()
489 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, in dw_pcie_prog_outbound_atu()
492 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, in dw_pcie_prog_outbound_atu()
495 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, in dw_pcie_prog_outbound_atu()
498 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, in dw_pcie_prog_outbound_atu()
499 lower_32_bits(atu->pci_addr)); in dw_pcie_prog_outbound_atu()
500 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, in dw_pcie_prog_outbound_atu()
501 upper_32_bits(atu->pci_addr)); in dw_pcie_prog_outbound_atu()
503 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); in dw_pcie_prog_outbound_atu()
509 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); in dw_pcie_prog_outbound_atu()
511 val = PCIE_ATU_ENABLE | atu->ctrl2; in dw_pcie_prog_outbound_atu()
512 if (atu->type == PCIE_ATU_TYPE_MSG) { in dw_pcie_prog_outbound_atu()
513 /* The data-less messages only for now */ in dw_pcie_prog_outbound_atu()
514 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; in dw_pcie_prog_outbound_atu()
516 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); in dw_pcie_prog_outbound_atu()
522 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { in dw_pcie_prog_outbound_atu()
523 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); in dw_pcie_prog_outbound_atu()
530 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu()
532 return -ETIMEDOUT; in dw_pcie_prog_outbound_atu()
549 u64 limit_addr = pci_addr + size - 1; in dw_pcie_prog_inbound_atu()
550 u32 retries, val; in dw_pcie_prog_inbound_atu() local
552 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || in dw_pcie_prog_inbound_atu()
553 !IS_ALIGNED(parent_bus_addr, pci->region_align) || in dw_pcie_prog_inbound_atu()
554 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { in dw_pcie_prog_inbound_atu()
555 return -EINVAL; in dw_pcie_prog_inbound_atu()
585 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { in dw_pcie_prog_inbound_atu()
593 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
595 return -ETIMEDOUT; in dw_pcie_prog_inbound_atu()
601 u32 retries, val; in dw_pcie_prog_ep_inbound_atu() local
603 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) || in dw_pcie_prog_ep_inbound_atu()
605 return -EINVAL; in dw_pcie_prog_ep_inbound_atu()
622 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { in dw_pcie_prog_ep_inbound_atu()
630 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
632 return -ETIMEDOUT; in dw_pcie_prog_ep_inbound_atu()
643 int retries; in dw_pcie_wait_for_link() local
646 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { in dw_pcie_wait_for_link()
653 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { in dw_pcie_wait_for_link()
654 dev_info(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
655 return -ETIMEDOUT; in dw_pcie_wait_for_link()
663 if (pci->max_link_speed > 2) in dw_pcie_wait_for_link()
669 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", in dw_pcie_wait_for_link()
681 if (pci->ops && pci->ops->link_up) in dw_pcie_link_up()
682 return pci->ops->link_up(pci); in dw_pcie_link_up()
712 if (pci->max_link_speed < 1) { in dw_pcie_link_set_max_speed()
713 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); in dw_pcie_link_set_max_speed()
720 switch (pcie_link_speed[pci->max_link_speed]) { in dw_pcie_link_set_max_speed()
789 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); in dw_pcie_link_set_max_link_width()
806 u64 max; in dw_pcie_iatu_detect() local
812 max_region = min((int)pci->atu_size / 512, 256); in dw_pcie_iatu_detect()
814 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; in dw_pcie_iatu_detect()
815 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; in dw_pcie_iatu_detect()
840 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
849 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); in dw_pcie_iatu_detect()
851 max = 0; in dw_pcie_iatu_detect()
854 pci->num_ob_windows = ob; in dw_pcie_iatu_detect()
855 pci->num_ib_windows = ib; in dw_pcie_iatu_detect()
856 pci->region_align = 1 << fls(min); in dw_pcie_iatu_detect()
857 pci->region_limit = (max << 32) | (SZ_4G - 1); in dw_pcie_iatu_detect()
859 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
861 pci->num_ob_windows, pci->num_ib_windows, in dw_pcie_iatu_detect()
862 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); in dw_pcie_iatu_detect()
870 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_dma()
871 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); in dw_pcie_readl_dma()
873 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); in dw_pcie_readl_dma()
875 dev_err(pci->dev, "Read DMA address failed\n"); in dw_pcie_readl_dma()
887 return -EINVAL; in dw_pcie_edma_irq_vector()
904 pci->edma.dev = pci->dev; in dw_pcie_edma_init_data()
906 if (!pci->edma.ops) in dw_pcie_edma_init_data()
907 pci->edma.ops = &dw_pcie_edma_ops; in dw_pcie_edma_init_data()
909 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; in dw_pcie_edma_init_data()
921 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) in dw_pcie_edma_find_mf()
922 return pci->edma.reg_base ? 0 : -ENODEV; in dw_pcie_edma_find_mf()
934 if (val == 0xFFFFFFFF && pci->edma.reg_base) { in dw_pcie_edma_find_mf()
935 pci->edma.mf = EDMA_MF_EDMA_UNROLL; in dw_pcie_edma_find_mf()
937 pci->edma.mf = EDMA_MF_EDMA_LEGACY; in dw_pcie_edma_find_mf()
939 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; in dw_pcie_edma_find_mf()
941 return -ENODEV; in dw_pcie_edma_find_mf()
952 * Autodetect the read/write channels count only for non-HDMA platforms. in dw_pcie_edma_find_channels()
957 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { in dw_pcie_edma_find_channels()
960 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); in dw_pcie_edma_find_channels()
961 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); in dw_pcie_edma_find_channels()
965 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || in dw_pcie_edma_find_channels()
966 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) in dw_pcie_edma_find_channels()
967 return -EINVAL; in dw_pcie_edma_find_channels()
987 struct platform_device *pdev = to_platform_device(pci->dev); in dw_pcie_edma_irq_verify()
988 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; in dw_pcie_edma_irq_verify()
992 if (pci->edma.nr_irqs > 1) in dw_pcie_edma_irq_verify()
993 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; in dw_pcie_edma_irq_verify()
997 pci->edma.nr_irqs = 1; in dw_pcie_edma_irq_verify()
1001 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { in dw_pcie_edma_irq_verify()
1002 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); in dw_pcie_edma_irq_verify()
1006 return -EINVAL; in dw_pcie_edma_irq_verify()
1018 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { in dw_pcie_edma_ll_alloc()
1019 ll = &pci->edma.ll_region_wr[i]; in dw_pcie_edma_ll_alloc()
1020 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
1021 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
1023 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
1024 return -ENOMEM; in dw_pcie_edma_ll_alloc()
1026 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
1029 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { in dw_pcie_edma_ll_alloc()
1030 ll = &pci->edma.ll_region_rd[i]; in dw_pcie_edma_ll_alloc()
1031 ll->sz = DMA_LLP_MEM_SIZE; in dw_pcie_edma_ll_alloc()
1032 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, in dw_pcie_edma_ll_alloc()
1034 if (!ll->vaddr.mem) in dw_pcie_edma_ll_alloc()
1035 return -ENOMEM; in dw_pcie_edma_ll_alloc()
1037 ll->paddr = paddr; in dw_pcie_edma_ll_alloc()
1055 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); in dw_pcie_edma_detect()
1061 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); in dw_pcie_edma_detect()
1066 ret = dw_edma_probe(&pci->edma); in dw_pcie_edma_detect()
1067 if (ret && ret != -ENODEV) { in dw_pcie_edma_detect()
1068 dev_err(pci->dev, "Couldn't register eDMA device\n"); in dw_pcie_edma_detect()
1072 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", in dw_pcie_edma_detect()
1073 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", in dw_pcie_edma_detect()
1074 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); in dw_pcie_edma_detect()
1081 dw_edma_remove(&pci->edma); in dw_pcie_edma_remove()
1091 if (pci->n_fts[0]) { in dw_pcie_setup()
1094 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
1095 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
1100 if (pci->n_fts[1]) { in dw_pcie_setup()
1103 val |= pci->n_fts[1]; in dw_pcie_setup()
1119 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); in dw_pcie_setup()
1126 struct device *dev = pci->dev; in dw_pcie_parent_bus_offset()
1127 struct device_node *np = dev->of_node; in dw_pcie_parent_bus_offset()
1133 index = of_property_match_string(np, "reg-names", reg_name); in dw_pcie_parent_bus_offset()
1142 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL; in dw_pcie_parent_bus_offset()
1156 return cpu_phys_addr - reg_addr; in dw_pcie_parent_bus_offset()
1159 if (pci->use_parent_dt_ranges) { in dw_pcie_parent_bus_offset()
1179 return cpu_phys_addr - reg_addr; in dw_pcie_parent_bus_offset()