Lines Matching +full:bt1 +full:- +full:ccu
1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 PCIe controller driver
26 #include "pcie-designware.h"
28 /* Baikal-T1 System CCU control registers */
114 /* Baikal-T1 PCIe specific control registers */
130 /* Generic Baikal-T1 PCIe interface resources */
169 * Baikal-T1 MMIO space must be read/written by the dword-aligned
178 return -EINVAL; in bt1_pcie_read_mmio()
180 *val = readl(addr - ofs) >> ofs * BITS_PER_BYTE; in bt1_pcie_read_mmio()
191 return -EINVAL; in bt1_pcie_read_mmio()
200 return -EINVAL; in bt1_pcie_write_mmio()
206 mask = GENMASK(size * BITS_PER_BYTE - 1, 0); in bt1_pcie_write_mmio()
207 tmp = readl(addr - ofs) & ~(mask << ofs * BITS_PER_BYTE); in bt1_pcie_write_mmio()
209 writel(tmp, addr - ofs); in bt1_pcie_write_mmio()
213 return -EINVAL; in bt1_pcie_write_mmio()
224 dev_err(pci->dev, "Read DBI address failed\n"); in bt1_pcie_read_dbi()
238 dev_err(pci->dev, "Write DBI address failed\n"); in bt1_pcie_write_dbi()
247 regmap_update_bits(btpci->sys_regs, BT1_CCU_PCIE_GENC, in bt1_pcie_write_dbi2()
252 dev_err(pci->dev, "Write DBI2 address failed\n"); in bt1_pcie_write_dbi2()
254 regmap_update_bits(btpci->sys_regs, BT1_CCU_PCIE_GENC, in bt1_pcie_write_dbi2()
268 regmap_update_bits(btpci->sys_regs, BT1_CCU_PCIE_GENC, in bt1_pcie_start_link()
271 ret = regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_PMSC, val, in bt1_pcie_start_link()
275 dev_err(pci->dev, "LTSSM failed to set PHY link up\n"); in bt1_pcie_start_link()
279 ret = regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_PMSC, val, in bt1_pcie_start_link()
283 dev_err(pci->dev, "LTSSM failed to set data link up\n"); in bt1_pcie_start_link()
289 * attempt to reach a higher bus performance (up to Gen.3 - 8.0 GT/s). in bt1_pcie_start_link()
296 ret = regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_PMSC, val, in bt1_pcie_start_link()
300 dev_err(pci->dev, "LTSSM failed to get into L0 state\n"); in bt1_pcie_start_link()
309 regmap_update_bits(btpci->sys_regs, BT1_CCU_PCIE_GENC, in bt1_pcie_stop_link()
329 struct device *dev = btpci->dw.dev; in bt1_pcie_get_resources()
332 /* DBI access is supposed to be performed by the dword-aligned IOs */ in bt1_pcie_get_resources()
333 btpci->dw.pp.bridge->ops = &bt1_pci_ops; in bt1_pcie_get_resources()
335 /* These CSRs are in MMIO so we won't check the regmap-methods status */ in bt1_pcie_get_resources()
336 btpci->sys_regs = in bt1_pcie_get_resources()
337 syscon_regmap_lookup_by_phandle(dev->of_node, "baikal,bt1-syscon"); in bt1_pcie_get_resources()
338 if (IS_ERR(btpci->sys_regs)) in bt1_pcie_get_resources()
339 return dev_err_probe(dev, PTR_ERR(btpci->sys_regs), in bt1_pcie_get_resources()
344 if (!btpci->dw.app_clks[bt1_pcie_app_clks[i]].clk) { in bt1_pcie_get_resources()
346 return -ENOENT; in bt1_pcie_get_resources()
351 if (!btpci->dw.core_clks[bt1_pcie_core_clks[i]].clk) { in bt1_pcie_get_resources()
353 return -ENOENT; in bt1_pcie_get_resources()
358 if (!btpci->dw.app_rsts[bt1_pcie_app_rsts[i]].rstc) { in bt1_pcie_get_resources()
360 return -ENOENT; in bt1_pcie_get_resources()
365 if (!btpci->dw.core_rsts[bt1_pcie_core_rsts[i]].rstc) { in bt1_pcie_get_resources()
367 return -ENOENT; in bt1_pcie_get_resources()
376 struct device *dev = btpci->dw.dev; in bt1_pcie_full_stop_bus()
377 struct dw_pcie *pci = &btpci->dw; in bt1_pcie_full_stop_bus()
381 regmap_update_bits(btpci->sys_regs, BT1_CCU_PCIE_GENC, in bt1_pcie_full_stop_bus()
385 * Application reset controls are trigger-based so assert the core in bt1_pcie_full_stop_bus()
388 ret = reset_control_bulk_assert(DW_PCIE_NUM_CORE_RSTS, pci->core_rsts); in bt1_pcie_full_stop_bus()
397 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, pci->core_clks); in bt1_pcie_full_stop_bus()
399 clk_bulk_disable_unprepare(DW_PCIE_NUM_APP_CLKS, pci->app_clks); in bt1_pcie_full_stop_bus()
403 gpiod_set_value_cansleep(pci->pe_rst, 1); in bt1_pcie_full_stop_bus()
415 struct device *dev = btpci->dw.dev; in bt1_pcie_cold_start_bus()
416 struct dw_pcie *pci = &btpci->dw; in bt1_pcie_cold_start_bus()
421 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_PWR_RST].rstc); in bt1_pcie_cold_start_bus()
427 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_HOT_RST].rstc); in bt1_pcie_cold_start_bus()
433 /* Wait for the PM-core to stop requesting the PHY reset */ in bt1_pcie_cold_start_bus()
434 ret = regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_RSTC, val, in bt1_pcie_cold_start_bus()
442 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_PHY_RST].rstc); in bt1_pcie_cold_start_bus()
449 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_APP_CLKS, pci->app_clks); in bt1_pcie_cold_start_bus()
455 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, pci->core_clks); in bt1_pcie_cold_start_bus()
462 ret = regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_RSTC, val, in bt1_pcie_cold_start_bus()
470 /* PCS-PIPE interface and controller core can be now activated */ in bt1_pcie_cold_start_bus()
471 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_PIPE_RST].rstc); in bt1_pcie_cold_start_bus()
477 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_CORE_RST].rstc); in bt1_pcie_cold_start_bus()
484 ret = reset_control_bulk_reset(DW_PCIE_NUM_APP_RSTS, pci->app_rsts); in bt1_pcie_cold_start_bus()
490 /* Sticky/Non-sticky CSR flags can be now unreset too */ in bt1_pcie_cold_start_bus()
491 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_STICKY_RST].rstc); in bt1_pcie_cold_start_bus()
497 ret = reset_control_deassert(pci->core_rsts[DW_PCIE_NON_STICKY_RST].rstc); in bt1_pcie_cold_start_bus()
499 dev_err(dev, "Failed to deassert non-sticky reset\n"); in bt1_pcie_cold_start_bus()
504 gpiod_set_value_cansleep(pci->pe_rst, 0); in bt1_pcie_cold_start_bus()
512 reset_control_assert(pci->core_rsts[DW_PCIE_STICKY_RST].rstc); in bt1_pcie_cold_start_bus()
515 reset_control_assert(pci->core_rsts[DW_PCIE_CORE_RST].rstc); in bt1_pcie_cold_start_bus()
518 reset_control_assert(pci->core_rsts[DW_PCIE_PIPE_RST].rstc); in bt1_pcie_cold_start_bus()
521 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, pci->core_clks); in bt1_pcie_cold_start_bus()
524 clk_bulk_disable_unprepare(DW_PCIE_NUM_APP_CLKS, pci->app_clks); in bt1_pcie_cold_start_bus()
527 reset_control_assert(pci->core_rsts[DW_PCIE_PHY_RST].rstc); in bt1_pcie_cold_start_bus()
530 reset_control_assert(pci->core_rsts[DW_PCIE_HOT_RST].rstc); in bt1_pcie_cold_start_bus()
533 reset_control_assert(pci->core_rsts[DW_PCIE_PWR_RST].rstc); in bt1_pcie_cold_start_bus()
570 btpci = devm_kzalloc(&pdev->dev, sizeof(*btpci), GFP_KERNEL); in bt1_pcie_create_data()
572 return ERR_PTR(-ENOMEM); in bt1_pcie_create_data()
574 btpci->pdev = pdev; in bt1_pcie_create_data()
583 struct device *dev = &btpci->pdev->dev; in bt1_pcie_add_port()
590 btpci->dw.version = DW_PCIE_VER_460A; in bt1_pcie_add_port()
591 btpci->dw.dev = dev; in bt1_pcie_add_port()
592 btpci->dw.ops = &bt1_pcie_ops; in bt1_pcie_add_port()
594 btpci->dw.pp.num_vectors = MAX_MSI_IRQS; in bt1_pcie_add_port()
595 btpci->dw.pp.ops = &bt1_pcie_host_ops; in bt1_pcie_add_port()
597 dw_pcie_cap_set(&btpci->dw, REQ_RES); in bt1_pcie_add_port()
599 ret = dw_pcie_host_init(&btpci->dw.pp); in bt1_pcie_add_port()
606 dw_pcie_host_deinit(&btpci->dw.pp); in bt1_pcie_del_port()
628 { .compatible = "baikal,bt1-pcie" },
637 .name = "bt1-pcie",
644 MODULE_DESCRIPTION("Baikal-T1 PCIe driver");