1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
25 	struct pci_config_window *cfg = bus->sysdata;  in al_pcie_map_bus()
26 	struct al_pcie_acpi *pcie = cfg->priv;  in al_pcie_map_bus()  local
27 	void __iomem *dbi_base = pcie->dbi_base;  in al_pcie_map_bus()
29 	if (bus->number == cfg->busr.start) {  in al_pcie_map_bus()
31 		 * The DW PCIe core doesn't filter out transactions to other  in al_pcie_map_bus()
45 	struct device *dev = cfg->parent;  in al_pcie_init()
54 		return -ENOMEM;  in al_pcie_init()
58 		return -ENOMEM;  in al_pcie_init()
60 	ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);  in al_pcie_init()
63 			root->segment);  in al_pcie_init()
69 	al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);  in al_pcie_init()
70 	if (IS_ERR(al_pcie->dbi_base))  in al_pcie_init()
71 		return PTR_ERR(al_pcie->dbi_base);  in al_pcie_init()
73 	cfg->priv = al_pcie;  in al_pcie_init()
92 #include "pcie-designware.h"
132 	void __iomem *controller_base; /* base of PCIe unit (not DW core) */
140 #define to_al_pcie(x)		dev_get_drvdata((x)->dev)
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)  in al_pcie_controller_readl()  argument
144 	return readl_relaxed(pcie->controller_base + offset);  in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,  in al_pcie_controller_writel()  argument
150 	writel_relaxed(val, pcie->controller_base + offset);  in al_pcie_controller_writel()
153 static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)  in al_pcie_rev_id_get()  argument
158 	dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +  in al_pcie_rev_id_get()
174 		dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",  in al_pcie_rev_id_get()
176 		return -EINVAL;  in al_pcie_rev_id_get()
179 	dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);  in al_pcie_rev_id_get()
184 static int al_pcie_reg_offsets_set(struct al_pcie *pcie)  in al_pcie_reg_offsets_set()  argument
186 	switch (pcie->controller_rev_id) {  in al_pcie_reg_offsets_set()
188 		pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;  in al_pcie_reg_offsets_set()
192 		pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;  in al_pcie_reg_offsets_set()
195 		dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",  in al_pcie_reg_offsets_set()
196 			pcie->controller_rev_id);  in al_pcie_reg_offsets_set()
197 		return -EINVAL;  in al_pcie_reg_offsets_set()
203 static inline void al_pcie_target_bus_set(struct al_pcie *pcie,  in al_pcie_target_bus_set()  argument
212 	al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +  in al_pcie_target_bus_set()
213 				  pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,  in al_pcie_target_bus_set()
220 	struct dw_pcie_rp *pp = bus->sysdata;  in al_pcie_conf_addr_map_bus()
221 	struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));  in al_pcie_conf_addr_map_bus()  local
222 	unsigned int busnr = bus->number;  in al_pcie_conf_addr_map_bus()
223 	struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;  in al_pcie_conf_addr_map_bus()
224 	unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;  in al_pcie_conf_addr_map_bus()
225 	unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;  in al_pcie_conf_addr_map_bus()
227 	if (busnr_reg != target_bus_cfg->reg_val) {  in al_pcie_conf_addr_map_bus()
228 		dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",  in al_pcie_conf_addr_map_bus()
229 			target_bus_cfg->reg_val, busnr_reg);  in al_pcie_conf_addr_map_bus()
230 		target_bus_cfg->reg_val = busnr_reg;  in al_pcie_conf_addr_map_bus()
231 		al_pcie_target_bus_set(pcie,  in al_pcie_conf_addr_map_bus()
232 				       target_bus_cfg->reg_val,  in al_pcie_conf_addr_map_bus()
233 				       target_bus_cfg->reg_mask);  in al_pcie_conf_addr_map_bus()
236 	return pp->va_cfg0_base + PCIE_ECAM_OFFSET(busnr_ecam, devfn, where);  in al_pcie_conf_addr_map_bus()
245 static int al_pcie_config_prepare(struct al_pcie *pcie)  in al_pcie_config_prepare()  argument
248 	struct dw_pcie_rp *pp = &pcie->pci->pp;  in al_pcie_config_prepare()
258 	ft = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);  in al_pcie_config_prepare()
260 		return -ENODEV;  in al_pcie_config_prepare()
262 	bus = ft->res;  in al_pcie_config_prepare()
263 	target_bus_cfg = &pcie->target_bus_cfg;  in al_pcie_config_prepare()
265 	ecam_bus_mask = (pcie->ecam_size >> PCIE_ECAM_BUS_SHIFT) - 1;  in al_pcie_config_prepare()
267 		dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");  in al_pcie_config_prepare()
272 	target_bus_cfg->ecam_mask = ecam_bus_mask;  in al_pcie_config_prepare()
274 	target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;  in al_pcie_config_prepare()
275 	target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;  in al_pcie_config_prepare()
277 	al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,  in al_pcie_config_prepare()
278 			       target_bus_cfg->reg_mask);  in al_pcie_config_prepare()
280 	secondary_bus = bus->start + 1;  in al_pcie_config_prepare()
281 	subordinate_bus = bus->end;  in al_pcie_config_prepare()
284 	cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +  in al_pcie_config_prepare()
287 	cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);  in al_pcie_config_prepare()
295 	al_pcie_controller_writel(pcie, cfg_control_offset, reg);  in al_pcie_config_prepare()
303 	struct al_pcie *pcie = to_al_pcie(pci);  in al_pcie_host_init()  local
306 	pp->bridge->child_ops = &al_child_pci_ops;  in al_pcie_host_init()
308 	rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);  in al_pcie_host_init()
312 	rc = al_pcie_reg_offsets_set(pcie);  in al_pcie_host_init()
316 	rc = al_pcie_config_prepare(pcie);  in al_pcie_host_init()
329 	struct device *dev = &pdev->dev;  in al_pcie_probe()
337 		return -ENOMEM;  in al_pcie_probe()
341 		return -ENOMEM;  in al_pcie_probe()
343 	pci->dev = dev;  in al_pcie_probe()
344 	pci->pp.ops = &al_pcie_host_ops;  in al_pcie_probe()
346 	al_pcie->pci = pci;  in al_pcie_probe()
347 	al_pcie->dev = dev;  in al_pcie_probe()
352 		return -ENOENT;  in al_pcie_probe()
354 	al_pcie->ecam_size = resource_size(ecam_res);  in al_pcie_probe()
358 	al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);  in al_pcie_probe()
359 	if (IS_ERR(al_pcie->controller_base)) {  in al_pcie_probe()
362 		return PTR_ERR(al_pcie->controller_base);  in al_pcie_probe()
369 	return dw_pcie_host_init(&pci->pp);  in al_pcie_probe()
373 	{ .compatible = "amazon,al-alpine-v2-pcie",
375 	{ .compatible = "amazon,al-alpine-v3-pcie",
382 		.name	= "al-pcie",