Lines Matching +full:pci +full:- +full:ep
1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/pci.h>
32 #include "../../pci.h"
33 #include "pcie-designware.h"
89 struct dw_pcie *pci;
91 int phy_count; /* DT phy-names count */
103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
107 return readl(pcie->base + offset);
113 writel(value, pcie->base + offset);
116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
121 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
142 struct device *dev = pci->dev;
145 if (dw_pcie_link_up(pci)) {
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
195 irq_set_chip_data(irq, domain->host_data);
207 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
211 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
218 generic_handle_domain_irq(pp->irq_domain,
229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
232 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
250 dev_warn_ratelimited(pci->dev,
259 struct dw_pcie *pci;
266 pci = to_dw_pcie_from_pp(pp);
267 dra7xx = to_dra7xx_pcie(pci);
281 generic_handle_domain_irq(dra7xx->irq_domain, bit);
291 struct dw_pcie *pci = dra7xx->pci;
292 struct device *dev = pci->dev;
293 struct dw_pcie_ep *ep = &pci->ep;
318 "Power Management Event Turn-Off message received\n");
322 "Power Management Turn-Off Ack message received\n");
331 if (dra7xx->mode == DW_PCIE_EP_TYPE)
332 dw_pcie_ep_linkup(ep);
333 dev_dbg(dev, "Link-up state change\n");
349 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
350 struct device *dev = pci->dev;
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
352 struct device_node *node = dev->of_node;
357 return -ENODEV;
360 irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
362 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
365 if (!dra7xx->irq_domain) {
367 return -ENODEV;
377 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
379 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
380 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
384 dw_pcie_ep_reset_bar(pci, bar);
401 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
406 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
409 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
410 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
420 dev_err(pci->dev, "UNKNOWN IRQ type\n");
433 dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
448 struct dw_pcie_ep *ep;
449 struct device *dev = &pdev->dev;
450 struct dw_pcie *pci = dra7xx->pci;
452 ep = &pci->ep;
453 ep->ops = &pcie_ep_ops;
455 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
456 if (IS_ERR(pci->dbi_base))
457 return PTR_ERR(pci->dbi_base);
459 pci->dbi_base2 =
461 if (IS_ERR(pci->dbi_base2))
462 return PTR_ERR(pci->dbi_base2);
464 ret = dw_pcie_ep_init(ep);
470 ret = dw_pcie_ep_init_registers(ep);
473 dw_pcie_ep_deinit(ep);
477 pci_epc_init_notify(ep->epc);
486 struct dw_pcie *pci = dra7xx->pci;
487 struct dw_pcie_rp *pp = &pci->pp;
488 struct device *dev = pci->dev;
490 pp->irq = platform_get_irq(pdev, 1);
491 if (pp->irq < 0)
492 return pp->irq;
495 pp->msi_irq[0] = -ENODEV;
501 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
502 if (IS_ERR(pci->dbi_base))
503 return PTR_ERR(pci->dbi_base);
505 pp->ops = &dra7xx_pcie_host_ops;
525 int phy_count = dra7xx->phy_count;
527 while (phy_count--) {
528 phy_power_off(dra7xx->phy[phy_count]);
529 phy_exit(dra7xx->phy[phy_count]);
535 int phy_count = dra7xx->phy_count;
540 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
544 ret = phy_init(dra7xx->phy[i]);
548 ret = phy_power_on(dra7xx->phy[i]);
550 phy_exit(dra7xx->phy[i]);
558 while (--i >= 0) {
559 phy_power_off(dra7xx->phy[i]);
560 phy_exit(dra7xx->phy[i]);
596 .compatible = "ti,dra7-pcie",
600 .compatible = "ti,dra7-pcie-ep",
604 .compatible = "ti,dra746-pcie-rc",
608 .compatible = "ti,dra726-pcie-rc",
612 .compatible = "ti,dra746-pcie-ep",
616 .compatible = "ti,dra726-pcie-ep",
627 * Access to the PCIe slave port that are not 32-bit aligned will result
629 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
637 struct device_node *np = dev->of_node;
641 regmap = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-unaligned-access",
644 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
645 return -EINVAL;
658 struct device_node *np = dev->of_node;
664 pcie_syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-lane-sel",
667 dev_err(dev, "unable to get ti,syscon-lane-sel\n");
668 return -EINVAL;
688 struct dw_pcie *pci;
690 struct device *dev = &pdev->dev;
691 struct device_node *np = dev->of_node;
700 return -EINVAL;
702 mode = (enum dw_pcie_device_mode)data->mode;
703 b1co_mode_sel_mask = data->b1co_mode_sel_mask;
707 return -ENOMEM;
709 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
710 if (!pci)
711 return -ENOMEM;
713 pci->dev = dev;
714 pci->ops = &dw_pcie_ops;
724 phy_count = of_property_count_strings(np, "phy-names");
732 return -ENOMEM;
736 return -ENOMEM;
738 dra7xx->clk = devm_clk_get_optional(dev, NULL);
739 if (IS_ERR(dra7xx->clk))
740 return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
743 ret = clk_prepare_enable(dra7xx->clk);
748 snprintf(name, sizeof(name), "pcie-phy%d", i);
753 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
755 ret = -EINVAL;
760 dra7xx->base = base;
761 dra7xx->phy = phy;
762 dra7xx->pci = pci;
763 dra7xx->phy_count = phy_count;
768 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
789 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
800 ret = -ENODEV;
817 ret = -ENODEV;
835 dra7xx->mode = mode;
839 "dra7xx-pcie-main", dra7xx);
848 if (dra7xx->mode == DW_PCIE_RC_TYPE)
849 dw_pcie_host_deinit(&dra7xx->pci->pp);
851 dw_pcie_ep_deinit(&dra7xx->pci->ep);
860 while (--i >= 0)
869 struct dw_pcie *pci = dra7xx->pci;
872 if (dra7xx->mode != DW_PCIE_RC_TYPE)
876 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
878 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
886 struct dw_pcie *pci = dra7xx->pci;
889 if (dra7xx->mode != DW_PCIE_RC_TYPE)
893 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
895 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
925 struct device *dev = &pdev->dev;
929 dra7xx_pcie_stop_link(dra7xx->pci);
938 clk_disable_unprepare(dra7xx->clk);
950 .name = "dra7-pcie",