1 // SPDX-License-Identifier: GPL-2.0
3  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5  * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
33 #include "pcie-designware.h"
35 /* PCIe controller wrapper DRA7XX configuration registers */
40 #define	ERR_FATAL					BIT(1)
59 #define	INTB						BIT(1)
91 	int			phy_count;	/* DT phy-names count */
103 #define to_dra7xx_pcie(x)	dev_get_drvdata((x)->dev)
105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)  in dra7xx_pcie_readl()  argument
107 	return readl(pcie->base + offset);  in dra7xx_pcie_readl()
110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,  in dra7xx_pcie_writel()  argument
113 	writel(value, pcie->base + offset);  in dra7xx_pcie_writel()
142 	struct device *dev = pci->dev;  in dra7xx_pcie_establish_link()
195 	irq_set_chip_data(irq, domain->host_data);  in dra7xx_pcie_intx_map()
218 		generic_handle_domain_irq(pp->irq_domain,  in dra7xx_pcie_handle_msi()
224 	return 1;  in dra7xx_pcie_handle_msi()
232 	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;  in dra7xx_pcie_handle_msi_irq()
250 		dev_warn_ratelimited(pci->dev,  in dra7xx_pcie_handle_msi_irq()
281 			generic_handle_domain_irq(dra7xx->irq_domain, bit);  in dra7xx_pcie_msi_irq_handler()
291 	struct dw_pcie *pci = dra7xx->pci;  in dra7xx_pcie_irq_handler()
292 	struct device *dev = pci->dev;  in dra7xx_pcie_irq_handler()
293 	struct dw_pcie_ep *ep = &pci->ep;  in dra7xx_pcie_irq_handler()
311 		dev_dbg(dev, "AXI tag lookup fatal Error\n");  in dra7xx_pcie_irq_handler()
318 			"Power Management Event Turn-Off message received\n");  in dra7xx_pcie_irq_handler()
322 			"Power Management Turn-Off Ack message received\n");  in dra7xx_pcie_irq_handler()
331 		if (dra7xx->mode == DW_PCIE_EP_TYPE)  in dra7xx_pcie_irq_handler()
333 		dev_dbg(dev, "Link-up state change\n");  in dra7xx_pcie_irq_handler()
350 	struct device *dev = pci->dev;  in dra7xx_pcie_init_irq_domain()
352 	struct device_node *node = dev->of_node;  in dra7xx_pcie_init_irq_domain()
356 		dev_err(dev, "No PCIe Intc node found\n");  in dra7xx_pcie_init_irq_domain()
357 		return -ENODEV;  in dra7xx_pcie_init_irq_domain()
360 	irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,  in dra7xx_pcie_init_irq_domain()
362 	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,  in dra7xx_pcie_init_irq_domain()
365 	if (!dra7xx->irq_domain) {  in dra7xx_pcie_init_irq_domain()
367 		return -ENODEV;  in dra7xx_pcie_init_irq_domain()
392 	mdelay(1);  in dra7xx_pcie_raise_intx_irq()
401 	reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;  in dra7xx_pcie_raise_msi_irq()
420 		dev_err(pci->dev, "UNKNOWN IRQ type\n");  in dra7xx_pcie_raise_irq()
449 	struct device *dev = &pdev->dev;  in dra7xx_add_pcie_ep()
450 	struct dw_pcie *pci = dra7xx->pci;  in dra7xx_add_pcie_ep()
452 	ep = &pci->ep;  in dra7xx_add_pcie_ep()
453 	ep->ops = &pcie_ep_ops;  in dra7xx_add_pcie_ep()
455 	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");  in dra7xx_add_pcie_ep()
456 	if (IS_ERR(pci->dbi_base))  in dra7xx_add_pcie_ep()
457 		return PTR_ERR(pci->dbi_base);  in dra7xx_add_pcie_ep()
459 	pci->dbi_base2 =  in dra7xx_add_pcie_ep()
461 	if (IS_ERR(pci->dbi_base2))  in dra7xx_add_pcie_ep()
462 		return PTR_ERR(pci->dbi_base2);  in dra7xx_add_pcie_ep()
477 	pci_epc_init_notify(ep->epc);  in dra7xx_add_pcie_ep()
486 	struct dw_pcie *pci = dra7xx->pci;  in dra7xx_add_pcie_port()
487 	struct dw_pcie_rp *pp = &pci->pp;  in dra7xx_add_pcie_port()
488 	struct device *dev = pci->dev;  in dra7xx_add_pcie_port()
490 	pp->irq = platform_get_irq(pdev, 1);  in dra7xx_add_pcie_port()
491 	if (pp->irq < 0)  in dra7xx_add_pcie_port()
492 		return pp->irq;  in dra7xx_add_pcie_port()
495 	pp->msi_irq[0] = -ENODEV;  in dra7xx_add_pcie_port()
501 	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");  in dra7xx_add_pcie_port()
502 	if (IS_ERR(pci->dbi_base))  in dra7xx_add_pcie_port()
503 		return PTR_ERR(pci->dbi_base);  in dra7xx_add_pcie_port()
505 	pp->ops = &dra7xx_pcie_host_ops;  in dra7xx_add_pcie_port()
509 		dev_err(dev, "failed to initialize host\n");  in dra7xx_add_pcie_port()
525 	int phy_count = dra7xx->phy_count;  in dra7xx_pcie_disable_phy()
527 	while (phy_count--) {  in dra7xx_pcie_disable_phy()
528 		phy_power_off(dra7xx->phy[phy_count]);  in dra7xx_pcie_disable_phy()
529 		phy_exit(dra7xx->phy[phy_count]);  in dra7xx_pcie_disable_phy()
535 	int phy_count = dra7xx->phy_count;  in dra7xx_pcie_enable_phy()
540 		ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);  in dra7xx_pcie_enable_phy()
544 		ret = phy_init(dra7xx->phy[i]);  in dra7xx_pcie_enable_phy()
548 		ret = phy_power_on(dra7xx->phy[i]);  in dra7xx_pcie_enable_phy()
550 			phy_exit(dra7xx->phy[i]);  in dra7xx_pcie_enable_phy()
558 	while (--i >= 0) {  in dra7xx_pcie_enable_phy()
559 		phy_power_off(dra7xx->phy[i]);  in dra7xx_pcie_enable_phy()
560 		phy_exit(dra7xx->phy[i]);  in dra7xx_pcie_enable_phy()
596 		.compatible = "ti,dra7-pcie",
600 		.compatible = "ti,dra7-pcie-ep",
604 		.compatible = "ti,dra746-pcie-rc",
608 		.compatible = "ti,dra726-pcie-rc",
612 		.compatible = "ti,dra746-pcie-ep",
616 		.compatible = "ti,dra726-pcie-ep",
627  * Access to the PCIe slave port that are not 32-bit aligned will result
629  * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
632  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
637 	struct device_node *np = dev->of_node;  in dra7xx_pcie_unaligned_memaccess()
642 						 "ti,syscon-unaligned-access");  in dra7xx_pcie_unaligned_memaccess()
644 		dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");  in dra7xx_pcie_unaligned_memaccess()
645 		return -EINVAL;  in dra7xx_pcie_unaligned_memaccess()
648 	ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",  in dra7xx_pcie_unaligned_memaccess()
651 		dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");  in dra7xx_pcie_unaligned_memaccess()
655 	ret = regmap_update_bits(regmap, args.args[0], args.args[1],  in dra7xx_pcie_unaligned_memaccess()
656 				 args.args[1]);  in dra7xx_pcie_unaligned_memaccess()
668 	struct device_node *np = dev->of_node;  in dra7xx_pcie_configure_two_lane()
674 	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");  in dra7xx_pcie_configure_two_lane()
676 		dev_err(dev, "unable to get ti,syscon-lane-sel\n");  in dra7xx_pcie_configure_two_lane()
677 		return -EINVAL;  in dra7xx_pcie_configure_two_lane()
680 	if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,  in dra7xx_pcie_configure_two_lane()
683 		return -EINVAL;  in dra7xx_pcie_configure_two_lane()
705 	struct device *dev = &pdev->dev;  in dra7xx_pcie_probe()
706 	struct device_node *np = dev->of_node;  in dra7xx_pcie_probe()
715 		return -EINVAL;  in dra7xx_pcie_probe()
717 	mode = (enum dw_pcie_device_mode)data->mode;  in dra7xx_pcie_probe()
718 	b1co_mode_sel_mask = data->b1co_mode_sel_mask;  in dra7xx_pcie_probe()
722 		return -ENOMEM;  in dra7xx_pcie_probe()
726 		return -ENOMEM;  in dra7xx_pcie_probe()
728 	pci->dev = dev;  in dra7xx_pcie_probe()
729 	pci->ops = &dw_pcie_ops;  in dra7xx_pcie_probe()
739 	phy_count = of_property_count_strings(np, "phy-names");  in dra7xx_pcie_probe()
747 		return -ENOMEM;  in dra7xx_pcie_probe()
751 		return -ENOMEM;  in dra7xx_pcie_probe()
753 	dra7xx->clk = devm_clk_get_optional(dev, NULL);  in dra7xx_pcie_probe()
754 	if (IS_ERR(dra7xx->clk))  in dra7xx_pcie_probe()
755 		return dev_err_probe(dev, PTR_ERR(dra7xx->clk),  in dra7xx_pcie_probe()
758 	ret = clk_prepare_enable(dra7xx->clk);  in dra7xx_pcie_probe()
763 		snprintf(name, sizeof(name), "pcie-phy%d", i);  in dra7xx_pcie_probe()
768 		link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);  in dra7xx_pcie_probe()
770 			ret = -EINVAL;  in dra7xx_pcie_probe()
775 	dra7xx->base = base;  in dra7xx_pcie_probe()
776 	dra7xx->phy = phy;  in dra7xx_pcie_probe()
777 	dra7xx->pci = pci;  in dra7xx_pcie_probe()
778 	dra7xx->phy_count = phy_count;  in dra7xx_pcie_probe()
783 			dra7xx->phy_count = 1; /* Fallback to x1 lane mode */  in dra7xx_pcie_probe()
804 		dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);  in dra7xx_pcie_probe()
815 			ret = -ENODEV;  in dra7xx_pcie_probe()
832 			ret = -ENODEV;  in dra7xx_pcie_probe()
850 	dra7xx->mode = mode;  in dra7xx_pcie_probe()
854 					"dra7xx-pcie-main", dra7xx);  in dra7xx_pcie_probe()
863 	if (dra7xx->mode == DW_PCIE_RC_TYPE)  in dra7xx_pcie_probe()
864 		dw_pcie_host_deinit(&dra7xx->pci->pp);  in dra7xx_pcie_probe()
866 		dw_pcie_ep_deinit(&dra7xx->pci->ep);  in dra7xx_pcie_probe()
875 	while (--i >= 0)  in dra7xx_pcie_probe()
884 	struct dw_pcie *pci = dra7xx->pci;  in dra7xx_pcie_suspend()
887 	if (dra7xx->mode != DW_PCIE_RC_TYPE)  in dra7xx_pcie_suspend()
901 	struct dw_pcie *pci = dra7xx->pci;  in dra7xx_pcie_resume()
904 	if (dra7xx->mode != DW_PCIE_RC_TYPE)  in dra7xx_pcie_resume()
940 	struct device *dev = &pdev->dev;  in dra7xx_pcie_shutdown()
944 	dra7xx_pcie_stop_link(dra7xx->pci);  in dra7xx_pcie_shutdown()
953 	clk_disable_unprepare(dra7xx->clk);  in dra7xx_pcie_shutdown()
965 		.name	= "dra7-pcie",
975 MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");