1 // SPDX-License-Identifier: GPL-2.0
3  * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC
14 #include "pcie-cadence.h"
17  * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to
19  * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports
20  * 1/2/4 byte aligned access, so directly using read/write should be fine.
37 	struct device *dev = &pdev->dev;  in sg2042_pcie_probe()
39 	struct cdns_pcie *pcie;  in sg2042_pcie_probe()  local
45 		return dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n");  in sg2042_pcie_probe()
47 	bridge->ops = &sg2042_pcie_root_ops;  in sg2042_pcie_probe()
48 	bridge->child_ops = &sg2042_pcie_child_ops;  in sg2042_pcie_probe()
51 	pcie = &rc->pcie;  in sg2042_pcie_probe()
52 	pcie->dev = dev;  in sg2042_pcie_probe()
54 	platform_set_drvdata(pdev, pcie);  in sg2042_pcie_probe()
60 	ret = cdns_pcie_init_phy(dev, pcie);  in sg2042_pcie_probe()
66 		dev_err_probe(dev, ret, "Failed to setup host!\n");  in sg2042_pcie_probe()
67 		cdns_pcie_disable_phy(pcie);  in sg2042_pcie_probe()
76 	struct cdns_pcie *pcie = platform_get_drvdata(pdev);  in sg2042_pcie_remove()  local
77 	struct device *dev = &pdev->dev;  in sg2042_pcie_remove()
80 	rc = container_of(pcie, struct cdns_pcie_rc, pcie);  in sg2042_pcie_remove()
83 	cdns_pcie_disable_phy(pcie);  in sg2042_pcie_remove()
90 	struct cdns_pcie *pcie = dev_get_drvdata(dev);  in sg2042_pcie_suspend_noirq()  local
92 	cdns_pcie_disable_phy(pcie);  in sg2042_pcie_suspend_noirq()
99 	struct cdns_pcie *pcie = dev_get_drvdata(dev);  in sg2042_pcie_resume_noirq()  local
102 	ret = cdns_pcie_enable_phy(pcie);  in sg2042_pcie_resume_noirq()
116 	{ .compatible = "sophgo,sg2042-pcie-host" },
123 		.name		= "sg2042-pcie",
133 MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs");