Lines Matching +full:irq +full:- +full:status +full:- +full:read +full:- +full:quirk
1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
150 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
190 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
201 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
217 RP_BAR_UNDEFINED = -1,
256 * struct cdns_pcie - private data for Cadence PCIe controller drivers
264 * @ops: Platform-specific ops to control various inputs from Cadence PCIe
279 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
287 * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or
289 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
290 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
304 * struct cdns_pcie_epf - Structure to hold info about endpoint function
314 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
319 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
323 * IRQ) TLP through the PCIe bus.
324 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
327 * the MSI/INTX IRQ dedicated outbound region.
331 * minimize time between read and write
333 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
334 * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag
357 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
362 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
367 return readw(pcie->reg_base + reg); in cdns_pcie_readw()
372 return readb(pcie->reg_base + reg); in cdns_pcie_readb()
410 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); in cdns_pcie_read_sz()
430 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); in cdns_pcie_write_sz()
440 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writeb()
448 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writew()
455 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_readw()
464 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writeb()
472 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writew()
480 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writel()
485 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_readw()
492 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readl()
497 if (pcie->ops && pcie->ops->start_link) in cdns_pcie_start_link()
498 return pcie->ops->start_link(pcie); in cdns_pcie_start_link()
505 if (pcie->ops && pcie->ops->stop_link) in cdns_pcie_stop_link()
506 pcie->ops->stop_link(pcie); in cdns_pcie_stop_link()
511 if (pcie->ops && pcie->ops->link_up) in cdns_pcie_link_up()
512 return pcie->ops->link_up(pcie); in cdns_pcie_link_up()