Lines Matching +full:endpoint +full:- +full:base
1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
42 /* Endpoint Bus and Device Number Register */
49 /* Endpoint Function f BAR b Configuration Registers */
71 /* Endpoint Function Configuration Register */
96 /* BAR control values applicable to both Endpoint Function and Root Complex */
117 (((aperture) - 2) << ((bar) * 8))
124 * Endpoint Function Registers (PCI configuration space for endpoint functions)
134 * Endpoint PF Registers
155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
190 /* Region r AXI Region Base Address Register 0 */
195 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
197 /* Region r AXI Region Base Address Register 1 */
206 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
222 RP_BAR_UNDEFINED = -1,
236 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
292 * struct cdns_pcie - private data for Cadence PCIe controller drivers
293 * @reg_base: IO mapped register base
296 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
300 * @ops: Platform-specific ops to control various inputs from Cadence PCIe
315 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
340 * struct cdns_pcie_epf - Structure to hold info about endpoint function
342 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers
350 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
354 * @ob_addr: base addresses in the AXI bus where the outbound regions start
355 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
357 * @irq_cpu_addr: base address in the CPU space where a write access triggers
368 * @epf: Structure to hold info about endpoint function
393 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
398 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
415 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); in cdns_pcie_read_sz()
435 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); in cdns_pcie_write_sz()
445 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writeb()
453 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writew()
460 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_readw()
465 /* Endpoint Function register access */
469 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writeb()
477 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writew()
485 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writel()
490 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_readw()
497 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readl()
502 if (pcie->ops->start_link) in cdns_pcie_start_link()
503 return pcie->ops->start_link(pcie); in cdns_pcie_start_link()
510 if (pcie->ops->stop_link) in cdns_pcie_stop_link()
511 pcie->ops->stop_link(pcie); in cdns_pcie_stop_link()
516 if (pcie->ops->link_up) in cdns_pcie_link_up()
517 return pcie->ops->link_up(pcie); in cdns_pcie_link_up()