1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
10 #include "pcie-cadence.h"
51 	u64 sz = 1ULL << fls64(size - 1);  in cdns_pcie_set_outbound_region()
92 	if (pcie->is_rc) {  in cdns_pcie_set_outbound_region()
109 	if (pcie->ops && pcie->ops->cpu_addr_fixup)  in cdns_pcie_set_outbound_region()
110 		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);  in cdns_pcie_set_outbound_region()
131 	if (pcie->is_rc) {  in cdns_pcie_set_outbound_region_for_normal_msg()
140 	if (pcie->ops && pcie->ops->cpu_addr_fixup)  in cdns_pcie_set_outbound_region_for_normal_msg()
141 		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);  in cdns_pcie_set_outbound_region_for_normal_msg()
171 	int i = pcie->phy_count;  in cdns_pcie_disable_phy()
173 	while (i--) {  in cdns_pcie_disable_phy()
174 		phy_power_off(pcie->phy[i]);  in cdns_pcie_disable_phy()
175 		phy_exit(pcie->phy[i]);  in cdns_pcie_disable_phy()
185 	for (i = 0; i < pcie->phy_count; i++) {  in cdns_pcie_enable_phy()
186 		ret = phy_init(pcie->phy[i]);  in cdns_pcie_enable_phy()
190 		ret = phy_power_on(pcie->phy[i]);  in cdns_pcie_enable_phy()
192 			phy_exit(pcie->phy[i]);  in cdns_pcie_enable_phy()
200 	while (--i >= 0) {  in cdns_pcie_enable_phy()
201 		phy_power_off(pcie->phy[i]);  in cdns_pcie_enable_phy()
202 		phy_exit(pcie->phy[i]);  in cdns_pcie_enable_phy()
211 	struct device_node *np = dev->of_node;  in cdns_pcie_init_phy()
213 	struct phy **phy;  in cdns_pcie_init_phy()  local
219 	phy_count = of_property_count_strings(np, "phy-names");  in cdns_pcie_init_phy()
221 		dev_info(dev, "no \"phy-names\" property found; PHY will not be initialized\n");  in cdns_pcie_init_phy()
222 		pcie->phy_count = 0;  in cdns_pcie_init_phy()
226 	phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);  in cdns_pcie_init_phy()
227 	if (!phy)  in cdns_pcie_init_phy()
228 		return -ENOMEM;  in cdns_pcie_init_phy()
232 		return -ENOMEM;  in cdns_pcie_init_phy()
235 		of_property_read_string_index(np, "phy-names", i, &name);  in cdns_pcie_init_phy()
236 		phy[i] = devm_phy_get(dev, name);  in cdns_pcie_init_phy()
237 		if (IS_ERR(phy[i])) {  in cdns_pcie_init_phy()
238 			ret = PTR_ERR(phy[i]);  in cdns_pcie_init_phy()
241 		link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);  in cdns_pcie_init_phy()
243 			devm_phy_put(dev, phy[i]);  in cdns_pcie_init_phy()
244 			ret = -EINVAL;  in cdns_pcie_init_phy()
249 	pcie->phy_count = phy_count;  in cdns_pcie_init_phy()
250 	pcie->phy = phy;  in cdns_pcie_init_phy()
251 	pcie->link = link;  in cdns_pcie_init_phy()
260 	while (--i >= 0) {  in cdns_pcie_init_phy()
262 		devm_phy_put(dev, phy[i]);  in cdns_pcie_init_phy()
285 		dev_err(dev, "failed to enable PHY\n");  in cdns_pcie_resume_noirq()
298 MODULE_DESCRIPTION("Cadence PCIe controller driver");
299 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");