Lines Matching +full:axi +full:- +full:pcie +full:- +full:host +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
54 /* Update Output registers for AXI region 0. */ in cdns_pci_map_bus()
58 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus()
60 /* Configuration Type 0 or Type 1 access. */ in cdns_pci_map_bus()
67 if (busn == bridge->busnr + 1) in cdns_pci_map_bus()
71 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); in cdns_pci_map_bus()
73 return rc->cfg_base + (where & 0xfff); in cdns_pci_map_bus()
82 static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) in cdns_pcie_host_training_complete() argument
91 lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); in cdns_pcie_host_training_complete()
100 return -ETIMEDOUT; in cdns_pcie_host_training_complete()
103 static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) in cdns_pcie_host_wait_for_link() argument
105 struct device *dev = pcie->dev; in cdns_pcie_host_wait_for_link()
110 if (cdns_pcie_link_up(pcie)) { in cdns_pcie_host_wait_for_link()
117 return -ETIMEDOUT; in cdns_pcie_host_wait_for_link()
120 static int cdns_pcie_retrain(struct cdns_pcie *pcie) in cdns_pcie_retrain() argument
128 * but the PCIe root port support is > 2.5 GB/s. in cdns_pcie_retrain()
131 lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + in cdns_pcie_retrain()
136 lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); in cdns_pcie_retrain()
138 lnk_ctl = cdns_pcie_rp_readw(pcie, in cdns_pcie_retrain()
141 cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, in cdns_pcie_retrain()
144 ret = cdns_pcie_host_training_complete(pcie); in cdns_pcie_retrain()
148 ret = cdns_pcie_host_wait_for_link(pcie); in cdns_pcie_retrain()
153 static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie) in cdns_pcie_host_enable_ptm_response() argument
157 val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL); in cdns_pcie_host_enable_ptm_response()
158 cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN); in cdns_pcie_host_enable_ptm_response()
163 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_start_link() local
166 ret = cdns_pcie_host_wait_for_link(pcie); in cdns_pcie_host_start_link()
172 if (!ret && rc->quirk_retrain_flag) in cdns_pcie_host_start_link()
173 ret = cdns_pcie_retrain(pcie); in cdns_pcie_host_start_link()
180 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_init_root_port() local
186 * - disable both BAR0 and BAR1. in cdns_pcie_host_init_root_port()
187 * - enable Prefetchable Memory Base and Limit registers in type 1 in cdns_pcie_host_init_root_port()
189 * - enable IO Base and Limit registers in type 1 config in cdns_pcie_host_init_root_port()
199 cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); in cdns_pcie_host_init_root_port()
202 if (rc->vendor_id != 0xffff) { in cdns_pcie_host_init_root_port()
203 id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | in cdns_pcie_host_init_root_port()
204 CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); in cdns_pcie_host_init_root_port()
205 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); in cdns_pcie_host_init_root_port()
208 if (rc->device_id != 0xffff) in cdns_pcie_host_init_root_port()
209 cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); in cdns_pcie_host_init_root_port()
211 cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0); in cdns_pcie_host_init_root_port()
212 cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); in cdns_pcie_host_init_root_port()
213 cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); in cdns_pcie_host_init_root_port()
223 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_bar_ib_config() local
226 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_bar_ib_config()
227 return -EBUSY; in cdns_pcie_host_bar_ib_config()
229 rc->avail_ib_bar[bar] = false; in cdns_pcie_host_bar_ib_config()
235 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0); in cdns_pcie_host_bar_ib_config()
236 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1); in cdns_pcie_host_bar_ib_config()
241 value = cdns_pcie_readl(pcie, CDNS_PCIE_LM_RC_BAR_CFG); in cdns_pcie_host_bar_ib_config()
258 cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); in cdns_pcie_host_bar_ib_config()
270 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_find_min_bar()
294 if (!rc->avail_ib_bar[bar]) in cdns_pcie_host_find_max_bar()
315 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_bar_config() local
316 struct device *dev = pcie->dev; in cdns_pcie_host_bar_config()
321 cpu_addr = entry->res->start; in cdns_pcie_host_bar_config()
322 pci_addr = entry->res->start - entry->offset; in cdns_pcie_host_bar_config()
323 flags = entry->res->flags; in cdns_pcie_host_bar_config()
324 size = resource_size(entry->res); in cdns_pcie_host_bar_config()
326 if (entry->offset) { in cdns_pcie_host_bar_config()
329 return -EINVAL; in cdns_pcie_host_bar_config()
365 return -EINVAL; in cdns_pcie_host_bar_config()
376 size -= winsize; in cdns_pcie_host_bar_config()
391 return resource_size(entry2->res) - resource_size(entry1->res); in cdns_pcie_host_dma_ranges_cmp()
396 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_map_dma_ranges() local
397 struct device *dev = pcie->dev; in cdns_pcie_host_map_dma_ranges()
398 struct device_node *np = dev->of_node; in cdns_pcie_host_map_dma_ranges()
406 return -ENOMEM; in cdns_pcie_host_map_dma_ranges()
408 if (list_empty(&bridge->dma_ranges)) { in cdns_pcie_host_map_dma_ranges()
409 of_property_read_u32(np, "cdns,no-bar-match-nbits", in cdns_pcie_host_map_dma_ranges()
412 (u64)1 << no_bar_nbits, 0); in cdns_pcie_host_map_dma_ranges()
418 list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); in cdns_pcie_host_map_dma_ranges()
420 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in cdns_pcie_host_map_dma_ranges()
423 dev_err(dev, "Fail to configure IB using dma-ranges\n"); in cdns_pcie_host_map_dma_ranges()
433 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_init_address_translation() local
435 struct resource *cfg_res = rc->cfg_res; in cdns_pcie_host_init_address_translation()
437 u64 cpu_addr = cfg_res->start; in cdns_pcie_host_init_address_translation()
441 entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in cdns_pcie_host_init_address_translation()
443 busnr = entry->res->start; in cdns_pcie_host_init_address_translation()
452 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); in cdns_pcie_host_init_address_translation()
453 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); in cdns_pcie_host_init_address_translation()
455 if (pcie->ops->cpu_addr_fixup) in cdns_pcie_host_init_address_translation()
456 cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); in cdns_pcie_host_init_address_translation()
461 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0); in cdns_pcie_host_init_address_translation()
462 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1); in cdns_pcie_host_init_address_translation()
464 r = 1; in cdns_pcie_host_init_address_translation()
465 resource_list_for_each_entry(entry, &bridge->windows) { in cdns_pcie_host_init_address_translation()
466 struct resource *res = entry->res; in cdns_pcie_host_init_address_translation()
467 u64 pci_addr = res->start - entry->offset; in cdns_pcie_host_init_address_translation()
470 cdns_pcie_set_outbound_region(pcie, busnr, 0, r, in cdns_pcie_host_init_address_translation()
472 pci_pio_to_address(res->start), in cdns_pcie_host_init_address_translation()
476 cdns_pcie_set_outbound_region(pcie, busnr, 0, r, in cdns_pcie_host_init_address_translation()
478 res->start, in cdns_pcie_host_init_address_translation()
501 struct cdns_pcie *pcie = &rc->pcie; in cdns_pcie_host_link_setup() local
502 struct device *dev = rc->pcie.dev; in cdns_pcie_host_link_setup()
505 if (rc->quirk_detect_quiet_flag) in cdns_pcie_host_link_setup()
506 cdns_pcie_detect_quiet_min_delay_set(&rc->pcie); in cdns_pcie_host_link_setup()
508 cdns_pcie_host_enable_ptm_response(pcie); in cdns_pcie_host_link_setup()
510 ret = cdns_pcie_start_link(pcie); in cdns_pcie_host_link_setup()
518 dev_dbg(dev, "PCIe link never came up\n"); in cdns_pcie_host_link_setup()
525 struct device *dev = rc->pcie.dev; in cdns_pcie_host_setup()
527 struct device_node *np = dev->of_node; in cdns_pcie_host_setup()
530 struct cdns_pcie *pcie; in cdns_pcie_host_setup() local
536 return -ENOMEM; in cdns_pcie_host_setup()
538 pcie = &rc->pcie; in cdns_pcie_host_setup()
539 pcie->is_rc = true; in cdns_pcie_host_setup()
541 rc->vendor_id = 0xffff; in cdns_pcie_host_setup()
542 of_property_read_u32(np, "vendor-id", &rc->vendor_id); in cdns_pcie_host_setup()
544 rc->device_id = 0xffff; in cdns_pcie_host_setup()
545 of_property_read_u32(np, "device-id", &rc->device_id); in cdns_pcie_host_setup()
547 pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); in cdns_pcie_host_setup()
548 if (IS_ERR(pcie->reg_base)) { in cdns_pcie_host_setup()
550 return PTR_ERR(pcie->reg_base); in cdns_pcie_host_setup()
554 rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); in cdns_pcie_host_setup()
555 if (IS_ERR(rc->cfg_base)) in cdns_pcie_host_setup()
556 return PTR_ERR(rc->cfg_base); in cdns_pcie_host_setup()
557 rc->cfg_res = res; in cdns_pcie_host_setup()
564 rc->avail_ib_bar[bar] = true; in cdns_pcie_host_setup()
570 if (!bridge->ops) in cdns_pcie_host_setup()
571 bridge->ops = &cdns_pcie_host_ops; in cdns_pcie_host_setup()