1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Low-level parallel port routines for built-in port on SGI IP32
10  * Thanks to Ilya A. Volynets-Evenbakh for his help.
19  *	Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
21  *	SPP/ECP FIFO can be driven in PIO or DMA mode.  PIO mode can work with
24  *	Hardware ECP mode is not fully implemented (ecp_read_data and
32  *	If DMA mode works well, decide if support for PIO FIFO modes should be
35  *	the linux-mips.org tree.  Note: the MIPS specific functions readsb()
40 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
43  * FIFO buffer and supports DMA transfers.
49  * registers are port-mapped.  On the O2, they are memory-mapped.
51  * it is for the built-in serial ports on the same chip).
54 /*--- Some configuration defines ---------------------------------------*/
66 /*----------------------------------------------------------------------*/
84 #include <linux/dma-mapping.h>
101 /*--- Global variables -------------------------------------------------*/
117  * @verbose_probing:	log chit-chat during initialization
130 /* Timing constants for FIFO modes.  */
134 /*--- I/O register definitions -----------------------------------------*/
137  * struct parport_ip32_regs - virtual addresses of parallel port registers
146  * @ecpAFifo:	ECP Address FIFO
147  * @fifo:	General FIFO register.  The same address is used for:
148  *		- cFifo, the Parallel Port DATA FIFO
149  *		- ecpDFifo, the ECP Data FIFO
150  *		- tFifo, the ECP Test FIFO
165 	void __iomem *fifo;  member
226 /*--- Private data -----------------------------------------------------*/
229  * enum parport_ip32_irq_mode - operation mode of interrupt handler
236  * struct parport_ip32_private - private stuff for &struct parport
241  * @fifo_depth:		number of PWords that FIFO will hold
261 /*--- Debug code -------------------------------------------------------*/
264  * pr_debug1 - print debug messages
275  * pr_trace, pr_trace1 - trace function calls
282  * pr_debug1().  __pr_trace() is the low-level macro and is not to be used
288 		   __p ? __p->name : "parport_ip32"; }),		\
294  * __pr_probe, pr_probe - print message if @verbose_probing is true
304 	__pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
307  * parport_ip32_dump_state - print register status of parport
321 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_dump_state()
324 	printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);  in parport_ip32_dump_state()
329 		unsigned int ecr = readb(priv->regs.ecr);  in parport_ip32_dump_state()
347 		oecr = readb(priv->regs.ecr);  in parport_ip32_dump_state()
348 		writeb(ECR_MODE_PS2, priv->regs.ecr);  in parport_ip32_dump_state()
349 		writeb(ECR_MODE_CFG, priv->regs.ecr);  in parport_ip32_dump_state()
350 		cnfgA = readb(priv->regs.cnfgA);  in parport_ip32_dump_state()
351 		cnfgB = readb(priv->regs.cnfgB);  in parport_ip32_dump_state()
352 		writeb(ECR_MODE_PS2, priv->regs.ecr);  in parport_ip32_dump_state()
353 		writeb(oecr, priv->regs.ecr);  in parport_ip32_dump_state()
355 		pr_cont(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");  in parport_ip32_dump_state()
387 		unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);  in parport_ip32_dump_state()
406 		unsigned int dsr = readb(priv->regs.dsr);  in parport_ip32_dump_state()
431  * CHECK_EXTRA_BITS - track and log extra bits
447 				  (p)->name, __func__, #b, __b, __m);	\
453 /*--- IP32 parallel port DMA operations --------------------------------*/
456  * struct parport_ip32_dma_data - private data needed for DMA operation
479  * parport_ip32_dma_setup_context - setup next DMA context
492 		 * mace->perif.ctrl.parport.context_a and context_b are  in parport_ip32_dma_setup_context()
495 			&mace->perif.ctrl.parport.context_a :  in parport_ip32_dma_setup_context()
496 			&mace->perif.ctrl.parport.context_b;  in parport_ip32_dma_setup_context()
508 			 "(%u): 0x%04x:0x%04x, %u -> %u%s",  in parport_ip32_dma_setup_context()
517 		ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &  in parport_ip32_dma_setup_context()
521 		parport_ip32_dma.left -= count;  in parport_ip32_dma_setup_context()
537  * parport_ip32_dma_interrupt - DMA interrupt handler
558  * parport_ip32_dma_start - begins a DMA transfer
575 	/* FIXME - add support for DMA_FROM_DEVICE.  In this case, buffer must  in parport_ip32_dma_start()
581 	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_start()
593 	parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir);  in parport_ip32_dma_start()
601 	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_start()
603 	limit = MACEPAR_CONTEXT_DATA_BOUND -  in parport_ip32_dma_start()
604 		(parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));  in parport_ip32_dma_start()
610 	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_start()
616  * parport_ip32_dma_stop - ends a running DMA transfer
647 	ctrl = readq(&mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_stop()
649 	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_stop()
652 	ctx_a = readq(&mace->perif.ctrl.parport.context_a);  in parport_ip32_dma_stop()
653 	ctx_b = readq(&mace->perif.ctrl.parport.context_b);  in parport_ip32_dma_stop()
654 	ctrl = readq(&mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_stop()
655 	diag = readq(&mace->perif.ctrl.parport.diagnostic);  in parport_ip32_dma_stop()
670 	/* Reset DMA controller, and re-enable IRQs */  in parport_ip32_dma_stop()
672 	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_stop()
678 	dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf,  in parport_ip32_dma_stop()
683  * parport_ip32_dma_get_residue - get residue from last DMA transfer
693  * parport_ip32_dma_register - initialize DMA engine
705 	writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);  in parport_ip32_dma_register()
717 	/* FIXME - what is this IRQ for? */  in parport_ip32_dma_register()
736  * parport_ip32_dma_unregister - release and free resources for DMA engine
747 /*--- Interrupt handlers and associates --------------------------------*/
750  * parport_ip32_wakeup - wakes up code waiting for an interrupt
755 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_wakeup()
756 	complete(&priv->irq_complete);  in parport_ip32_wakeup()
760  * parport_ip32_interrupt - interrupt handler
770 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_interrupt()
771 	enum parport_ip32_irq_mode irq_mode = priv->irq_mode;  in parport_ip32_interrupt()
785 /*--- Some utility function to manipulate ECR register -----------------*/
788  * parport_ip32_read_econtrol - read contents of the ECR register
793 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_read_econtrol()
794 	return readb(priv->regs.ecr);  in parport_ip32_read_econtrol()
798  * parport_ip32_write_econtrol - write new contents to the ECR register
805 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_write_econtrol()
806 	writeb(c, priv->regs.ecr);  in parport_ip32_write_econtrol()
810  * parport_ip32_frob_econtrol - change bits from the ECR register
815  * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits
828  * parport_ip32_set_mode - change mode of ECP port
851 /*--- Basic functions needed for parport -------------------------------*/
854  * parport_ip32_read_data - return current contents of the DATA register
859 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_read_data()
860 	return readb(priv->regs.data);  in parport_ip32_read_data()
864  * parport_ip32_write_data - set new contents for the DATA register
870 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_write_data()
871 	writeb(d, priv->regs.data);  in parport_ip32_write_data()
875  * parport_ip32_read_status - return current contents of the DSR register
880 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_read_status()
881 	return readb(priv->regs.dsr);  in parport_ip32_read_status()
885  * __parport_ip32_read_control - return cached contents of the DCR register
890 	struct parport_ip32_private * const priv = p->physport->private_data;  in __parport_ip32_read_control()
891 	return priv->dcr_cache; /* use soft copy */  in __parport_ip32_read_control()
895  * __parport_ip32_write_control - set new contents for the DCR register
902 	struct parport_ip32_private * const priv = p->physport->private_data;  in __parport_ip32_write_control()
903 	CHECK_EXTRA_BITS(p, c, priv->dcr_writable);  in __parport_ip32_write_control()
904 	c &= priv->dcr_writable; /* only writable bits */  in __parport_ip32_write_control()
905 	writeb(c, priv->regs.dcr);  in __parport_ip32_write_control()
906 	priv->dcr_cache = c;		/* update soft copy */  in __parport_ip32_write_control()
910  * __parport_ip32_frob_control - change bits from the DCR register
916  * exclusive-or with the bits in @val, and write the result to the DCR.
929  * parport_ip32_read_control - return cached contents of the DCR register
943  * parport_ip32_write_control - set new contents for the DCR register
960  * parport_ip32_frob_control - change bits from the DCR register
981  * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK
990  * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK
999  * parport_ip32_data_forward - enable host-to-peripheral communications
1002  * Enable the data line drivers, for 8-bit host-to-peripheral communications.
1010  * parport_ip32_data_reverse - enable peripheral-to-host communications
1013  * Place the data bus in a high impedance state, if @p->modes has the
1022  * parport_ip32_init_state - for core parport code
1029 	s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;  in parport_ip32_init_state()
1030 	s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;  in parport_ip32_init_state()
1034  * parport_ip32_save_state - for core parport code
1041 	s->u.ip32.dcr = __parport_ip32_read_control(p);  in parport_ip32_save_state()
1042 	s->u.ip32.ecr = parport_ip32_read_econtrol(p);  in parport_ip32_save_state()
1046  * parport_ip32_restore_state - for core parport code
1053 	parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);  in parport_ip32_restore_state()
1054 	parport_ip32_write_econtrol(p, s->u.ip32.ecr);  in parport_ip32_restore_state()
1055 	__parport_ip32_write_control(p, s->u.ip32.dcr);  in parport_ip32_restore_state()
1058 /*--- EPP mode functions -----------------------------------------------*/
1061  * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode
1068 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_clear_epp_timeout()
1079 		writeb(r | DSR_TIMEOUT, priv->regs.dsr);  in parport_ip32_clear_epp_timeout()
1081 		writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);  in parport_ip32_clear_epp_timeout()
1092  * parport_ip32_epp_read - generic EPP read function
1103 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_read()
1110 		if (readb(priv->regs.dsr) & DSR_TIMEOUT) {  in parport_ip32_epp_read()
1112 			return -EIO;  in parport_ip32_epp_read()
1119 			if (readb(priv->regs.dsr) & DSR_TIMEOUT) {  in parport_ip32_epp_read()
1131  * parport_ip32_epp_write - generic EPP write function
1142 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_write()
1149 		if (readb(priv->regs.dsr) & DSR_TIMEOUT) {  in parport_ip32_epp_write()
1151 			return -EIO;  in parport_ip32_epp_write()
1158 			if (readb(priv->regs.dsr) & DSR_TIMEOUT) {  in parport_ip32_epp_write()
1169  * parport_ip32_epp_read_data - read a block of data in EPP mode
1178 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_read_data()
1179 	return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);  in parport_ip32_epp_read_data()
1183  * parport_ip32_epp_write_data - write a block of data in EPP mode
1192 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_write_data()
1193 	return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);  in parport_ip32_epp_write_data()
1197  * parport_ip32_epp_read_addr - read a block of addresses in EPP mode
1206 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_read_addr()
1207 	return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);  in parport_ip32_epp_read_addr()
1211  * parport_ip32_epp_write_addr - write a block of addresses in EPP mode
1220 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_epp_write_addr()
1221 	return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);  in parport_ip32_epp_write_addr()
1224 /*--- ECP mode functions (FIFO) ----------------------------------------*/
1227  * parport_ip32_fifo_wait_break - check if the waiting function should return
1233  *	- expired timeout;
1234  *	- a pending signal;
1235  *	- nFault asserted low.
1243 		pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);  in parport_ip32_fifo_wait_break()
1247 		pr_debug1(PPIP32 "%s: Signal pending\n", p->name);  in parport_ip32_fifo_wait_break()
1251 		pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);  in parport_ip32_fifo_wait_break()
1258  * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling)
1261  * Returns the number of bytes that can safely be written in the FIFO.  A
1267 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_fwp_wait_polling()
1268 	struct parport * const physport = p->physport;  in parport_ip32_fwp_wait_polling()
1273 	expire = jiffies + physport->cad->timeout;  in parport_ip32_fwp_wait_polling()
1279 		/* Check FIFO state.  We do nothing when the FIFO is nor full,  in parport_ip32_fwp_wait_polling()
1280 		 * nor empty.  It appears that the FIFO full bit is not always  in parport_ip32_fwp_wait_polling()
1281 		 * reliable, the FIFO state is sometimes wrongly reported, and  in parport_ip32_fwp_wait_polling()
1285 			/* FIFO is empty, fill it up */  in parport_ip32_fwp_wait_polling()
1286 			count = priv->fifo_depth;  in parport_ip32_fwp_wait_polling()
1298  * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven)
1301  * Returns the number of bytes that can safely be written in the FIFO.  A
1308 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_fwp_wait_interrupt()
1309 	struct parport * const physport = p->physport;  in parport_ip32_fwp_wait_interrupt()
1315 	nfault_timeout = min((unsigned long)physport->cad->timeout,  in parport_ip32_fwp_wait_interrupt()
1317 	expire = jiffies + physport->cad->timeout;  in parport_ip32_fwp_wait_interrupt()
1324 		reinit_completion(&priv->irq_complete);  in parport_ip32_fwp_wait_interrupt()
1329 		/* Enabling serviceIntr while the FIFO is empty does not  in parport_ip32_fwp_wait_interrupt()
1334 			/* FIFO is not empty: wait for an interrupt or a  in parport_ip32_fwp_wait_interrupt()
1337 				&priv->irq_complete, nfault_timeout);  in parport_ip32_fwp_wait_interrupt()
1342 					p->name, __func__);  in parport_ip32_fwp_wait_interrupt()
1350 		/* Check FIFO state */  in parport_ip32_fwp_wait_interrupt()
1352 			/* FIFO is empty, fill it up */  in parport_ip32_fwp_wait_interrupt()
1353 			count = priv->fifo_depth;  in parport_ip32_fwp_wait_interrupt()
1356 			/* FIFO is not empty, but we know that can safely push  in parport_ip32_fwp_wait_interrupt()
1358 			count = priv->writeIntrThreshold;  in parport_ip32_fwp_wait_interrupt()
1361 		/* FIFO is not empty, and we did not get any interrupt.  in parport_ip32_fwp_wait_interrupt()
1371  * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode)
1377  * FIFO.  Returns the number of bytes that were actually written.  It can work
1384 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_fifo_write_block_pio()
1388 	priv->irq_mode = PARPORT_IP32_IRQ_HERE;  in parport_ip32_fifo_write_block_pio()
1393 		count = (p->irq == PARPORT_IRQ_NONE) ?  in parport_ip32_fifo_write_block_pio()
1401 			writeb(*bufp, priv->regs.fifo);  in parport_ip32_fifo_write_block_pio()
1402 			bufp++, left--;  in parport_ip32_fifo_write_block_pio()
1404 			writesb(priv->regs.fifo, bufp, count);  in parport_ip32_fifo_write_block_pio()
1405 			bufp += count, left -= count;  in parport_ip32_fifo_write_block_pio()
1409 	priv->irq_mode = PARPORT_IP32_IRQ_FWD;  in parport_ip32_fifo_write_block_pio()
1411 	return len - left;  in parport_ip32_fifo_write_block_pio()
1415  * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode)
1421  * FIFO.  Returns the number of bytes that were actually written.  The
1428 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_fifo_write_block_dma()
1429 	struct parport * const physport = p->physport;  in parport_ip32_fifo_write_block_dma()
1435 	priv->irq_mode = PARPORT_IP32_IRQ_HERE;  in parport_ip32_fifo_write_block_dma()
1438 	reinit_completion(&priv->irq_complete);  in parport_ip32_fifo_write_block_dma()
1441 	nfault_timeout = min((unsigned long)physport->cad->timeout,  in parport_ip32_fifo_write_block_dma()
1443 	expire = jiffies + physport->cad->timeout;  in parport_ip32_fifo_write_block_dma()
1447 		wait_for_completion_interruptible_timeout(&priv->irq_complete,  in parport_ip32_fifo_write_block_dma()
1454 	written = len - parport_ip32_dma_get_residue();  in parport_ip32_fifo_write_block_dma()
1456 	priv->irq_mode = PARPORT_IP32_IRQ_FWD;  in parport_ip32_fifo_write_block_dma()
1462  * parport_ip32_fifo_write_block - write a block of data
1468  * p FIFO.  Returns the number of bytes that were actually written.
1475 		/* FIXME - Maybe some threshold value should be set for @len  in parport_ip32_fifo_write_block()
1477 		written = (p->modes & PARPORT_MODE_DMA) ?  in parport_ip32_fifo_write_block()
1484  * parport_ip32_drain_fifo - wait for FIFO to empty
1488  * This function waits for FIFO to empty.  It returns 1 when FIFO is empty, or
1525  * parport_ip32_get_fifo_residue - reset FIFO
1529  * This function resets FIFO, and returns the number of bytes remaining in it.
1534 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_get_fifo_residue()
1538 	/* FIXME - We are missing one byte if the printer is off-line.  I  in parport_ip32_get_fifo_residue()
1546 		pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);  in parport_ip32_get_fifo_residue()
1557 		 * Let's hope that the FIFO is really stuck and that the  in parport_ip32_get_fifo_residue()
1562 		/* Fill up FIFO */  in parport_ip32_get_fifo_residue()
1563 		for (residue = priv->fifo_depth; residue > 0; residue--) {  in parport_ip32_get_fifo_residue()
1566 			writeb(0x00, priv->regs.fifo);  in parport_ip32_get_fifo_residue()
1570 		pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",  in parport_ip32_get_fifo_residue()
1571 			  p->name, residue,  in parport_ip32_get_fifo_residue()
1574 	/* Now reset the FIFO */  in parport_ip32_get_fifo_residue()
1583 				  p->name, __func__);  in parport_ip32_get_fifo_residue()
1588 				  p->name, __func__);  in parport_ip32_get_fifo_residue()
1593 	cnfga = readb(priv->regs.cnfgA);  in parport_ip32_get_fifo_residue()
1596 			  p->name, cnfga);  in parport_ip32_get_fifo_residue()
1598 			  p->name);  in parport_ip32_get_fifo_residue()
1613  * parport_ip32_compat_write_data - write a block of data in SPP mode
1624 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_compat_write_data()
1625 	struct parport * const physport = p->physport;  in parport_ip32_compat_write_data()
1630 	if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)  in parport_ip32_compat_write_data()
1633 	/* Reset FIFO, go in forward mode, and disable ackIntEn */  in parport_ip32_compat_write_data()
1639 	physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;  in parport_ip32_compat_write_data()
1647 				p->name, __func__);  in parport_ip32_compat_write_data()
1655 	/* Wait FIFO to empty.  Timeout is proportional to FIFO_depth.  */  in parport_ip32_compat_write_data()
1656 	parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);  in parport_ip32_compat_write_data()
1659 	written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);  in parport_ip32_compat_write_data()
1664 		       p->name, __func__);  in parport_ip32_compat_write_data()
1667 	/* Reset FIFO */  in parport_ip32_compat_write_data()
1669 	physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;  in parport_ip32_compat_write_data()
1675  * FIXME - Insert here parport_ip32_ecp_read_data().
1679  * parport_ip32_ecp_write_data - write a block of data in ECP mode
1690 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_ecp_write_data()
1691 	struct parport * const physport = p->physport;  in parport_ip32_ecp_write_data()
1696 	if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)  in parport_ip32_ecp_write_data()
1700 	if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {  in parport_ip32_ecp_write_data()
1708 			       p->name, __func__);  in parport_ip32_ecp_write_data()
1709 			physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;  in parport_ip32_ecp_write_data()
1714 	/* Reset FIFO, go in forward mode, and disable ackIntEn */  in parport_ip32_ecp_write_data()
1720 	physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;  in parport_ip32_ecp_write_data()
1728 				p->name, __func__);  in parport_ip32_ecp_write_data()
1736 	/* Wait FIFO to empty.  Timeout is proportional to FIFO_depth.  */  in parport_ip32_ecp_write_data()
1737 	parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);  in parport_ip32_ecp_write_data()
1740 	written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);  in parport_ip32_ecp_write_data()
1745 		       p->name, __func__);  in parport_ip32_ecp_write_data()
1748 	/* Reset FIFO */  in parport_ip32_ecp_write_data()
1750 	physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;  in parport_ip32_ecp_write_data()
1756  * FIXME - Insert here parport_ip32_ecp_write_addr().
1759 /*--- Default parport operations ---------------------------------------*/
1797 /*--- Device detection -------------------------------------------------*/
1800  * parport_ip32_ecp_supported - check for an ECP port
1809 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_ecp_supported()
1813 	writeb(ecr, priv->regs.ecr);  in parport_ip32_ecp_supported()
1814 	if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))  in parport_ip32_ecp_supported()
1828  * parport_ip32_fifo_supported - check for FIFO parameters
1831  * Check for FIFO parameters of an Extended Capabilities Port.  Returns 1 on
1832  * success, and 0 otherwise.  Adjust FIFO parameters in the parport structure.
1837 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_fifo_supported()
1844 	configa = readb(priv->regs.cnfgA);  in parport_ip32_fifo_supported()
1845 	configb = readb(priv->regs.cnfgB);  in parport_ip32_fifo_supported()
1868 	priv->pword = pword;  in parport_ip32_fifo_supported()
1869 	pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);  in parport_ip32_fifo_supported()
1872 	writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);  in parport_ip32_fifo_supported()
1873 	if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)  in parport_ip32_fifo_supported()
1874 		pr_probe(p, "Hardware compression detected (unsupported)\n");  in parport_ip32_fifo_supported()
1875 	writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);  in parport_ip32_fifo_supported()
1877 	/* Reset FIFO and go in test mode (no interrupt, no DMA) */  in parport_ip32_fifo_supported()
1880 	/* FIFO must be empty now */  in parport_ip32_fifo_supported()
1881 	if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {  in parport_ip32_fifo_supported()
1882 		pr_probe(p, "FIFO not reset\n");  in parport_ip32_fifo_supported()
1886 	/* Find out FIFO depth. */  in parport_ip32_fifo_supported()
1887 	priv->fifo_depth = 0;  in parport_ip32_fifo_supported()
1889 		if (readb(priv->regs.ecr) & ECR_F_FULL) {  in parport_ip32_fifo_supported()
1890 			/* FIFO full */  in parport_ip32_fifo_supported()
1891 			priv->fifo_depth = i;  in parport_ip32_fifo_supported()
1894 		writeb((u8)i, priv->regs.fifo);  in parport_ip32_fifo_supported()
1897 		pr_probe(p, "Can't fill FIFO\n");  in parport_ip32_fifo_supported()
1900 	if (!priv->fifo_depth) {  in parport_ip32_fifo_supported()
1901 		pr_probe(p, "Can't get FIFO depth\n");  in parport_ip32_fifo_supported()
1904 	pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);  in parport_ip32_fifo_supported()
1911 	priv->writeIntrThreshold = 0;  in parport_ip32_fifo_supported()
1912 	for (i = 0; i < priv->fifo_depth; i++) {  in parport_ip32_fifo_supported()
1913 		if (readb(priv->regs.fifo) != (u8)i) {  in parport_ip32_fifo_supported()
1914 			pr_probe(p, "Invalid data in FIFO\n");  in parport_ip32_fifo_supported()
1917 		if (!priv->writeIntrThreshold  in parport_ip32_fifo_supported()
1918 		    && readb(priv->regs.ecr) & ECR_SERVINTR)  in parport_ip32_fifo_supported()
1920 			priv->writeIntrThreshold = i + 1;  in parport_ip32_fifo_supported()
1921 		if (i + 1 < priv->fifo_depth  in parport_ip32_fifo_supported()
1922 		    && readb(priv->regs.ecr) & ECR_F_EMPTY) {  in parport_ip32_fifo_supported()
1923 			/* FIFO empty before the last byte? */  in parport_ip32_fifo_supported()
1924 			pr_probe(p, "Data lost in FIFO\n");  in parport_ip32_fifo_supported()
1928 	if (!priv->writeIntrThreshold) {  in parport_ip32_fifo_supported()
1932 	pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);  in parport_ip32_fifo_supported()
1934 	/* FIFO must be empty now */  in parport_ip32_fifo_supported()
1935 	if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {  in parport_ip32_fifo_supported()
1936 		pr_probe(p, "Can't empty FIFO\n");  in parport_ip32_fifo_supported()
1940 	/* Reset FIFO */  in parport_ip32_fifo_supported()
1944 	/* Test FIFO, no interrupt, no DMA */  in parport_ip32_fifo_supported()
1951 	priv->readIntrThreshold = 0;  in parport_ip32_fifo_supported()
1952 	for (i = 0; i < priv->fifo_depth; i++) {  in parport_ip32_fifo_supported()
1953 		writeb(0xaa, priv->regs.fifo);  in parport_ip32_fifo_supported()
1954 		if (readb(priv->regs.ecr) & ECR_SERVINTR) {  in parport_ip32_fifo_supported()
1956 			priv->readIntrThreshold = i + 1;  in parport_ip32_fifo_supported()
1960 	if (!priv->readIntrThreshold) {  in parport_ip32_fifo_supported()
1964 	pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);  in parport_ip32_fifo_supported()
1973 	priv->fifo_depth = 0;  in parport_ip32_fifo_supported()
1978 /*--- Initialization code ----------------------------------------------*/
1981  * parport_ip32_make_isa_registers - compute (ISA) register addresses
2008 		.fifo		= r_base_hi(0),  in parport_ip32_make_isa_registers()
2018  * parport_ip32_probe_port - probe and register IP32 built-in parallel port
2031 	parport_ip32_make_isa_registers(&regs, &mace->isa.parallel,  in parport_ip32_probe_port()
2032 					&mace->isa.ecp1284, 8 /* regshift */);  in parport_ip32_probe_port()
2038 		err = -ENOMEM;  in parport_ip32_probe_port()
2041 	p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);  in parport_ip32_probe_port()
2042 	p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);  in parport_ip32_probe_port()
2043 	p->private_data = priv;  in parport_ip32_probe_port()
2052 	init_completion(&priv->irq_complete);  in parport_ip32_probe_port()
2056 		err = -ENODEV;  in parport_ip32_probe_port()
2063 	p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;  in parport_ip32_probe_port()
2064 	p->modes |= PARPORT_MODE_TRISTATE;  in parport_ip32_probe_port()
2067 		pr_warn(PPIP32 "%s: error: FIFO disabled\n", p->name);  in parport_ip32_probe_port()
2068 		/* Disable hardware modes depending on a working FIFO. */  in parport_ip32_probe_port()
2071 		/* DMA is not needed if FIFO is not supported.  */  in parport_ip32_probe_port()
2078 		if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {  in parport_ip32_probe_port()
2079 			pr_warn(PPIP32 "%s: error: IRQ disabled\n", p->name);  in parport_ip32_probe_port()
2084 			p->irq = irq;  in parport_ip32_probe_port()
2085 			priv->dcr_writable |= DCR_IRQ;  in parport_ip32_probe_port()
2092 			pr_warn(PPIP32 "%s: error: DMA disabled\n", p->name);  in parport_ip32_probe_port()
2095 			p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */  in parport_ip32_probe_port()
2096 			p->modes |= PARPORT_MODE_DMA;  in parport_ip32_probe_port()
2101 		/* Enable compatibility FIFO mode */  in parport_ip32_probe_port()
2102 		p->ops->compat_write_data = parport_ip32_compat_write_data;  in parport_ip32_probe_port()
2103 		p->modes |= PARPORT_MODE_COMPAT;  in parport_ip32_probe_port()
2104 		pr_probe(p, "Hardware support for SPP mode enabled\n");  in parport_ip32_probe_port()
2107 		/* Set up access functions to use EPP hardware. */  in parport_ip32_probe_port()
2108 		p->ops->epp_read_data = parport_ip32_epp_read_data;  in parport_ip32_probe_port()
2109 		p->ops->epp_write_data = parport_ip32_epp_write_data;  in parport_ip32_probe_port()
2110 		p->ops->epp_read_addr = parport_ip32_epp_read_addr;  in parport_ip32_probe_port()
2111 		p->ops->epp_write_addr = parport_ip32_epp_write_addr;  in parport_ip32_probe_port()
2112 		p->modes |= PARPORT_MODE_EPP;  in parport_ip32_probe_port()
2113 		pr_probe(p, "Hardware support for EPP mode enabled\n");  in parport_ip32_probe_port()
2116 		/* Enable ECP FIFO mode */  in parport_ip32_probe_port()
2117 		p->ops->ecp_write_data = parport_ip32_ecp_write_data;  in parport_ip32_probe_port()
2118 		/* FIXME - not implemented */  in parport_ip32_probe_port()
2119 /*		p->ops->ecp_read_data  = parport_ip32_ecp_read_data; */  in parport_ip32_probe_port()
2120 /*		p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */  in parport_ip32_probe_port()
2121 		p->modes |= PARPORT_MODE_ECP;  in parport_ip32_probe_port()
2122 		pr_probe(p, "Hardware support for ECP mode enabled\n");  in parport_ip32_probe_port()
2134 	pr_info("%s: SGI IP32 at 0x%lx (0x%lx)", p->name, p->base, p->base_hi);  in parport_ip32_probe_port()
2135 	if (p->irq != PARPORT_IRQ_NONE)  in parport_ip32_probe_port()
2136 		pr_cont(", irq %d", p->irq);  in parport_ip32_probe_port()
2140 	if (p->modes & PARPORT_MODE_##x)				\  in parport_ip32_probe_port()
2167  * parport_ip32_unregister_port - unregister a parallel port
2175 	struct parport_ip32_private * const priv = p->physport->private_data;  in parport_ip32_unregister_port()
2176 	struct parport_operations *ops = p->ops;  in parport_ip32_unregister_port()
2179 	if (p->modes & PARPORT_MODE_DMA)  in parport_ip32_unregister_port()
2181 	if (p->irq != PARPORT_IRQ_NONE)  in parport_ip32_unregister_port()
2182 		free_irq(p->irq, p);  in parport_ip32_unregister_port()
2189  * parport_ip32_init - module initialization function
2193 	pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");  in parport_ip32_init()
2199  * parport_ip32_exit - module termination function
2206 /*--- Module stuff -----------------------------------------------------*/
2209 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
2217 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
2224 		 ", bit 2: hardware SPP mode"
2225 		 ", bit 3: hardware EPP mode"
2226 		 ", bit 4: hardware ECP mode");