Lines Matching full:hba
111 static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba) in LBA_DEV() argument
113 return container_of(hba, struct lba_device, hba); in LBA_DEV()
191 u8 first_bus = d->hba.hba_bus->busn_res.start; in lba_device_present()
192 u8 last_sub_bus = d->hba.hba_bus->busn_res.end; in lba_device_present()
207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
315 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
347 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_rd_cfg()
349 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_rd_cfg()
358 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_rd_cfg()
368 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in elroy_cfg_read()
411 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_wr_cfg()
420 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_wr_cfg()
421 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_wr_cfg()
456 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); in elroy_cfg_write()
458 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); in elroy_cfg_write()
460 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); in elroy_cfg_write()
464 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in elroy_cfg_write()
485 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_read()
515 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_write()
538 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in mercury_cfg_write()
710 ** Resources aren't allocated until recursive buswalk below HBA is completed.
739 ldev->hba.io_space.name, in lba_fixup_bus()
740 ldev->hba.io_space.start, ldev->hba.io_space.end, in lba_fixup_bus()
741 ldev->hba.io_space.flags); in lba_fixup_bus()
743 ldev->hba.lmmio_space.name, in lba_fixup_bus()
744 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, in lba_fixup_bus()
745 ldev->hba.lmmio_space.flags); in lba_fixup_bus()
747 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); in lba_fixup_bus()
753 if (ldev->hba.elmmio_space.flags) { in lba_fixup_bus()
755 &(ldev->hba.elmmio_space)); in lba_fixup_bus()
760 (long)ldev->hba.elmmio_space.start, in lba_fixup_bus()
761 (long)ldev->hba.elmmio_space.end); in lba_fixup_bus()
768 if (ldev->hba.lmmio_space.flags) { in lba_fixup_bus()
769 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); in lba_fixup_bus()
773 (long)ldev->hba.lmmio_space.start, in lba_fixup_bus()
774 (long)ldev->hba.lmmio_space.end); in lba_fixup_bus()
780 if (ldev->hba.gmmio_space.flags) { in lba_fixup_bus()
781 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); in lba_fixup_bus()
785 (long)ldev->hba.gmmio_space.start, in lba_fixup_bus()
786 (long)ldev->hba.gmmio_space.end); in lba_fixup_bus()
1077 lba_dev->hba.bus_num.start = p->start; in lba_pat_resources()
1078 lba_dev->hba.bus_num.end = p->end; in lba_pat_resources()
1079 lba_dev->hba.bus_num.flags = IORESOURCE_BUS; in lba_pat_resources()
1084 if (!lba_dev->hba.lmmio_space.flags) { in lba_pat_resources()
1087 lba_len = ~READ_REG32(lba_dev->hba.base_addr in lba_pat_resources()
1093 sprintf(lba_dev->hba.lmmio_name, in lba_pat_resources()
1095 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1096 lba_dev->hba.lmmio_space_offset = p->start - in lba_pat_resources()
1098 r = &lba_dev->hba.lmmio_space; in lba_pat_resources()
1099 r->name = lba_dev->hba.lmmio_name; in lba_pat_resources()
1100 } else if (!lba_dev->hba.elmmio_space.flags) { in lba_pat_resources()
1101 sprintf(lba_dev->hba.elmmio_name, in lba_pat_resources()
1103 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1104 r = &lba_dev->hba.elmmio_space; in lba_pat_resources()
1105 r->name = lba_dev->hba.elmmio_name; in lba_pat_resources()
1120 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", in lba_pat_resources()
1121 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1122 r = &lba_dev->hba.gmmio_space; in lba_pat_resources()
1123 r->name = lba_dev->hba.gmmio_name; in lba_pat_resources()
1143 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_pat_resources()
1144 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1145 r = &lba_dev->hba.io_space; in lba_pat_resources()
1146 r->name = lba_dev->hba.io_name; in lba_pat_resources()
1147 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_pat_resources()
1177 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; in lba_legacy_resources()
1186 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); in lba_legacy_resources()
1187 r = &(lba_dev->hba.bus_num); in lba_legacy_resources()
1196 r = &(lba_dev->hba.lmmio_space); in lba_legacy_resources()
1197 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", in lba_legacy_resources()
1198 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1199 r->name = lba_dev->hba.lmmio_name; in lba_legacy_resources()
1268 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); in lba_legacy_resources()
1275 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1276 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); in lba_legacy_resources()
1305 r = &(lba_dev->hba.elmmio_space); in lba_legacy_resources()
1306 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", in lba_legacy_resources()
1307 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1308 r->name = lba_dev->hba.elmmio_name; in lba_legacy_resources()
1314 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); in lba_legacy_resources()
1321 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1322 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); in lba_legacy_resources()
1327 r = &(lba_dev->hba.io_space); in lba_legacy_resources()
1328 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_legacy_resources()
1329 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1330 r->name = lba_dev->hba.io_name; in lba_legacy_resources()
1332 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; in lba_legacy_resources()
1333 …r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - … in lba_legacy_resources()
1336 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_legacy_resources()
1362 d->hba.base_addr, in lba_hw_init()
1363 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), in lba_hw_init()
1364 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), in lba_hw_init()
1365 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), in lba_hw_init()
1366 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); in lba_hw_init()
1368 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), in lba_hw_init()
1369 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), in lba_hw_init()
1370 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), in lba_hw_init()
1371 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); in lba_hw_init()
1373 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); in lba_hw_init()
1377 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); in lba_hw_init()
1391 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; in lba_hw_init()
1396 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1400 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1418 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1420 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1422 WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1433 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { in lba_hw_init()
1444 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); in lba_hw_init()
1559 lba_dev->hba.base_addr = addr; in lba_driver_probe()
1560 lba_dev->hba.dev = dev; in lba_driver_probe()
1562 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ in lba_driver_probe()
1567 pcibios_register_hba(&lba_dev->hba); in lba_driver_probe()
1591 if (lba_dev->hba.bus_num.start < lba_next_bus) in lba_driver_probe()
1592 lba_dev->hba.bus_num.start = lba_next_bus; in lba_driver_probe()
1604 &(lba_dev->hba.lmmio_space))) { in lba_driver_probe()
1606 (long)lba_dev->hba.lmmio_space.start, in lba_driver_probe()
1607 (long)lba_dev->hba.lmmio_space.end); in lba_driver_probe()
1608 lba_dev->hba.lmmio_space.flags = 0; in lba_driver_probe()
1611 pci_add_resource_offset(&resources, &lba_dev->hba.io_space, in lba_driver_probe()
1612 HBA_PORT_BASE(lba_dev->hba.hba_num)); in lba_driver_probe()
1613 if (lba_dev->hba.elmmio_space.flags) in lba_driver_probe()
1614 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space, in lba_driver_probe()
1615 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1616 if (lba_dev->hba.lmmio_space.flags) in lba_driver_probe()
1617 pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space, in lba_driver_probe()
1618 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1619 if (lba_dev->hba.gmmio_space.flags) { in lba_driver_probe()
1622 /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */ in lba_driver_probe()
1625 pci_add_resource(&resources, &lba_dev->hba.bus_num); in lba_driver_probe()
1628 lba_bus = lba_dev->hba.hba_bus = in lba_driver_probe()
1629 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, in lba_driver_probe()
1650 lba_dump_res(&lba_dev->hba.io_space, 2); in lba_driver_probe()
1652 lba_dump_res(&lba_dev->hba.lmmio_space, 2); in lba_driver_probe()