1 // SPDX-License-Identifier: GPL-2.0
3  * STM32 Factory-programmed memory read access driver
5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
18 #include "stm32-bsec-optee-ta.h"
20 /* BSEC secure service access from non-secure */
51 		*buf8++ = readb_relaxed(priv->base + i);  in stm32_romem_read()
56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)  in stm32_bsec_smc()  argument
61 	arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);  in stm32_bsec_smc()
63 		return -EIO;  in stm32_bsec_smc()
70 	return -ENXIO;  in stm32_bsec_smc()
78 	struct device *dev = priv->cfg.dev;  in stm32_bsec_read()
83 	/* Round unaligned access to 32-bits */  in stm32_bsec_read()
88 	if (roffset + rbytes > priv->cfg.size)  in stm32_bsec_read()
89 		return -EINVAL;  in stm32_bsec_read()
92 		u32 otp = i >> 2;  in stm32_bsec_read()  local
94 		if (otp < priv->lower) {  in stm32_bsec_read()
97 				priv->base + STM32MP15_BSEC_DATA0 + i);  in stm32_bsec_read()
99 			ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,  in stm32_bsec_read()
102 				dev_err(dev, "Can't read data%d (%d)\n", otp,  in stm32_bsec_read()
109 			size = min(bytes, (size_t)(4 - skip_bytes));  in stm32_bsec_read()
113 		bytes -= size;  in stm32_bsec_read()
125 	struct device *dev = priv->cfg.dev;  in stm32_bsec_write()
129 	/* Allow only writing complete 32-bits aligned words */  in stm32_bsec_write()
131 		return -EINVAL;  in stm32_bsec_write()
142 	if (offset + bytes >= priv->lower * 4)  in stm32_bsec_write()
153 	return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);  in stm32_bsec_pta_read()
161 	return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);  in stm32_bsec_pta_write()
169 	/* check that the OP-TEE support the BSEC SMC (legacy mode) */  in stm32_bsec_smc_check()
180 	/* check that the OP-TEE node is present and available. */  in optee_presence_check()
181 	np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");  in optee_presence_check()
192 	struct device *dev = &pdev->dev;  in stm32_romem_probe()
199 		return -ENOMEM;  in stm32_romem_probe()
201 	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in stm32_romem_probe()
202 	if (IS_ERR(priv->base))  in stm32_romem_probe()
203 		return PTR_ERR(priv->base);  in stm32_romem_probe()
205 	priv->cfg.name = "stm32-romem";  in stm32_romem_probe()
206 	priv->cfg.word_size = 1;  in stm32_romem_probe()
207 	priv->cfg.stride = 1;  in stm32_romem_probe()
208 	priv->cfg.dev = dev;  in stm32_romem_probe()
209 	priv->cfg.priv = priv;  in stm32_romem_probe()
210 	priv->cfg.owner = THIS_MODULE;  in stm32_romem_probe()
211 	priv->cfg.type = NVMEM_TYPE_OTP;  in stm32_romem_probe()
212 	priv->cfg.add_legacy_fixed_of_cells = true;  in stm32_romem_probe()
214 	priv->lower = 0;  in stm32_romem_probe()
218 		priv->cfg.read_only = true;  in stm32_romem_probe()
219 		priv->cfg.size = resource_size(res);  in stm32_romem_probe()
220 		priv->cfg.reg_read = stm32_romem_read;  in stm32_romem_probe()
222 		priv->cfg.size = cfg->size;  in stm32_romem_probe()
223 		priv->lower = cfg->lower;  in stm32_romem_probe()
224 		if (cfg->ta || optee_presence_check()) {  in stm32_romem_probe()
225 			rc = stm32_bsec_optee_ta_open(&priv->ctx);  in stm32_romem_probe()
227 				/* wait for OP-TEE client driver to be up and ready */  in stm32_romem_probe()
228 				if (rc == -EPROBE_DEFER)  in stm32_romem_probe()
229 					return -EPROBE_DEFER;  in stm32_romem_probe()
231 				if (cfg->ta || !stm32_bsec_smc_check())  in stm32_romem_probe()
235 		if (priv->ctx) {  in stm32_romem_probe()
236 			rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);  in stm32_romem_probe()
241 			priv->cfg.reg_read = stm32_bsec_pta_read;  in stm32_romem_probe()
242 			priv->cfg.reg_write = stm32_bsec_pta_write;  in stm32_romem_probe()
244 			priv->cfg.reg_read = stm32_bsec_read;  in stm32_romem_probe()
245 			priv->cfg.reg_write = stm32_bsec_write;  in stm32_romem_probe()
249 	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));  in stm32_romem_probe()
253  * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
254  * => 96 x 32-bits data words
255  * - Lower: 1K bits, 2:1 redundancy, incremental bit programming
256  *   => 32 (x 32-bits) lower shadow registers = words 0 to 31
257  * - Upper: 2K bits, ECC protection, word programming only
258  *   => 64 (x 32-bits) = words 32 to 95
273  * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
274  *   lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
275  *   mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
276  *   upper OTP (OTP256 to OTP383), bulk (32-bit) programmable
286 	{ .compatible = "st,stm32f4-otp", }, {
287 		.compatible = "st,stm32mp15-bsec",
290 		.compatible = "st,stm32mp13-bsec",
293 		.compatible = "st,stm32mp25-bsec",
303 		.name = "stm32-romem",
310 MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
311 MODULE_ALIAS("platform:nvmem-stm32-romem");