Lines Matching +full:0 +full:x430
56 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
57 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
97 AMD_CNTL_OFFSET = 0x200,
106 AMD_STA_OFFSET = 0x204,
107 AMD_PGSLV_OFFSET = 0x208,
108 AMD_SPAD_MUX_OFFSET = 0x20C,
109 AMD_SPAD_OFFSET = 0x210,
110 AMD_RSMU_HCID = 0x250,
111 AMD_RSMU_SIID = 0x254,
112 AMD_PSION_OFFSET = 0x300,
113 AMD_SSION_OFFSET = 0x330,
114 AMD_MMINDEX_OFFSET = 0x400,
115 AMD_MMDATA_OFFSET = 0x404,
116 AMD_SIDEINFO_OFFSET = 0x408,
118 AMD_SIDE_MASK = BIT(0),
122 AMD_ROMBARLMT_OFFSET = 0x410,
123 AMD_BAR1LMT_OFFSET = 0x414,
124 AMD_BAR23LMT_OFFSET = 0x418,
125 AMD_BAR45LMT_OFFSET = 0x420,
127 AMD_POMBARXLAT_OFFSET = 0x428,
128 AMD_BAR1XLAT_OFFSET = 0x430,
129 AMD_BAR23XLAT_OFFSET = 0x438,
130 AMD_BAR45XLAT_OFFSET = 0x440,
132 AMD_DBFM_OFFSET = 0x450,
133 AMD_DBREQ_OFFSET = 0x454,
134 AMD_MIRRDBSTAT_OFFSET = 0x458,
135 AMD_DBMASK_OFFSET = 0x45C,
136 AMD_DBSTAT_OFFSET = 0x460,
137 AMD_INTMASK_OFFSET = 0x470,
138 AMD_INTSTAT_OFFSET = 0x474,
141 AMD_PEER_FLUSH_EVENT = BIT(0),
153 AMD_PMESTAT_OFFSET = 0x480,
154 AMD_PMSGTRIG_OFFSET = 0x490,
155 AMD_LTRLATENCY_OFFSET = 0x494,
156 AMD_FLUSHTRIG_OFFSET = 0x498,
159 AMD_SMUACK_OFFSET = 0x4A0,
160 AMD_SINRST_OFFSET = 0x4A4,
161 AMD_RSPNUM_OFFSET = 0x4A8,
162 AMD_SMU_SPADMUTEX = 0x4B0,
163 AMD_SMU_SPADOFFSET = 0x4B4,
165 AMD_PEER_OFFSET = 0x400,