Lines Matching +full:modem +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2021-2022, Intel Corporation.
36 struct dpmaif_isr_en_mask *isr_en_msk = &hw_info->isr_en_mask; in t7xx_dpmaif_init_intr()
41 isr_en_msk->ap_ul_l2intr_en_msk = ul_intr_enable; in t7xx_dpmaif_init_intr()
42 iowrite32(DPMAIF_AP_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_init_intr()
45 iowrite32(ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMCR0); in t7xx_dpmaif_init_intr()
46 iowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMSR0); in t7xx_dpmaif_init_intr()
49 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0, in t7xx_dpmaif_init_intr()
56 isr_en_msk->ap_dl_l2intr_err_en_msk = dl_intr_enable; in t7xx_dpmaif_init_intr()
59 isr_en_msk->ap_ul_l2intr_en_msk = ul_intr_enable; in t7xx_dpmaif_init_intr()
60 iowrite32(DPMAIF_AP_APDL_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0); in t7xx_dpmaif_init_intr()
63 iowrite32(~ul_intr_enable, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_init_intr()
64 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMR0, in t7xx_dpmaif_init_intr()
70 isr_en_msk->ap_udl_ip_busy_en_msk = DPMAIF_UDL_IP_BUSY; in t7xx_dpmaif_init_intr()
71 iowrite32(DPMAIF_AP_IP_BUSY_MASK, hw_info->pcie_base + DPMAIF_AP_IP_BUSY); in t7xx_dpmaif_init_intr()
72 iowrite32(isr_en_msk->ap_udl_ip_busy_en_msk, in t7xx_dpmaif_init_intr()
73 hw_info->pcie_base + DPMAIF_AO_AP_DLUL_IP_BUSY_MASK); in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
77 iowrite32(DPMA_HPC_ALL_INT_MASK, hw_info->pcie_base + DPMAIF_HPC_INTR_MASK); in t7xx_dpmaif_init_intr()
88 isr_en_msk = &hw_info->isr_en_mask; in t7xx_dpmaif_mask_ulq_intr()
90 isr_en_msk->ap_ul_l2intr_en_msk &= ~ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr()
91 iowrite32(ul_int_que_done, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMSR0); in t7xx_dpmaif_mask_ulq_intr()
93 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0, in t7xx_dpmaif_mask_ulq_intr()
97 dev_err(hw_info->dev, in t7xx_dpmaif_mask_ulq_intr()
108 isr_en_msk = &hw_info->isr_en_mask; in t7xx_dpmaif_unmask_ulq_intr()
110 isr_en_msk->ap_ul_l2intr_en_msk |= ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr()
111 iowrite32(ul_int_que_done, hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMCR0); in t7xx_dpmaif_unmask_ulq_intr()
113 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0, in t7xx_dpmaif_unmask_ulq_intr()
117 dev_err(hw_info->dev, in t7xx_dpmaif_unmask_ulq_intr()
124 hw_info->isr_en_mask.ap_dl_l2intr_en_msk |= DP_DL_INT_BATCNT_LEN_ERR; in t7xx_dpmaif_dl_unmask_batcnt_len_err_intr()
125 iowrite32(DP_DL_INT_BATCNT_LEN_ERR, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMCR0); in t7xx_dpmaif_dl_unmask_batcnt_len_err_intr()
130 hw_info->isr_en_mask.ap_dl_l2intr_en_msk |= DP_DL_INT_PITCNT_LEN_ERR; in t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr()
131 iowrite32(DP_DL_INT_PITCNT_LEN_ERR, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMCR0); in t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr()
138 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0); in t7xx_update_dlq_intr()
139 iowrite32(q_done, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_update_dlq_intr()
149 iowrite32(q_done, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_mask_dlq_intr()
154 dev_err(hw_info->dev, in t7xx_mask_dlq_intr()
157 return -ETIMEDOUT; in t7xx_mask_dlq_intr()
160 hw_info->isr_en_mask.ap_dl_l2intr_en_msk &= ~q_done; in t7xx_mask_dlq_intr()
169 iowrite32(mask, hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMCR0); in t7xx_dpmaif_dlq_unmask_rx_done()
170 hw_info->isr_en_mask.ap_dl_l2intr_en_msk |= mask; in t7xx_dpmaif_dlq_unmask_rx_done()
177 ip_busy_sts = ioread32(hw_info->pcie_base + DPMAIF_AP_IP_BUSY); in t7xx_dpmaif_clr_ip_busy_sts()
178 iowrite32(ip_busy_sts, hw_info->pcie_base + DPMAIF_AP_IP_BUSY); in t7xx_dpmaif_clr_ip_busy_sts()
186 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_dlq_mask_rx_pitcnt_len_err_intr()
189 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_dlq_mask_rx_pitcnt_len_err_intr()
197 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMCR0); in t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr()
200 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMCR0); in t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr()
205 iowrite32(DPMAIF_AP_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_ul_clr_all_intr()
210 iowrite32(DPMAIF_AP_APDL_ALL_L2TISAR0_MASK, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0); in t7xx_dpmaif_dl_clr_all_intr()
216 para->intr_types[para->intr_cnt] = intr_type; in t7xx_dpmaif_set_intr_para()
217 para->intr_queues[para->intr_cnt] = intr_queue; in t7xx_dpmaif_set_intr_para()
218 para->intr_cnt++; in t7xx_dpmaif_set_intr_para()
221 /* The para->intr_cnt counter is set to zero before this function is called.
257 iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_hw_check_tx_intr()
260 /* The para->intr_cnt counter is set to zero before this function is called.
273 hw_info->isr_en_mask.ap_dl_l2intr_en_msk &= ~DP_DL_INT_BATCNT_LEN_ERR; in t7xx_dpmaif_hw_check_rx_intr()
275 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_hw_check_rx_intr()
280 hw_info->isr_en_mask.ap_dl_l2intr_en_msk &= ~DP_DL_INT_PITCNT_LEN_ERR; in t7xx_dpmaif_hw_check_rx_intr()
282 hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMSR0); in t7xx_dpmaif_hw_check_rx_intr()
331 iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0); in t7xx_dpmaif_hw_check_rx_intr()
335 * t7xx_dpmaif_hw_get_intr_cnt() - Reads interrupt status and count from HW.
350 rx_intr_status = ioread32(hw_info->pcie_base + DPMAIF_AP_APDL_L2TISAR0); in t7xx_dpmaif_hw_get_intr_cnt()
351 rx_intr_qdone = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMR0); in t7xx_dpmaif_hw_get_intr_cnt()
358 tx_intr_status = ioread32(hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_hw_get_intr_cnt()
359 tx_intr_qdone = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0); in t7xx_dpmaif_hw_get_intr_cnt()
391 return para->intr_cnt; in t7xx_dpmaif_hw_get_intr_cnt()
398 value = ioread32(hw_info->pcie_base + DPMAIF_AP_MEM_CLR); in t7xx_dpmaif_sram_init()
400 iowrite32(value, hw_info->pcie_base + DPMAIF_AP_MEM_CLR); in t7xx_dpmaif_sram_init()
402 return ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AP_MEM_CLR, in t7xx_dpmaif_sram_init()
409 iowrite32(DPMAIF_AP_AO_RST_BIT, hw_info->pcie_base + DPMAIF_AP_AO_RGU_ASSERT); in t7xx_dpmaif_hw_reset()
411 iowrite32(DPMAIF_AP_RST_BIT, hw_info->pcie_base + DPMAIF_AP_RGU_ASSERT); in t7xx_dpmaif_hw_reset()
413 iowrite32(DPMAIF_AP_AO_RST_BIT, hw_info->pcie_base + DPMAIF_AP_AO_RGU_DEASSERT); in t7xx_dpmaif_hw_reset()
415 iowrite32(DPMAIF_AP_RST_BIT, hw_info->pcie_base + DPMAIF_AP_RGU_DEASSERT); in t7xx_dpmaif_hw_reset()
430 ap_port_mode = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_hw_config()
432 iowrite32(ap_port_mode, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_hw_config()
433 iowrite32(DPMAIF_CG_EN, hw_info->pcie_base + DPMAIF_AP_CG_EN); in t7xx_dpmaif_hw_config()
439 iowrite32(DPMAIF_PCIE_MODE_SET_VALUE, hw_info->pcie_base + DPMAIF_UL_RESERVE_AO_RW); in t7xx_dpmaif_pcie_dpmaif_sign()
446 enable_bat_cache = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_performance()
448 iowrite32(enable_bat_cache, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_performance()
450 enable_pit_burst = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_performance()
452 iowrite32(enable_pit_burst, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_performance()
464 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_HPC_CNTL); in t7xx_dpmaif_hw_hpc_cntl_set()
472 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_DLQ_AGG_CFG); in t7xx_dpmaif_hw_agg_cfg_set()
478 hw_info->pcie_base + DPMAIF_AO_DL_DLQPIT_INIT_CON5); in t7xx_dpmaif_hw_hash_bit_choose_set()
483 iowrite32(DPMAIF_MID_TIMEOUT_THRES_DF, hw_info->pcie_base + DPMAIF_AO_DL_DLQPIT_TIMEOUT0); in t7xx_dpmaif_hw_mid_pit_timeout_thres_set()
496 hw_info->pcie_base + DPMAIF_AO_DL_DLQPIT_TIMEOUT1 + sizeof(u32) * i); in t7xx_dpmaif_hw_dlq_timeout_thres_set()
502 iowrite32(DPMAIF_DLQ_PRS_THRES_DF, hw_info->pcie_base + DPMAIF_AO_DL_DLQPIT_TRIG_THRES); in t7xx_dpmaif_hw_dlq_start_prs_thres_set()
526 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT, in t7xx_dpmaif_dl_bat_init_done()
530 dev_err(hw_info->dev, "Data plane modem DL BAT is not ready\n"); in t7xx_dpmaif_dl_bat_init_done()
534 iowrite32(dl_bat_init, hw_info->pcie_base + DPMAIF_DL_BAT_INIT); in t7xx_dpmaif_dl_bat_init_done()
536 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT, in t7xx_dpmaif_dl_bat_init_done()
540 dev_err(hw_info->dev, "Data plane modem DL BAT initialization failed\n"); in t7xx_dpmaif_dl_bat_init_done()
548 iowrite32(lower_32_bits(addr), hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON0); in t7xx_dpmaif_dl_set_bat_base_addr()
549 iowrite32(upper_32_bits(addr), hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON3); in t7xx_dpmaif_dl_set_bat_base_addr()
556 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_set_bat_size()
559 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_set_bat_size()
566 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_bat_en()
573 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_bat_en()
580 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0); in t7xx_dpmaif_dl_set_ao_bid_maxcnt()
583 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0); in t7xx_dpmaif_dl_set_ao_bid_maxcnt()
588 iowrite32(DPMAIF_HW_MTU_SIZE, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON1); in t7xx_dpmaif_dl_set_ao_mtu()
595 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_pit_chknum()
598 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_pit_chknum()
605 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0); in t7xx_dpmaif_dl_set_ao_remain_minsz()
609 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0); in t7xx_dpmaif_dl_set_ao_remain_minsz()
616 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_bat_bufsz()
620 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_bat_bufsz()
627 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_bat_rsv_length()
630 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2); in t7xx_dpmaif_dl_set_ao_bat_rsv_length()
637 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_pkt_alignment()
640 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_pkt_alignment()
647 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_pkt_checksum()
649 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_pkt_checksum()
656 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_set_ao_frg_check_thres()
659 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_set_ao_frg_check_thres()
666 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_set_ao_frg_bufsz()
670 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_set_ao_frg_bufsz()
677 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_frg_ao_en()
684 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES); in t7xx_dpmaif_dl_frg_ao_en()
691 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_ao_bat_check_thres()
694 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES); in t7xx_dpmaif_dl_set_ao_bat_check_thres()
701 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PIT_SEQ_END); in t7xx_dpmaif_dl_set_pit_seqnum()
704 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PIT_SEQ_END); in t7xx_dpmaif_dl_set_pit_seqnum()
710 iowrite32(lower_32_bits(addr), hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON0); in t7xx_dpmaif_dl_set_dlq_pit_base_addr()
711 iowrite32(upper_32_bits(addr), hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON4); in t7xx_dpmaif_dl_set_dlq_pit_base_addr()
718 value = ioread32(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON1); in t7xx_dpmaif_dl_set_dlq_pit_size()
721 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON1); in t7xx_dpmaif_dl_set_dlq_pit_size()
722 iowrite32(0, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON2); in t7xx_dpmaif_dl_set_dlq_pit_size()
723 iowrite32(0, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON3); in t7xx_dpmaif_dl_set_dlq_pit_size()
724 iowrite32(0, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON5); in t7xx_dpmaif_dl_set_dlq_pit_size()
725 iowrite32(0, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON6); in t7xx_dpmaif_dl_set_dlq_pit_size()
732 value = ioread32(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON3); in t7xx_dpmaif_dl_dlq_pit_en()
734 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON3); in t7xx_dpmaif_dl_dlq_pit_en()
748 timeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT, in t7xx_dpmaif_dl_dlq_pit_init_done()
753 dev_err(hw_info->dev, "Data plane modem DL PIT is not ready\n"); in t7xx_dpmaif_dl_dlq_pit_init_done()
757 iowrite32(dl_pit_init, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT); in t7xx_dpmaif_dl_dlq_pit_init_done()
758 timeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT, in t7xx_dpmaif_dl_dlq_pit_init_done()
763 dev_err(hw_info->dev, "Data plane modem DL PIT initialization failed\n"); in t7xx_dpmaif_dl_dlq_pit_init_done()
769 t7xx_dpmaif_dl_set_dlq_pit_base_addr(hw_info, dl_que->pit_base); in t7xx_dpmaif_config_dlq_pit_hw()
770 t7xx_dpmaif_dl_set_dlq_pit_size(hw_info, dl_que->pit_size_cnt); in t7xx_dpmaif_config_dlq_pit_hw()
780 t7xx_dpmaif_config_dlq_pit_hw(hw_info, i, &hw_info->dl_que[i]); in t7xx_dpmaif_config_all_dlq_hw()
788 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_all_q_en()
795 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1); in t7xx_dpmaif_dl_all_q_en()
799 timeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT, in t7xx_dpmaif_dl_all_q_en()
803 dev_err(hw_info->dev, "Timeout updating BAT setting to HW\n"); in t7xx_dpmaif_dl_all_q_en()
805 iowrite32(dl_bat_init, hw_info->pcie_base + DPMAIF_DL_BAT_INIT); in t7xx_dpmaif_dl_all_q_en()
806 timeout = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT, in t7xx_dpmaif_dl_all_q_en()
810 dev_err(hw_info->dev, "Data plane modem DL BAT is not ready\n"); in t7xx_dpmaif_dl_all_q_en()
820 dl_que = &hw_info->dl_que[0]; /* All queues share one BAT/frag BAT table */ in t7xx_dpmaif_config_dlq_hw()
821 if (!dl_que->que_started) in t7xx_dpmaif_config_dlq_hw()
822 return -EBUSY; in t7xx_dpmaif_config_dlq_hw()
837 t7xx_dpmaif_dl_set_bat_base_addr(hw_info, dl_que->frg_base); in t7xx_dpmaif_config_dlq_hw()
838 t7xx_dpmaif_dl_set_bat_size(hw_info, dl_que->frg_size_cnt); in t7xx_dpmaif_config_dlq_hw()
845 t7xx_dpmaif_dl_set_bat_base_addr(hw_info, dl_que->bat_base); in t7xx_dpmaif_config_dlq_hw()
846 t7xx_dpmaif_dl_set_bat_size(hw_info, dl_que->bat_size_cnt); in t7xx_dpmaif_config_dlq_hw()
853 /* Init PIT (two PIT table) */ in t7xx_dpmaif_config_dlq_hw()
865 value = ioread32(hw_info->pcie_base + DPMAIF_UL_DRBSIZE_ADDRH_n(q_num)); in t7xx_dpmaif_ul_update_drb_size()
868 iowrite32(value, hw_info->pcie_base + DPMAIF_UL_DRBSIZE_ADDRH_n(q_num)); in t7xx_dpmaif_ul_update_drb_size()
874 iowrite32(lower_32_bits(addr), hw_info->pcie_base + DPMAIF_ULQSAR_n(q_num)); in t7xx_dpmaif_ul_update_drb_base_addr()
875 iowrite32(upper_32_bits(addr), hw_info->pcie_base + DPMAIF_UL_DRB_ADDRH_n(q_num)); in t7xx_dpmaif_ul_update_drb_base_addr()
883 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_rdy_en()
890 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_rdy_en()
898 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_arb_en()
905 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_arb_en()
914 ul_que = &hw_info->ul_que[i]; in t7xx_dpmaif_config_ulq_hw()
915 if (ul_que->que_started) { in t7xx_dpmaif_config_ulq_hw()
916 t7xx_dpmaif_ul_update_drb_size(hw_info, i, ul_que->drb_size_cnt * in t7xx_dpmaif_config_ulq_hw()
918 t7xx_dpmaif_ul_update_drb_base_addr(hw_info, i, ul_que->drb_base); in t7xx_dpmaif_config_ulq_hw()
932 ap_cfg = ioread32(hw_info->pcie_base + DPMAIF_AP_OVERWRITE_CFG); in t7xx_dpmaif_hw_init_done()
934 iowrite32(ap_cfg, hw_info->pcie_base + DPMAIF_AP_OVERWRITE_CFG); in t7xx_dpmaif_hw_init_done()
936 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AP_OVERWRITE_CFG, in t7xx_dpmaif_hw_init_done()
942 iowrite32(DPMAIF_UL_INIT_DONE, hw_info->pcie_base + DPMAIF_AO_UL_INIT_SET); in t7xx_dpmaif_hw_init_done()
943 iowrite32(DPMAIF_DL_INIT_DONE, hw_info->pcie_base + DPMAIF_AO_DL_INIT_SET); in t7xx_dpmaif_hw_init_done()
949 u32 dpmaif_dl_is_busy = ioread32(hw_info->pcie_base + DPMAIF_DL_CHK_BUSY); in t7xx_dpmaif_dl_idle_check()
956 u32 ul_arb_en = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_all_q_en()
963 iowrite32(ul_arb_en, hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0); in t7xx_dpmaif_ul_all_q_en()
968 u32 dpmaif_ul_is_busy = ioread32(hw_info->pcie_base + DPMAIF_UL_CHK_BUSY); in t7xx_dpmaif_ul_idle_check()
982 err = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_ULQ_ADD_DESC_CH_n(q_num), in t7xx_dpmaif_ul_update_hw_drb_cnt()
986 dev_err(hw_info->dev, "UL add is not ready\n"); in t7xx_dpmaif_ul_update_hw_drb_cnt()
990 iowrite32(ul_update, hw_info->pcie_base + DPMAIF_ULQ_ADD_DESC_CH_n(q_num)); in t7xx_dpmaif_ul_update_hw_drb_cnt()
992 err = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_ULQ_ADD_DESC_CH_n(q_num), in t7xx_dpmaif_ul_update_hw_drb_cnt()
996 dev_err(hw_info->dev, "Timeout updating UL add\n"); in t7xx_dpmaif_ul_update_hw_drb_cnt()
1001 unsigned int value = ioread32(hw_info->pcie_base + DPMAIF_ULQ_STA0_n(q_num)); in t7xx_dpmaif_ul_get_rd_idx()
1015 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_ADD, in t7xx_dpmaif_dlq_add_pit_remain_cnt()
1019 dev_err(hw_info->dev, "Data plane modem is not ready to add dlq\n"); in t7xx_dpmaif_dlq_add_pit_remain_cnt()
1023 iowrite32(dl_update, hw_info->pcie_base + DPMAIF_DL_DLQPIT_ADD); in t7xx_dpmaif_dlq_add_pit_remain_cnt()
1025 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_ADD, in t7xx_dpmaif_dlq_add_pit_remain_cnt()
1029 dev_err(hw_info->dev, "Data plane modem add dlq failed\n"); in t7xx_dpmaif_dlq_add_pit_remain_cnt()
1041 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_DLQ_WR_IDX + in t7xx_dpmaif_dl_dlq_pit_get_wr_idx()
1050 return ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_ADD, in t7xx_dl_add_timedout()
1060 dev_err(hw_info->dev, "DL add BAT not ready\n"); in t7xx_dpmaif_dl_snd_hw_bat_cnt()
1061 return -EBUSY; in t7xx_dpmaif_dl_snd_hw_bat_cnt()
1066 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_ADD); in t7xx_dpmaif_dl_snd_hw_bat_cnt()
1069 dev_err(hw_info->dev, "DL add BAT timeout\n"); in t7xx_dpmaif_dl_snd_hw_bat_cnt()
1070 return -EBUSY; in t7xx_dpmaif_dl_snd_hw_bat_cnt()
1080 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_BAT_RD_IDX); in t7xx_dpmaif_dl_get_bat_rd_idx()
1088 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_BAT_WR_IDX); in t7xx_dpmaif_dl_get_bat_wr_idx()
1097 dev_err(hw_info->dev, "Data plane modem is not ready to add frag DLQ\n"); in t7xx_dpmaif_dl_snd_hw_frg_cnt()
1098 return -EBUSY; in t7xx_dpmaif_dl_snd_hw_frg_cnt()
1103 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_ADD); in t7xx_dpmaif_dl_snd_hw_frg_cnt()
1106 dev_err(hw_info->dev, "Data plane modem add frag DLQ failed"); in t7xx_dpmaif_dl_snd_hw_frg_cnt()
1107 return -EBUSY; in t7xx_dpmaif_dl_snd_hw_frg_cnt()
1117 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_FRGBAT_RD_IDX); in t7xx_dpmaif_dl_get_frg_rd_idx()
1129 dl_que = &hw_info->dl_que[i]; in t7xx_dpmaif_set_queue_property()
1130 dl_que->bat_base = init_para->pkt_bat_base_addr[i]; in t7xx_dpmaif_set_queue_property()
1131 dl_que->bat_size_cnt = init_para->pkt_bat_size_cnt[i]; in t7xx_dpmaif_set_queue_property()
1132 dl_que->pit_base = init_para->pit_base_addr[i]; in t7xx_dpmaif_set_queue_property()
1133 dl_que->pit_size_cnt = init_para->pit_size_cnt[i]; in t7xx_dpmaif_set_queue_property()
1134 dl_que->frg_base = init_para->frg_bat_base_addr[i]; in t7xx_dpmaif_set_queue_property()
1135 dl_que->frg_size_cnt = init_para->frg_bat_size_cnt[i]; in t7xx_dpmaif_set_queue_property()
1136 dl_que->que_started = true; in t7xx_dpmaif_set_queue_property()
1140 ul_que = &hw_info->ul_que[i]; in t7xx_dpmaif_set_queue_property()
1141 ul_que->drb_base = init_para->drb_base_addr[i]; in t7xx_dpmaif_set_queue_property()
1142 ul_que->drb_size_cnt = init_para->drb_size_cnt[i]; in t7xx_dpmaif_set_queue_property()
1143 ul_que->que_started = true; in t7xx_dpmaif_set_queue_property()
1148 * t7xx_dpmaif_hw_stop_all_txq() - Stop all TX queues.
1155 * * 0 - Success
1156 * * -ETIMEDOUT - Timed out checking busy queues
1165 dev_err(hw_info->dev, "Failed to stop TX, status: 0x%x\n", in t7xx_dpmaif_hw_stop_all_txq()
1166 ioread32(hw_info->pcie_base + DPMAIF_UL_CHK_BUSY)); in t7xx_dpmaif_hw_stop_all_txq()
1167 return -ETIMEDOUT; in t7xx_dpmaif_hw_stop_all_txq()
1175 * t7xx_dpmaif_hw_stop_all_rxq() - Stop all RX queues.
1184 * * 0 - Success.
1185 * * -ETIMEDOUT - Timed out checking busy queues.
1195 dev_err(hw_info->dev, "Failed to stop RX, status: 0x%x\n", in t7xx_dpmaif_hw_stop_all_rxq()
1196 ioread32(hw_info->pcie_base + DPMAIF_DL_CHK_BUSY)); in t7xx_dpmaif_hw_stop_all_rxq()
1197 return -ETIMEDOUT; in t7xx_dpmaif_hw_stop_all_rxq()
1204 wr_idx = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PIT_WR_IDX); in t7xx_dpmaif_hw_stop_all_rxq()
1206 rd_idx = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PIT_RD_IDX); in t7xx_dpmaif_hw_stop_all_rxq()
1213 dev_err(hw_info->dev, "Check middle PIT sync fail\n"); in t7xx_dpmaif_hw_stop_all_rxq()
1214 return -ETIMEDOUT; in t7xx_dpmaif_hw_stop_all_rxq()
1224 * t7xx_dpmaif_hw_init() - Initialize HW data path API.
1231 * * 0 - Success.
1232 * * -ERROR - Error code from failure sub-initializations.
1240 dev_err(hw_info->dev, "DPMAIF HW config failed\n"); in t7xx_dpmaif_hw_init()
1246 dev_err(hw_info->dev, "DPMAIF HW interrupts init failed\n"); in t7xx_dpmaif_hw_init()
1256 dev_err(hw_info->dev, "DPMAIF HW dlq config failed\n"); in t7xx_dpmaif_hw_init()
1264 dev_err(hw_info->dev, "DPMAIF HW queue init failed\n"); in t7xx_dpmaif_hw_init()
1273 intr_status = ioread32(hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_ul_clr_done()
1276 iowrite32(intr_status, hw_info->pcie_base + DPMAIF_AP_L2TISAR0); in t7xx_dpmaif_ul_clr_done()