Lines Matching +full:7 +full:d
21 RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
52 PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
53 " if_vco_reg_en %d if_vga_en %d",
58 PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
59 " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
60 " ifloopc %d dac1 %d",
63 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
66 PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
70 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
73 PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
74 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
77 PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
78 " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
79 " dac %d",
82 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
85 PDEBUG("reg6 RFPLL2 n %d num %d",
88 case 7:
89 PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
92 PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
93 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
96 PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
97 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
101 PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
102 " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
103 " intbiasen %d tybypass %d",
105 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
109 PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
110 " tx_delay %d",
115 PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
119 PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
120 " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
121 " rf_biasvco %d",
123 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
127 PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
128 " tx_acal %d tx_pcal %d",