Lines Matching +full:12 +full:bit

71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
77 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
89 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
94 #define RTW89_TXWD_BODY3_BK BIT(13)
95 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
117 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
121 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
122 #define RTW89_TXWD_INFO0_DATA_STBC BIT(12)
123 #define RTW89_TXWD_INFO0_DATA_LDPC BIT(11)
124 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
125 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
130 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
135 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
136 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
137 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
143 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
151 #define BE_TXD_BODY0_HWAMSDU BIT(5)
152 #define BE_TXD_BODY0_HW_SEC_IV BIT(6)
153 #define BE_TXD_BODY0_WD_PAGE BIT(7)
154 #define BE_TXD_BODY0_CHK_EN BIT(8)
155 #define BE_TXD_BODY0_WP_INT BIT(9)
156 #define BE_TXD_BODY0_STF_MODE BIT(10)
159 #define BE_TXD_BODY0_SMH_EN BIT(20)
160 #define BE_TXD_BODY0_PKT_OFFSET BIT(21)
161 #define BE_TXD_BODY0_WDINFO_EN BIT(22)
162 #define BE_TXD_BODY0_MOREDATA BIT(23)
164 #define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
171 #define BE_TXD_BODY1_SEC_TYPE GENMASK(15, 12)
173 #define BE_TXD_BODY1_SW_SEC_IV BIT(18)
180 #define BE_TXD_BODY2_AGG_EN BIT(14)
181 #define BE_TXD_BODY2_BK BIT(15)
182 #define BE_TXD_BODY2_MACID_EXTEND BIT(16)
184 #define BE_TXD_BODY2_TID_IND BIT(23)
189 #define BE_TXD_BODY3_MLO_FLAG BIT(12)
190 #define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
191 #define BE_TXD_BODY3_TRY_RATE BIT(14)
192 #define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
195 #define BE_TXD_BODY3_RU_RTY BIT(28)
196 #define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
197 #define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
214 #define BE_TXD_BODY6_PS160 BIT(10)
215 #define BE_TXD_BODY6_BMC BIT(11)
216 #define BE_TXD_BODY6_NO_ACK BIT(12)
217 #define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13)
218 #define BE_TXD_BODY6_A4_HDR BIT(14)
219 #define BE_TXD_BODY6_EOSP_BIT BIT(15)
226 #define BE_TXD_BODY7_DATA_ER BIT(10)
227 #define BE_TXD_BODY7_DATA_BW_ER BIT(11)
228 #define BE_TXD_BODY7_DATA_DCM BIT(12)
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
237 #define BE_TXD_INFO0_DISRTSFB BIT(9)
238 #define BE_TXD_INFO0_DISDATAFB BIT(10)
239 #define BE_TXD_INFO0_DATA_LDPC BIT(11)
240 #define BE_TXD_INFO0_DATA_STBC BIT(12)
242 #define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22)
243 #define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23)
244 #define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
250 #define BE_TXD_INFO1_NAVUSEHDR BIT(10)
251 #define BE_TXD_INFO1_A_CTRL_BQR BIT(12)
252 #define BE_TXD_INFO1_A_CTRL_BSR BIT(14)
253 #define BE_TXD_INFO1_A_CTRL_CAS BIT(15)
259 #define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
261 #define BE_TXD_INFO2_FORCE_TXOP BIT(17)
263 #define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21)
265 #define BE_TXD_INFO2_SPE_RPT_V1 BIT(30)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
271 #define BE_TXD_INFO3_CQI_SND BIT(8)
272 #define BE_TXD_INFO3_RTT_EN BIT(9)
273 #define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
274 #define BE_TXD_INFO3_BT_NULL BIT(11)
275 #define BE_TXD_INFO3_TRI_FRAME BIT(12)
276 #define BE_TXD_INFO3_NULL_0 BIT(13)
277 #define BE_TXD_INFO3_NULL_1 BIT(14)
278 #define BE_TXD_INFO3_RAW BIT(15)
280 #define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25)
281 #define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
288 #define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
289 #define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
291 #define BE_TXD_INFO4_RTS_EN BIT(27)
292 #define BE_TXD_INFO4_CTS2SELF BIT(28)
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
298 #define BE_TXD_INFO5_SR_EN_V1 BIT(5)
303 #define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12)
304 #define BE_TXD_INFO6_UL_DOPPLER BIT(15)
305 #define BE_TXD_INFO6_UL_STBC BIT(16)
310 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
312 #define BE_TXD_INFO7_ELNA_IDX BIT(8)
316 #define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16)
327 #define AX_RXD_BB_SEL BIT(22)
328 #define AX_RXD_MAC_INFO_VLD BIT(23)
331 #define AX_RXD_LONG_RXD BIT(31)
336 #define AX_RXD_SR_EN BIT(7)
341 #define AX_RXD_NON_SRG_PPDU BIT(28)
342 #define AX_RXD_INTER_PPDU BIT(29)
343 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
344 #define AX_RXD_INTER_PPDU_v1 BIT(15)
352 #define AX_RXD_A1_MATCH BIT(0)
353 #define AX_RXD_SW_DEC BIT(1)
354 #define AX_RXD_HW_DEC BIT(2)
355 #define AX_RXD_AMPDU BIT(3)
356 #define AX_RXD_AMPDU_END_PKT BIT(4)
357 #define AX_RXD_AMSDU BIT(5)
358 #define AX_RXD_AMSDU_CUT BIT(6)
359 #define AX_RXD_LAST_MSDU BIT(7)
360 #define AX_RXD_BYPASS BIT(8)
361 #define AX_RXD_CRC32_ERR BIT(9)
362 #define AX_RXD_ICV_ERR BIT(10)
363 #define AX_RXD_MAGIC_WAKE BIT(11)
364 #define AX_RXD_UNICAST_WAKE BIT(12)
365 #define AX_RXD_PATTERN_WAKE BIT(13)
369 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
370 #define AX_RXD_WITH_LLC BIT(25)
371 #define AX_RXD_RX_STATISTICS BIT(26)
375 #define AX_RXD_MC BIT(2)
376 #define AX_RXD_BC BIT(3)
377 #define AX_RXD_MD BIT(4)
378 #define AX_RXD_MF BIT(5)
379 #define AX_RXD_PWR BIT(6)
380 #define AX_RXD_QOS BIT(7)
382 #define AX_RXD_EOSP BIT(12)
383 #define AX_RXD_HTC BIT(13)
384 #define AX_RXD_QNULL BIT(14)
393 #define AX_RXD_ADDR_CAM_VLD BIT(28)
394 #define AX_RXD_ADDR_FWD_EN BIT(29)
395 #define AX_RXD_RX_PL_MATCH BIT(30)
402 #define AX_RXD_SMART_ANT BIT(16)
404 #define AX_RXD_HDR_CNV BIT(21)
406 #define AX_RXD_BIP_KEYID BIT(27)
407 #define AX_RXD_BIP_ENC BIT(28)
413 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
414 #define RTW89_RXINFO_USER_DATA BIT(1)
415 #define RTW89_RXINFO_USER_CTRL BIT(2)
416 #define RTW89_RXINFO_USER_MGMT BIT(3)
417 #define RTW89_RXINFO_USER_BCN BIT(4)
431 #define RTW89_RXINFO_W0_INVALID_V1 BIT(27)
432 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
433 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
444 #define RTW89_PHY_STS_HDR_W0_HDR_2_EN BIT(5)
445 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
474 #define BE_RXD_BB_SEL BIT(30)
475 #define BE_RXD_LONG_RXD BIT(31)
481 #define BE_RXD_FW_RLS BIT(26)
486 #define BE_RXD_LAST_MSDU BIT(12)
487 #define BE_RXD_AMSDU_CUT BIT(13)
488 #define BE_RXD_ADDR_CAM_VLD BIT(14)
489 #define BE_RXD_REORDER BIT(15)
495 #define BE_RXD_BIP_KEYID BIT(4)
496 #define BE_RXD_BIP_ENC BIT(5)
497 #define BE_RXD_CRC32_ERR BIT(6)
498 #define BE_RXD_ICV_ERR BIT(7)
499 #define BE_RXD_HW_DEC BIT(8)
500 #define BE_RXD_SW_DEC BIT(9)
501 #define BE_RXD_A1_MATCH BIT(10)
502 #define BE_RXD_AMPDU BIT(11)
503 #define BE_RXD_AMPDU_EOF BIT(12)
504 #define BE_RXD_AMSDU BIT(13)
505 #define BE_RXD_MC BIT(14)
506 #define BE_RXD_BC BIT(15)
507 #define BE_RXD_MD BIT(16)
508 #define BE_RXD_MF BIT(17)
509 #define BE_RXD_PWR BIT(18)
510 #define BE_RXD_QOS BIT(19)
511 #define BE_RXD_EOSP BIT(20)
512 #define BE_RXD_HTC BIT(21)
513 #define BE_RXD_QNULL BIT(22)
514 #define BE_RXD_A4_FRAME BIT(23)
521 #define BE_RXD_BW_MASK GENMASK(14, 12)
523 #define BE_RXD_RX_REORDER_FIELD_EN BIT(19)
531 #define BE_RXD_SR_EN BIT(13)
532 #define BE_RXD_NON_SRG_PPDU BIT(14)
533 #define BE_RXD_INTER_PPDU BIT(15)
535 #define BE_RXD_RX_STATISTICS BIT(22)
536 #define BE_RXD_SMART_ANT BIT(23)
541 #define BE_RXD_MAGIC_WAKE BIT(5)
542 #define BE_RXD_UNICAST_WAKE BIT(6)
543 #define BE_RXD_PATTERN_WAKE BIT(7)
544 #define BE_RXD_RX_PL_MATCH BIT(8)
545 #define BE_RXD_RX_PL_ID_MASK GENMASK(15, 12)
546 #define BE_RXD_HDR_CNV BIT(16)
547 #define BE_RXD_NAT25_HIT BIT(17)
548 #define BE_RXD_IS_DA BIT(18)
549 #define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19)
551 #define BE_RXD_RXSC_HIT BIT(23)
552 #define BE_RXD_WITH_LLC BIT(24)
553 #define BE_RXD_RX_AGG_FIELD_EN BIT(25)
605 #define RTW89_PHY_STS_IE01_W2_LDPC BIT(28)
606 #define RTW89_PHY_STS_IE01_W2_STBC BIT(30)
640 	RTW89_TXCH_CH12	= 12, /* FW CMD */