Lines Matching +full:0 +full:xf0ffffff
25 {2, 1641, grp_0}, /* ACH 0 */
37 {0, 0, 0}, /* FWCMDQ */
38 {0, 0, 0}, /* BMC */
39 {0, 0, 0}, /* H2D */
43 1651, /* Group 0 */
46 0, /* WP threshold */
165 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
172 0xf},
175 0x0},
219 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
220 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
221 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
222 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
223 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
224 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
225 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
226 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
233 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
234 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
235 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
236 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
237 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
238 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
239 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
240 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
241 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
243 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
245 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
246 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
247 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
248 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
249 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
250 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
251 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
252 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
253 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
255 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
314 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02); in rtw8922a_pwr_on_func()
317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01); in rtw8922a_pwr_on_func()
323 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40); in rtw8922a_pwr_on_func()
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20); in rtw8922a_pwr_on_func()
332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04); in rtw8922a_pwr_on_func()
335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08); in rtw8922a_pwr_on_func()
338 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10); in rtw8922a_pwr_on_func()
341 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
344 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
347 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01); in rtw8922a_pwr_on_func()
350 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02); in rtw8922a_pwr_on_func()
353 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80); in rtw8922a_pwr_on_func()
356 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40); in rtw8922a_pwr_on_func()
359 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40); in rtw8922a_pwr_on_func()
362 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60); in rtw8922a_pwr_on_func()
402 return 0; in rtw8922a_pwr_on_func()
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10); in rtw8922a_pwr_off_func()
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08); in rtw8922a_pwr_off_func()
416 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04); in rtw8922a_pwr_off_func()
419 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
425 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80); in rtw8922a_pwr_off_func()
428 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02); in rtw8922a_pwr_off_func()
431 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01); in rtw8922a_pwr_off_func()
434 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF); in rtw8922a_pwr_off_func()
437 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF); in rtw8922a_pwr_off_func()
450 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20); in rtw8922a_pwr_off_func()
456 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40); in rtw8922a_pwr_off_func()
486 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2); in rtw8922a_pwr_off_func()
489 rtw89_write32(rtwdev, R_BE_UDM1, 0); in rtw8922a_pwr_off_func()
491 return 0; in rtw8922a_pwr_off_func()
505 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_efuse_parsing_tssi()
509 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
511 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
521 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
523 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
564 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) { in rtw8922a_efuse_parsing_gain_offset()
566 if (t != 0xff) in rtw8922a_efuse_parsing_gain_offset()
568 if (t != 0x0) in rtw8922a_efuse_parsing_gain_offset()
572 if (t & 0x80) in rtw8922a_efuse_parsing_gain_offset()
573 gain->offset[i][j] = (t ^ 0x7f) + 1; in rtw8922a_efuse_parsing_gain_offset()
585 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) { in rtw8922a_read_efuse_mac_addr()
587 efuse->addr[i] = val & 0xff; in rtw8922a_read_efuse_mac_addr()
597 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104); in rtw8922a_read_efuse_pci_sdio()
599 ether_addr_copy(efuse->addr, log_map + 0x001A); in rtw8922a_read_efuse_pci_sdio()
601 return 0; in rtw8922a_read_efuse_pci_sdio()
606 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078); in rtw8922a_read_efuse_usb()
608 return 0; in rtw8922a_read_efuse_usb()
618 efuse->country_code[0] = map->country_code[0]; in rtw8922a_read_efuse_rf()
625 return 0; in rtw8922a_read_efuse_rf()
639 return 0; in rtw8922a_read_efuse()
644 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
649 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733}; in rtw8922a_phycap_parsing_thermal_trim()
657 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_thermal_trim()
659 if (pg_th == 0xff) { in rtw8922a_phycap_parsing_thermal_trim()
660 info->thermal_trim[i] = 0; in rtw8922a_phycap_parsing_thermal_trim()
673 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n", in rtw8922a_phycap_parsing_thermal_trim()
683 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734}; in rtw8922a_phycap_parsing_pa_bias_trim()
684 static const u32 check_pa_pad_trim_addr = 0x1700; in rtw8922a_phycap_parsing_pa_bias_trim()
691 if (val != 0xff) in rtw8922a_phycap_parsing_pa_bias_trim()
694 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pa_bias_trim()
698 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pa_bias_trim()
716 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pa_bias_trim()
717 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); in rtw8922a_pa_bias_trim()
721 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pa_bias_trim()
732 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735}; in rtw8922a_phycap_parsing_pad_bias_trim()
737 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pad_bias_trim()
741 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pad_bias_trim()
758 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pad_bias_trim()
759 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0)); in rtw8922a_pad_bias_trim()
763 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pad_bias_trim()
777 return 0; in rtw8922a_read_phycap()
793 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0; in rtw8922a_set_channel_mac()
831 txsb = 0; in rtw8922a_set_channel_mac()
864 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
866 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
870 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
872 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
878 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
879 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
883 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
884 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
905 return 0; in rtw8922a_ctrl_sco_cck()
916 { .addr = 0x41E8, .mask = 0xFF00},
917 { .addr = 0x41E8, .mask = 0xFF0000},
918 { .addr = 0x41E8, .mask = 0xFF000000},
919 { .addr = 0x41EC, .mask = 0xFF},
920 { .addr = 0x41EC, .mask = 0xFF00},
921 { .addr = 0x41EC, .mask = 0xFF0000},
922 { .addr = 0x41EC, .mask = 0xFF000000},
923 { .addr = 0x41F0, .mask = 0xFF}
927 { .addr = 0x41F4, .mask = 0xFF},
928 { .addr = 0x41F4, .mask = 0xFF00},
929 { .addr = 0x41F4, .mask = 0xFF0000},
930 { .addr = 0x41F4, .mask = 0xFF000000}
934 { .addr = 0x41F0, .mask = 0xFF0000},
935 { .addr = 0x41F0, .mask = 0xFF000000}
939 { .addr = 0x41F0, .mask = 0xFF00}
943 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
944 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
945 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
946 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
947 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
948 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
949 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
950 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
951 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
952 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
953 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
954 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
955 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
956 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
960 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
961 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
962 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
963 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
967 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x4078, 0x4478},
968 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
969 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
970 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
971 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
972 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
973 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
974 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
975 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
976 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
977 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
978 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
979 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
980 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
984 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4080, 0x4480},
985 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
986 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4084, 0x4484},
987 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
988 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
989 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
990 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
991 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
992 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
993 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
994 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4088, 0x4488},
995 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
996 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
997 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
998 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
999 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1016 u32 reg_path_ofst = 0; in rtw8922a_set_rpl_gain()
1023 reg_path_ofst = 0x400; in rtw8922a_set_rpl_gain()
1025 for (i = 0; i < RTW89_BW20_SC_160M; i++) { in rtw8922a_set_rpl_gain()
1032 for (i = 0; i < RTW89_BW20_SC_80M; i++) { in rtw8922a_set_rpl_gain()
1039 for (i = 0; i < RTW89_BW20_SC_40M; i++) { in rtw8922a_set_rpl_gain()
1046 for (i = 0; i < RTW89_BW20_SC_20M; i++) { in rtw8922a_set_rpl_gain()
1070 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1082 for (i = 0; i < TIA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1094 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1106 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1134 u8 fraction = value & 0x3; in rtw8922a_set_rx_gain_normal_cck()
1138 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1140 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1144 value + 1 + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1146 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0); in rtw8922a_set_rx_gain_normal_cck()
1147 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0); in rtw8922a_set_rx_gain_normal_cck()
1151 value + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1159 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1160 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608}; in rtw8922a_set_rx_gain_normal_ofdm()
1161 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8}; in rtw8922a_set_rx_gain_normal_ofdm()
1162 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8}; in rtw8922a_set_rx_gain_normal_ofdm()
1163 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1171 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8); in rtw8922a_set_rx_gain_normal_ofdm()
1180 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1181 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1182 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1184 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1185 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1186 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1208 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx); in rtw8922a_set_cck_parameters()
1209 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx); in rtw8922a_set_cck_parameters()
1210 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx); in rtw8922a_set_cck_parameters()
1211 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx); in rtw8922a_set_cck_parameters()
1212 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx); in rtw8922a_set_cck_parameters()
1213 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx); in rtw8922a_set_cck_parameters()
1214 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx); in rtw8922a_set_cck_parameters()
1215 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx); in rtw8922a_set_cck_parameters()
1217 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx); in rtw8922a_set_cck_parameters()
1218 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx); in rtw8922a_set_cck_parameters()
1219 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx); in rtw8922a_set_cck_parameters()
1220 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx); in rtw8922a_set_cck_parameters()
1221 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx); in rtw8922a_set_cck_parameters()
1222 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx); in rtw8922a_set_cck_parameters()
1223 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx); in rtw8922a_set_cck_parameters()
1224 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx); in rtw8922a_set_cck_parameters()
1232 static const u32 band_sel[2] = {0x4160, 0x4560}; in rtw8922a_ctrl_ch()
1272 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1273 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1274 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1275 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1276 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1277 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1280 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1281 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1282 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1283 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1284 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1285 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1288 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1289 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1290 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1291 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1292 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1293 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1296 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1297 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1299 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1300 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1301 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1304 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1305 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1307 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1308 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1309 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1312 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx); in rtw8922a_ctrl_bw()
1313 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1315 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1316 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1317 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1328 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx); in rtw8922a_ctrl_bw()
1334 return 0; in rtw8922a_spur_freq()
1349 if (spur_freq == 0) { in rtw8922a_set_csi_tone_idx()
1351 0, phy_idx); in rtw8922a_set_csi_tone_idx()
1366 .notch1_idx = {0x41a0, 0xFF},
1367 .notch1_frac_idx = {0x41a0, 0xC00},
1368 .notch1_en = {0x41a0, 0x1000},
1369 .notch2_idx = {0x41ac, 0xFF},
1370 .notch2_frac_idx = {0x41ac, 0xC00},
1371 .notch2_en = {0x41ac, 0x1000},
1374 .notch1_idx = {0x45a0, 0xFF},
1375 .notch1_frac_idx = {0x45a0, 0xC00},
1376 .notch1_en = {0x45a0, 0x1000},
1377 .notch2_idx = {0x45ac, 0xFF},
1378 .notch2_frac_idx = {0x45ac, 0xC00},
1379 .notch2_en = {0x45ac, 0x1000},
1396 if (spur_freq == 0) { in rtw8922a_set_nbi_tone_idx()
1398 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1400 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1436 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1440 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1448 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1452 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1468 u32 cr_ofst = 0x0; in rtw8922a_ctrl_afe_dac()
1471 cr_ofst = 0x100; in rtw8922a_ctrl_afe_dac()
1479 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE); in rtw8922a_ctrl_afe_dac()
1480 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7); in rtw8922a_ctrl_afe_dac()
1483 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD); in rtw8922a_ctrl_afe_dac()
1484 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6); in rtw8922a_ctrl_afe_dac()
1492 {0x6990, 0x00000000},
1493 {0x6994, 0x00000000},
1494 {0x6998, 0x00000000},
1495 {0x6820, 0xFFFFFFFE},
1496 {0x6800, 0xC0000FFE},
1497 {0x6808, 0x76543210},
1498 {0x6814, 0xBFBFB000},
1499 {0x6818, 0x0478C009},
1500 {0x6800, 0xC0000FFF},
1501 {0x6820, 0xFFFFFFFF},
1505 {0x6990, 0x00000000},
1506 {0x6994, 0x00000000},
1507 {0x6998, 0x00000000},
1508 {0x6820, 0xFFFFFFFE},
1509 {0x6800, 0xC0000FFE},
1510 {0x6808, 0x76543210},
1511 {0x6814, 0xBFBFB000},
1512 {0x6818, 0x0478C009},
1513 {0x6800, 0xC0000FFF},
1514 {0x6820, 0xFFFFFFFF},
1531 for (i = 0; i < size; i++, reg++) in rtw8922a_bbmcu_cr_init()
1542 u32 rdy = 0; in rtw8922a_bb_preinit()
1547 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1548 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1549 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1550 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1552 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
1566 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200); in rtw8922a_bb_postinit()
1567 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1568 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1569 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA); in rtw8922a_bb_postinit()
1570 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1); in rtw8922a_bb_postinit()
1571 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1); in rtw8922a_bb_postinit()
1572 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0); in rtw8922a_bb_postinit()
1573 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0); in rtw8922a_bb_postinit()
1574 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0); in rtw8922a_bb_postinit()
1575 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0); in rtw8922a_bb_postinit()
1576 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1); in rtw8922a_bb_postinit()
1577 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1); in rtw8922a_bb_postinit()
1578 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1); in rtw8922a_bb_postinit()
1579 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1); in rtw8922a_bb_postinit()
1580 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0); in rtw8922a_bb_postinit()
1581 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000); in rtw8922a_bb_postinit()
1582 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0); in rtw8922a_bb_postinit()
1583 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0); in rtw8922a_bb_postinit()
1584 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200); in rtw8922a_bb_postinit()
1585 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx); in rtw8922a_bb_postinit()
1586 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx); in rtw8922a_bb_postinit()
1596 B_RXCCA_BE1_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1597 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1599 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1600 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1602 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); in rtw8922a_bb_reset_en()
1611 {0x11A00, 0x21C86900}, in rtw8922a_ctrl_tx_path_tmac()
1612 {0x11A04, 0x00E4E433}, in rtw8922a_ctrl_tx_path_tmac()
1613 {0x11A08, 0x39390CC9}, in rtw8922a_ctrl_tx_path_tmac()
1614 {0x11A0C, 0x4E433240}, in rtw8922a_ctrl_tx_path_tmac()
1615 {0x11A10, 0x90CC900E}, in rtw8922a_ctrl_tx_path_tmac()
1616 {0x11A14, 0x00240393}, in rtw8922a_ctrl_tx_path_tmac()
1617 {0x11A18, 0x201C8600}, in rtw8922a_ctrl_tx_path_tmac()
1619 int ret = 0; in rtw8922a_ctrl_tx_path_tmac()
1623 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx); in rtw8922a_ctrl_tx_path_tmac()
1626 return 0; in rtw8922a_ctrl_tx_path_tmac()
1629 path_com_cr[0].data = 0x21C82900; in rtw8922a_ctrl_tx_path_tmac()
1630 path_com_cr[1].data = 0x00E4E431; in rtw8922a_ctrl_tx_path_tmac()
1631 path_com_cr[2].data = 0x39390C49; in rtw8922a_ctrl_tx_path_tmac()
1632 path_com_cr[3].data = 0x4E431240; in rtw8922a_ctrl_tx_path_tmac()
1633 path_com_cr[4].data = 0x90C4900E; in rtw8922a_ctrl_tx_path_tmac()
1634 path_com_cr[6].data = 0x201C8200; in rtw8922a_ctrl_tx_path_tmac()
1636 path_com_cr[0].data = 0x21C04900; in rtw8922a_ctrl_tx_path_tmac()
1637 path_com_cr[1].data = 0x00E4E032; in rtw8922a_ctrl_tx_path_tmac()
1638 path_com_cr[2].data = 0x39380C89; in rtw8922a_ctrl_tx_path_tmac()
1639 path_com_cr[3].data = 0x4E032240; in rtw8922a_ctrl_tx_path_tmac()
1640 path_com_cr[4].data = 0x80C8900E; in rtw8922a_ctrl_tx_path_tmac()
1641 path_com_cr[6].data = 0x201C0400; in rtw8922a_ctrl_tx_path_tmac()
1643 path_com_cr[0].data = 0x21C86900; in rtw8922a_ctrl_tx_path_tmac()
1644 path_com_cr[1].data = 0x00E4E433; in rtw8922a_ctrl_tx_path_tmac()
1645 path_com_cr[2].data = 0x39390CC9; in rtw8922a_ctrl_tx_path_tmac()
1646 path_com_cr[3].data = 0x4E433240; in rtw8922a_ctrl_tx_path_tmac()
1647 path_com_cr[4].data = 0x90CC900E; in rtw8922a_ctrl_tx_path_tmac()
1648 path_com_cr[6].data = 0x201C8600; in rtw8922a_ctrl_tx_path_tmac()
1653 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) { in rtw8922a_ctrl_tx_path_tmac()
1669 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1670 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1673 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1674 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1675 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1676 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0, in rtw8922a_cfg_rx_nss_limit()
1696 return 0; in rtw8922a_cfg_rx_nss_limit()
1705 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1706 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1708 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1709 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1712 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1713 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1714 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1715 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1725 /* Set to 0 first to avoid abnormal EDCCA report */ in rtw8922a_ctrl_rx_path_tmac()
1726 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1729 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1734 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1739 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1747 return 0; in rtw8922a_ctrl_rx_path_tmac()
1752 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1753 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
1754 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
1755 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
1756 0x0D0C0907, 0x12121210},
1757 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1758 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
1759 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
1760 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
1761 0x100D0B08, 0x15151512},
1774 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; in rtw8922a_set_digital_pwr_comp()
1779 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { in rtw8922a_set_digital_pwr_comp()
1780 val = enable ? digital_pwr_comp[i] : 0; in rtw8922a_set_digital_pwr_comp()
1809 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1); in rtw8922a_ctrl_mlo()
1810 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0); in rtw8922a_ctrl_mlo()
1813 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_ctrl_mlo()
1814 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1); in rtw8922a_ctrl_mlo()
1820 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1826 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1833 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_ctrl_mlo()
1836 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1837 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_ctrl_mlo()
1838 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_ctrl_mlo()
1839 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_ctrl_mlo()
1841 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1842 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_ctrl_mlo()
1843 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_ctrl_mlo()
1844 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_ctrl_mlo()
1846 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB); in rtw8922a_ctrl_mlo()
1847 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB); in rtw8922a_ctrl_mlo()
1848 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB); in rtw8922a_ctrl_mlo()
1850 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180); in rtw8922a_ctrl_mlo()
1851 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0); in rtw8922a_ctrl_mlo()
1854 return 0; in rtw8922a_ctrl_mlo()
1864 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1867 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1877 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1880 0, phy_idx); in rtw8922a_ctrl_cck_en()
1883 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1916 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1917 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_pre_set_channel_bb()
1918 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1919 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_pre_set_channel_bb()
1920 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_pre_set_channel_bb()
1921 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_pre_set_channel_bb()
1923 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1924 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1925 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_pre_set_channel_bb()
1926 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_pre_set_channel_bb()
1927 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_pre_set_channel_bb()
1956 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0; in rtw8922a_dfs_en_idx()
1959 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1, in rtw8922a_dfs_en_idx()
1962 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0, in rtw8922a_dfs_en_idx()
1982 val &= ~0x1; in rtw8922a_adc_en_path()
1984 val &= ~0x2; in rtw8922a_adc_en_path()
1987 val |= 0x1; in rtw8922a_adc_en_path()
1989 val |= 0x2; in rtw8922a_adc_en_path()
2056 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); in rtw8922a_rfk_init()
2084 for (path = 0; path < RF_PATH_NUM_8922A; path++) { in _wait_rx_mode()
2089 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
2141 s16 ref_ofdm = 0; in rtw8922a_set_txpwr_ref()
2142 s16 ref_cck = 0; in rtw8922a_set_txpwr_ref()
2155 u8 ctrl = en ? 0x1 : 0x0; in rtw8922a_bb_tx_triangular()
2173 if (tx_shape_idx == 0) in rtw8922a_set_tx_shape()
2213 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2215 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2217 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2218 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2219 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2220 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2221 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2222 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2223 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2225 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2227 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2228 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2229 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2230 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2231 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2232 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2234 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2236 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2238 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2239 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2240 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2241 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2242 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2243 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2244 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2246 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2248 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2249 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2250 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2251 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2252 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2253 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2294 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2295 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); in rtw8922a_get_thermal()
2296 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2303 return clamp_t(int, th, 0, U8_MAX); in rtw8922a_get_thermal()
2313 module->bt_solo = 0; in rtw8922a_btc_set_rfe()
2315 module->wa_type = 0; in rtw8922a_btc_set_rfe()
2320 module->ant.diversity = 0; in rtw8922a_btc_set_rfe()
2329 if (module->rfe_type == 0) { in rtw8922a_btc_set_rfe()
2336 if (module->kt_ver == 0) in rtw8922a_btc_set_rfe()
2379 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ in rtw8922a_btc_init_cfg()
2380 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2382 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ in rtw8922a_btc_init_cfg()
2383 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); in rtw8922a_btc_init_cfg()
2385 /* if GNT_WL = 0 && BT = Tx_group --> in rtw8922a_btc_init_cfg()
2386 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) in rtw8922a_btc_init_cfg()
2389 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); in rtw8922a_btc_init_cfg()
2391 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2393 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); in rtw8922a_btc_init_cfg()
2405 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2407 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2409 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff); in rtw8922a_btc_init_cfg()
2416 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0)); in rtw8922a_btc_set_wl_txpwr_ctrl()
2420 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2422 B_BE_FORCE_PWR_BY_RATE_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2424 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2430 B_BE_FORCE_PWR_BY_RATE_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2435 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2437 B_BE_PWR_BT_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2439 B_BE_PWR_BT_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2445 B_BE_PWR_BT_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2453 return clamp_t(s8, val, -100, 0) + 100; in rtw8922a_btc_get_bt_rssi()
2457 {255, 0, 0, 7}, /* 0 -> original */
2458 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2459 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2460 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2461 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2462 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2463 {6, 1, 0, 7},
2464 {13, 1, 0, 7},
2465 {13, 1, 0, 7}
2469 {255, 0, 0, 7}, /* 0 -> original */
2470 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2471 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2472 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2473 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2474 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2475 {255, 1, 0, 7},
2476 {255, 1, 0, 7},
2477 {255, 1, 0, 7}
2484 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2485 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2486 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2487 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2488 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2489 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2490 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2491 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2492 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2493 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2494 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2495 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2496 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2497 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2498 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2499 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2500 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2501 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2502 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2515 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2516 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2517 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2518 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2519 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2521 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2522 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2523 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2524 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2525 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2527 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2528 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2529 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2530 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2531 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2533 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2534 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2535 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2536 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2537 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2553 if (chan_idx == 0) in rtw8922a_fill_freq_with_ppdu()
2570 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { in rtw8922a_query_ppdu()
2582 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0}; in rtw8922a_convert_rpl_to_rssi()
2584 u8 compensate = 0; in rtw8922a_convert_rpl_to_rssi()
2591 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_convert_rpl_to_rssi()
2593 rssi[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2594 phy_ppdu->rpl_path[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2595 phy_ppdu->rpl_fd[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2614 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9); in rtw8922a_mac_enable_bb_rf()
2616 return 0; in rtw8922a_mac_enable_bb_rf()
2624 return 0; in rtw8922a_mac_disable_bb_rf()
2713 .dle_scc_rsvd_size = 0,
2716 .rsvd_ple_ofst = 0x8f800,
2721 .rf_base_addr = {0xe000, 0xf000},
2722 .thermal_th = {0xad, 0xb4},
2764 .physical_efuse_size = 0x1300,
2765 .logical_efuse_size = 0x70000,
2766 .limit_efuse_size = 0x40000,
2767 .dav_phy_efuse_size = 0,
2768 .dav_log_efuse_size = 0,
2770 .phycap_addr = 0x1700,
2771 .phycap_size = 0x38,
2772 .para_ver = 0xf,
2773 .wlcx_desired = 0x07110000,
2774 .btcx_desired = 0x7,
2775 .scbd = 0x1,
2776 .mailbox = 0x1,
2791 .low_power_hci_modes = 0,
2808 .dcfo_comp_sft = 0,
2817 .dma_ch_mask = 0,