Lines Matching full:path
134 static void _rfk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path) in _rfk_get_thermal() argument
138 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _rfk_get_thermal()
139 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0); in _rfk_get_thermal()
140 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _rfk_get_thermal()
144 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL); in _rfk_get_thermal()
147 dpk->bp[path][kidx].ther_dpk); in _rfk_get_thermal()
252 void _txck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool force, in _txck_force() argument
255 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); in _txck_force()
260 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck); in _txck_force()
261 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); in _txck_force()
265 void _rxck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool force, in _rxck_force() argument
270 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); in _rxck_force()
275 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck); in _rxck_force()
276 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); in _rxck_force()
293 rtw8852bx_adc_cfg(rtwdev, bw, path); in _rxck_force()
297 enum rtw89_rf_path path, u8 kpath) in _rfk_bb_afe_setting() argument
341 enum rtw89_rf_path path, u8 kpath) in _rfk_bb_afe_restore() argument
370 enum rtw89_rf_path path) in _set_rx_dck() argument
372 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); in _set_rx_dck()
373 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
374 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
380 u8 path, dck_tune; in _rx_dck() local
387 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _rx_dck()
388 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rx_dck()
389 dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); in _rx_dck()
391 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
393 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
396 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
397 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
398 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rx_dck()
399 _set_rx_dck(rtwdev, phy, path); in _rx_dck()
400 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); in _rx_dck()
401 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rx_dck()
403 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
405 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
410 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _rck() argument
417 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); in _rck()
419 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rck()
421 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
422 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rck()
425 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); in _rck()
428 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
431 false, rtwdev, path, RR_RCKS, BIT(3)); in _rck()
433 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); in _rck()
438 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); in _rck()
439 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rck()
442 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK)); in _rck()
530 void _dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _dack_reset() argument
532 if (path == RF_PATH_A) { in _dack_reset()
542 void _dack_reload_by_path(struct rtw89_dev *rtwdev, u8 path, u8 index) in _dack_reload_by_path() argument
554 if (path == RF_PATH_A) in _dack_reload_by_path()
569 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8); in _dack_reload_by_path()
578 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8); in _dack_reload_by_path()
587 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8); in _dack_reload_by_path()
596 tmp |= dack->msbk_d[path][index][i] << (i * 8); in _dack_reload_by_path()
603 tmp = (dack->biask_d[path][index] << 22) | in _dack_reload_by_path()
604 (dack->dadck_d[path][index] << 14); in _dack_reload_by_path()
615 void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _dack_reload() argument
620 _dack_reload_by_path(rtwdev, path, i); in _dack_reload()
923 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) in _iqk_check_cal() argument
952 u8 path, u8 ktype) in _iqk_one_shot() argument
960 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
963 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
966 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
969 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
972 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
973 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
976 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
979 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
980 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
983 iqk_cmd = 0x408 | (1 << (4 + path)); in _iqk_one_shot()
986 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
996 fail = _iqk_check_cal(rtwdev, path, ktype); in _iqk_one_shot()
1001 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txk_setting() argument
1005 switch (iqk_info->iqk_band[path]) { in _iqk_txk_setting()
1007 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1008 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); in _iqk_txk_setting()
1009 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1010 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1011 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1012 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00); in _iqk_txk_setting()
1013 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1014 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_txk_setting()
1015 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x5); in _iqk_txk_setting()
1019 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1); in _iqk_txk_setting()
1020 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1021 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1022 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80); in _iqk_txk_setting()
1023 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1024 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_txk_setting()
1025 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4); in _iqk_txk_setting()
1033 static bool _iqk_2g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_2g_lok() argument
1037 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_2g_lok()
1039 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_2g_lok()
1041 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4)); in _iqk_2g_lok()
1043 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE); in _iqk_2g_lok()
1047 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_2g_lok()
1049 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_2g_lok()
1050 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_2g_lok()
1052 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER); in _iqk_2g_lok()
1056 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_2g_lok()
1058 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_2g_lok()
1059 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4)); in _iqk_2g_lok()
1061 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE); in _iqk_2g_lok()
1065 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_2g_lok()
1067 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_2g_lok()
1068 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_2g_lok()
1070 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER); in _iqk_2g_lok()
1078 static bool _iqk_5g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_5g_lok() argument
1082 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_5g_lok()
1084 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_5g_lok()
1086 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4)); in _iqk_5g_lok()
1088 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE); in _iqk_5g_lok()
1092 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_5g_lok()
1094 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_5g_lok()
1095 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_5g_lok()
1097 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER); in _iqk_5g_lok()
1101 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_5g_lok()
1103 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_5g_lok()
1104 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4)); in _iqk_5g_lok()
1106 _iqk_check_cal(rtwdev, path, ID_FLOK_COARSE); in _iqk_5g_lok()
1110 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_5g_lok()
1112 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_5g_lok()
1113 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_5g_lok()
1115 _iqk_check_cal(rtwdev, path, ID_FLOK_VBUFFER); in _iqk_5g_lok()
1122 static bool _iqk_2g_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_2g_tx() argument
1136 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _iqk_2g_tx()
1138 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _iqk_2g_tx()
1140 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _iqk_2g_tx()
1142 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_tx()
1144 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_tx()
1146 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_tx()
1148 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_tx()
1152 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_2g_tx()
1154 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); in _iqk_2g_tx()
1155 iqk_info->nb_txcfir[path] = in _iqk_2g_tx()
1156 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_2g_tx()
1161 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_2g_tx()
1163 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); in _iqk_2g_tx()
1168 path, gp, 1 << path, iqk_info->nb_txcfir[path]); in _iqk_2g_tx()
1175 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_2g_tx()
1176 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _iqk_2g_tx()
1183 static bool _iqk_5g_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_5g_tx() argument
1195 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]); in _iqk_5g_tx()
1196 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]); in _iqk_5g_tx()
1197 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]); in _iqk_5g_tx()
1199 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_5g_tx()
1201 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_tx()
1203 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_tx()
1205 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_tx()
1207 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_tx()
1211 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_5g_tx()
1214 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); in _iqk_5g_tx()
1215 iqk_info->nb_txcfir[path] = in _iqk_5g_tx()
1216 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_5g_tx()
1221 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_5g_tx()
1223 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); in _iqk_5g_tx()
1228 path, gp, 1 << path, iqk_info->nb_txcfir[path]); in _iqk_5g_tx()
1235 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_5g_tx()
1236 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _iqk_5g_tx()
1244 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_adc_fifo_rst() argument
1251 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxclk_setting() argument
1258 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { in _iqk_rxclk_setting()
1309 static bool _iqk_2g_rx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_2g_rx() argument
1324 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_2g_rx()
1325 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_2g_rx()
1326 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_2g_rx()
1327 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18); in _iqk_2g_rx()
1330 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]); in _iqk_2g_rx()
1331 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, g_idxattc2[gp]); in _iqk_2g_rx()
1332 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, g_idxattc1[gp]); in _iqk_2g_rx()
1334 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_rx()
1336 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_rx()
1338 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_2g_rx()
1340 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_2g_rx()
1344 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_2g_rx()
1350 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC); in _iqk_2g_rx()
1352 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, rf rxbb = %x\n", path, in _iqk_2g_rx()
1353 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0)); in _iqk_2g_rx()
1355 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_2g_rx()
1361 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); in _iqk_2g_rx()
1362 iqk_info->nb_rxcfir[path] = in _iqk_2g_rx()
1363 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _iqk_2g_rx()
1366 "[IQK]S%x, gp = 0x%x, 0x8%x3c = 0x%x\n", path, in _iqk_2g_rx()
1367 g_idx[gp], 1 << path, iqk_info->nb_rxcfir[path]); in _iqk_2g_rx()
1376 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); in _iqk_2g_rx()
1385 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_2g_rx()
1386 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _iqk_2g_rx()
1389 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_2g_rx()
1394 static bool _iqk_5g_rx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_5g_rx() argument
1409 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_5g_rx()
1410 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_5g_rx()
1411 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_5g_rx()
1412 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18); in _iqk_5g_rx()
1415 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, a_idxrxgain[gp]); in _iqk_5g_rx()
1416 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, a_idxattc2[gp]); in _iqk_5g_rx()
1417 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, a_idxattc1[gp]); in _iqk_5g_rx()
1419 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_rx()
1421 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_rx()
1423 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_5g_rx()
1425 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_5g_rx()
1429 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_5g_rx()
1435 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC); in _iqk_5g_rx()
1437 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, rf rxbb = %x\n", path, in _iqk_5g_rx()
1438 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0)); in _iqk_5g_rx()
1440 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_5g_rx()
1444 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); in _iqk_5g_rx()
1445 iqk_info->nb_rxcfir[path] = in _iqk_5g_rx()
1446 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _iqk_5g_rx()
1450 path, a_idx[gp], 1 << path, iqk_info->nb_rxcfir[path]); in _iqk_5g_rx()
1458 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); in _iqk_5g_rx()
1467 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_5g_rx()
1468 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _iqk_5g_rx()
1471 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_5g_rx()
1476 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_by_path() argument
1485 _iqk_txk_setting(rtwdev, path); in _iqk_by_path()
1486 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _iqk_by_path()
1487 lok_result = _iqk_2g_lok(rtwdev, phy_idx, path); in _iqk_by_path()
1489 lok_result = _iqk_5g_lok(rtwdev, phy_idx, path); in _iqk_by_path()
1498 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_by_path()
1499 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_by_path()
1500 rtw89_write_rf(rtwdev, path, RR_LOKVB, RFREG_MASK, 0x80200); in _iqk_by_path()
1504 rtw89_read_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK)); in _iqk_by_path()
1506 rtw89_read_rf(rtwdev, path, RR_RSV2, RFREG_MASK)); in _iqk_by_path()
1508 rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK)); in _iqk_by_path()
1510 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _iqk_by_path()
1511 txk_result = _iqk_2g_tx(rtwdev, phy_idx, path); in _iqk_by_path()
1513 txk_result = _iqk_5g_tx(rtwdev, phy_idx, path); in _iqk_by_path()
1515 _iqk_rxclk_setting(rtwdev, path); in _iqk_by_path()
1516 _iqk_adc_fifo_rst(rtwdev, phy_idx, path); in _iqk_by_path()
1518 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _iqk_by_path()
1519 rxk_result = _iqk_2g_rx(rtwdev, phy_idx, path); in _iqk_by_path()
1521 rxk_result = _iqk_5g_rx(rtwdev, phy_idx, path); in _iqk_by_path()
1528 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path, in _iqk_get_ch_info() argument
1539 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1547 idx = iqk_info->iqk_table_idx[path] + 1; in _iqk_get_ch_info()
1553 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_get_ch_info()
1556 iqk_info->iqk_band[path] = chan->band_type; in _iqk_get_ch_info()
1557 iqk_info->iqk_bw[path] = chan->band_width; in _iqk_get_ch_info()
1558 iqk_info->iqk_ch[path] = chan->channel; in _iqk_get_ch_info()
1559 iqk_info->iqk_mcc_ch[idx][path] = chan->channel; in _iqk_get_ch_info()
1560 iqk_info->iqk_table_idx[path] = idx; in _iqk_get_ch_info()
1563 path, reg_rf18, idx); in _iqk_get_ch_info()
1565 path, reg_rf18); in _iqk_get_ch_info()
1567 path, reg_35c); in _iqk_get_ch_info()
1571 idx, path, iqk_info->iqk_mcc_ch[idx][path]); in _iqk_get_ch_info()
1574 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_start_iqk() argument
1576 _iqk_by_path(rtwdev, phy_idx, path); in _iqk_start_iqk()
1579 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) in _iqk_restore() argument
1586 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), in _iqk_restore()
1587 MASKDWORD, iqk_info->nb_txcfir[path]); in _iqk_restore()
1588 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _iqk_restore()
1589 MASKDWORD, iqk_info->nb_rxcfir[path]); in _iqk_restore()
1591 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), in _iqk_restore()
1593 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _iqk_restore()
1597 0x00000e19 + (path << 4)); in _iqk_restore()
1599 _iqk_check_cal(rtwdev, path, 0x0); in _iqk_restore()
1607 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), BIT(28), 0x0); in _iqk_restore()
1609 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1610 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1611 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3); in _iqk_restore()
1612 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1613 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _iqk_restore()
1617 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_afebb_restore() argument
1641 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) in _iqk_preset() argument
1645 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), 0x00000001, idx); in _iqk_preset()
1646 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 0x00000008, idx); in _iqk_preset()
1647 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_preset()
1648 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_preset()
1650 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1651 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _iqk_preset()
1657 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_macbb_setting() argument
1702 u8 idx, path; in _iqk_init() local
1720 for (path = 0; path < RTW8852BT_SS; path++) { in _iqk_init()
1721 iqk_info->lok_cor_fail[idx][path] = false; in _iqk_init()
1722 iqk_info->lok_fin_fail[idx][path] = false; in _iqk_init()
1723 iqk_info->iqk_tx_fail[idx][path] = false; in _iqk_init()
1724 iqk_info->iqk_rx_fail[idx][path] = false; in _iqk_init()
1725 iqk_info->iqk_mcc_ch[idx][path] = 0x0; in _iqk_init()
1726 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1734 u8 path; in _wait_rx_mode() local
1737 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
1738 if (!(kpath & BIT(path))) in _wait_rx_mode()
1743 rtwdev, path, RR_MOD, RR_MOD_MASK); in _wait_rx_mode()
1745 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret); in _wait_rx_mode()
1759 enum rtw89_phy_idx phy_idx, u8 path, in _doiqk() argument
1775 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx); in _doiqk()
1778 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path); in _doiqk()
1779 _iqk_macbb_setting(rtwdev, phy_idx, path); in _doiqk()
1780 _iqk_preset(rtwdev, path); in _doiqk()
1781 _iqk_start_iqk(rtwdev, phy_idx, path); in _doiqk()
1782 _iqk_restore(rtwdev, path); in _doiqk()
1783 _iqk_afebb_restore(rtwdev, phy_idx, path); in _doiqk()
1785 _rfk_reload_rf_reg(rtwdev, backup_rf_val[path], path); in _doiqk()
1811 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off) in _dpk_onoff() argument
1814 u8 val, kidx = dpk->cur_idx[path]; in _dpk_onoff()
1817 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; in _dpk_onoff()
1824 val = dpk->is_dpk_enable & off_reverse & dpk->bp[path][kidx].path_ok; in _dpk_onoff()
1826 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_onoff()
1829 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, in _dpk_onoff()
1834 enum rtw89_rf_path path, enum rtw8852bt_dpk_id id) in _dpk_one_shot() argument
1840 dpk_cmd = (id << 8) | (0x19 + (path << 4)); in _dpk_one_shot()
1874 enum rtw89_rf_path path) in _dpk_rx_dck() argument
1876 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _dpk_rx_dck()
1877 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _dpk_rx_dck()
1881 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d RXDCK\n", path); in _dpk_rx_dck()
1885 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_information() argument
1890 u8 kidx = dpk->cur_idx[path]; in _dpk_information()
1892 dpk->bp[path][kidx].band = chan->band_type; in _dpk_information()
1893 dpk->bp[path][kidx].ch = chan->channel; in _dpk_information()
1894 dpk->bp[path][kidx].bw = chan->band_width; in _dpk_information()
1898 path, dpk->cur_idx[path], phy, in _dpk_information()
1899 rtwdev->is_tssi_mode[path] ? "on" : "off", in _dpk_information()
1901 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1902 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", in _dpk_information()
1903 dpk->bp[path][kidx].ch, in _dpk_information()
1904 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1905 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); in _dpk_information()
1909 enum rtw89_rf_path path, bool is_pause) in _dpk_tssi_pause() argument
1911 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), in _dpk_tssi_pause()
1914 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, in _dpk_tssi_pause()
1919 enum rtw89_rf_path path) in _dpk_kip_restore() argument
1925 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_kip_restore()
1928 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); in _dpk_kip_restore()
1932 enum rtw89_rf_path path, u8 cur_rxbb, u32 rf_18) in _dpk_lbk_rxiqk() argument
1935 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0); in _dpk_lbk_rxiqk()
1937 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, rf_18); in _dpk_lbk_rxiqk()
1938 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd); in _dpk_lbk_rxiqk()
1939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1942 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13); in _dpk_lbk_rxiqk()
1944 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00); in _dpk_lbk_rxiqk()
1946 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05); in _dpk_lbk_rxiqk()
1948 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0); in _dpk_lbk_rxiqk()
1949 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1950 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014); in _dpk_lbk_rxiqk()
1957 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); in _dpk_lbk_rxiqk()
1961 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
1964 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); in _dpk_lbk_rxiqk()
1965 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5); in _dpk_lbk_rxiqk()
1969 enum rtw89_rf_path path, u8 kidx) in _dpk_rf_setting() argument
1973 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { in _dpk_rf_setting()
1974 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1975 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2); in _dpk_rf_setting()
1976 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1977 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1979 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1980 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5); in _dpk_rf_setting()
1981 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1982 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1983 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC); in _dpk_rf_setting()
1984 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0); in _dpk_rf_setting()
1985 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800); in _dpk_rf_setting()
1988 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
1989 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); in _dpk_rf_setting()
1990 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
1994 enum rtw89_rf_path path, bool is_bypass) in _dpk_bypass_rxcfir() argument
1997 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1999 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2002 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2004 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2010 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_tpg_sel() argument
2014 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) in _dpk_tpg_sel()
2016 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) in _dpk_tpg_sel()
2022 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : in _dpk_tpg_sel()
2023 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); in _dpk_tpg_sel()
2027 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_table_select() argument
2032 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); in _dpk_table_select()
2038 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_sync_check() argument
2056 path, corr_idx, corr_val); in _dpk_sync_check()
2058 dpk->corr_idx[path][kidx] = corr_idx; in _dpk_sync_check()
2059 dpk->corr_val[path][kidx] = corr_val; in _dpk_sync_check()
2071 path, dc_i, dc_q); in _dpk_sync_check()
2073 dpk->dc_i[path][kidx] = dc_i; in _dpk_sync_check()
2074 dpk->dc_q[path][kidx] = dc_q; in _dpk_sync_check()
2084 enum rtw89_rf_path path, u8 kidx) in _dpk_sync() argument
2086 _dpk_one_shot(rtwdev, phy, path, SYNC); in _dpk_sync()
2159 enum rtw89_rf_path path, u8 kidx) in _dpk_gainloss() argument
2161 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); in _dpk_gainloss()
2168 enum rtw89_rf_path path, u8 kidx) in _dpk_kip_preset() argument
2170 _dpk_tpg_sel(rtwdev, path, kidx); in _dpk_kip_preset()
2171 _dpk_one_shot(rtwdev, phy, path, KIP_PRESET); in _dpk_kip_preset()
2175 enum rtw89_rf_path path) in _dpk_kip_pwr_clk_on() argument
2179 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_pwr_clk_on()
2185 u8 _dpk_txagc_check_8852bt(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 txagc) in _dpk_txagc_check_8852bt() argument
2189 if (txagc >= dpk->max_dpk_txagc[path]) in _dpk_txagc_check_8852bt()
2190 txagc = dpk->max_dpk_txagc[path]; in _dpk_txagc_check_8852bt()
2198 enum rtw89_rf_path path, u8 txagc) in _dpk_kip_set_txagc() argument
2202 val = _dpk_txagc_check_8852bt(rtwdev, path, txagc); in _dpk_kip_set_txagc()
2203 rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, val); in _dpk_kip_set_txagc()
2205 _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC); in _dpk_kip_set_txagc()
2212 enum rtw89_rf_path path) in _dpk_kip_set_rxagc() argument
2216 _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC); in _dpk_kip_set_rxagc()
2221 enum rtw89_rf_path path, u8 txagc, s8 gain_offset) in _dpk_set_offset() argument
2223 txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK); in _dpk_set_offset()
2232 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_set_offset()
2239 static bool _dpk_pas_read(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _dpk_pas_read() argument
2282 enum rtw89_rf_path path, u8 kidx, u8 init_txagc, in _dpk_agc() argument
2297 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB); in _dpk_agc()
2298 rf_18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _dpk_agc()
2303 _dpk_sync(rtwdev, phy, path, kidx); in _dpk_agc()
2306 _dpk_bypass_rxcfir(rtwdev, path, true); in _dpk_agc()
2308 _dpk_lbk_rxiqk(rtwdev, phy, path, in _dpk_agc()
2312 if (_dpk_sync_check(rtwdev, path, kidx) == true) { in _dpk_agc()
2327 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB); in _dpk_agc()
2339 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB, tmp_rxbb); in _dpk_agc()
2344 _dpk_lbk_rxiqk(rtwdev, phy, path, tmp_rxbb, rf_18); in _dpk_agc()
2353 _dpk_gainloss(rtwdev, phy, path, kidx); in _dpk_agc()
2357 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, path, true)) || in _dpk_agc()
2369 tmp_txagc == dpk->max_dpk_txagc[path]) { in _dpk_agc()
2374 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, in _dpk_agc()
2382 if (tmp_txagc == 0x3f || tmp_txagc == dpk->max_dpk_txagc[path]) { in _dpk_agc()
2387 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, in _dpk_agc()
2395 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_txagc, in _dpk_agc()
2408 _dpk_pas_read(rtwdev, path, false); in _dpk_agc()
2417 enum rtw89_rf_path path, u8 order) in _dpk_set_mdpd_para() argument
2426 dpk->dpk_order[path] = 0x3; in _dpk_set_mdpd_para()
2432 dpk->dpk_order[path] = 0x1; in _dpk_set_mdpd_para()
2438 dpk->dpk_order[path] = 0x0; in _dpk_set_mdpd_para()
2455 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_idl_mpa() argument
2459 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 && in _dpk_idl_mpa()
2460 dpk->bp[path][kidx].band == RTW89_BAND_5G) in _dpk_idl_mpa()
2461 _dpk_set_mdpd_para(rtwdev, path, 0x2); in _dpk_idl_mpa()
2463 _dpk_set_mdpd_para(rtwdev, path, 0x0); in _dpk_idl_mpa()
2465 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); in _dpk_idl_mpa()
2469 enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc) in _dpk_fill_result() argument
2475 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), BIT(8), kidx); in _dpk_fill_result()
2481 dpk->bp[path][kidx].txagc_dpk = txagc; in _dpk_fill_result()
2482 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), in _dpk_fill_result()
2485 dpk->bp[path][kidx].pwsf = pwsf; in _dpk_fill_result()
2486 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_fill_result()
2489 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2490 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); in _dpk_fill_result()
2492 dpk->bp[path][kidx].gs = gs; in _dpk_fill_result()
2495 R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2499 R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2502 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2503 B_DPD_ORDER_V1, dpk->dpk_order[path]); in _dpk_fill_result()
2505 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0); in _dpk_fill_result()
2510 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_reload_check() argument
2521 if (cur_band != dpk->bp[path][idx].band || in _dpk_reload_check()
2522 cur_ch != dpk->bp[path][idx].ch) in _dpk_reload_check()
2525 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_reload_check()
2527 dpk->cur_idx[path] = idx; in _dpk_reload_check()
2530 "[DPK] reload S%d[%d] success\n", path, idx); in _dpk_reload_check()
2537 void _rf_direct_cntrl(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool is_bybb) in _rf_direct_cntrl() argument
2540 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rf_direct_cntrl()
2542 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rf_direct_cntrl()
2546 void _drf_direct_cntrl(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool is_bybb) in _drf_direct_cntrl() argument
2549 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _drf_direct_cntrl()
2551 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _drf_direct_cntrl()
2555 enum rtw89_rf_path path, u8 gain, in _dpk_main() argument
2559 u8 txagc = 0x38, kidx = dpk->cur_idx[path]; in _dpk_main()
2563 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx); in _dpk_main()
2565 _rf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2566 _drf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2568 _dpk_kip_pwr_clk_on(rtwdev, path); in _dpk_main()
2569 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_main()
2570 _dpk_rf_setting(rtwdev, gain, path, kidx); in _dpk_main()
2571 _dpk_rx_dck(rtwdev, phy, path); in _dpk_main()
2572 _dpk_kip_preset(rtwdev, phy, path, kidx); in _dpk_main()
2573 _dpk_kip_set_rxagc(rtwdev, phy, path); in _dpk_main()
2574 _dpk_table_select(rtwdev, path, kidx, gain); in _dpk_main()
2576 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx); in _dpk_main()
2578 _rfk_get_thermal(rtwdev, kidx, path); in _dpk_main()
2585 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); in _dpk_main()
2587 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, RF_RX); in _dpk_main()
2588 _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc); in _dpk_main()
2592 dpk->bp[path][kidx].path_ok = 1; in _dpk_main()
2594 dpk->bp[path][kidx].path_ok = 0; in _dpk_main()
2596 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2599 _dpk_onoff(rtwdev, path, is_fail); in _dpk_main()
2601 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2616 u8 path; in _dpk_cal_select() local
2618 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2619 reloaded[path] = _dpk_reload_check(rtwdev, phy, path, chanctx_idx); in _dpk_cal_select()
2620 if (!reloaded[path] && dpk->bp[path][0].ch != 0) in _dpk_cal_select()
2621 dpk->cur_idx[path] = !dpk->cur_idx[path]; in _dpk_cal_select()
2623 _dpk_onoff(rtwdev, path, false); in _dpk_cal_select()
2629 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2630 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path); in _dpk_cal_select()
2631 _dpk_information(rtwdev, phy, path, chanctx_idx); in _dpk_cal_select()
2632 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2633 _dpk_tssi_pause(rtwdev, path, true); in _dpk_cal_select()
2636 _rfk_bb_afe_setting(rtwdev, phy, path, kpath); in _dpk_cal_select()
2638 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) in _dpk_cal_select()
2639 _dpk_main(rtwdev, phy, path, 1, chanctx_idx); in _dpk_cal_select()
2641 _rfk_bb_afe_restore(rtwdev, phy, path, kpath); in _dpk_cal_select()
2643 _dpk_kip_restore(rtwdev, path); in _dpk_cal_select()
2647 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2648 _rfk_reload_rf_reg(rtwdev, backup_rf_val[path], path); in _dpk_cal_select()
2649 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2650 _dpk_tssi_pause(rtwdev, path, false); in _dpk_cal_select()
2679 u8 path, kpath; in _dpk_force_bypass() local
2683 for (path = 0; path < RTW8852BT_SS; path++) { in _dpk_force_bypass()
2684 if (kpath & BIT(path)) in _dpk_force_bypass()
2685 _dpk_onoff(rtwdev, path, true); in _dpk_force_bypass()
2695 u8 path, kidx; in _dpk_track() local
2700 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _dpk_track()
2701 kidx = dpk->cur_idx[path]; in _dpk_track()
2705 path, kidx, dpk->bp[path][kidx].ch); in _dpk_track()
2707 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_track()
2712 if (dpk->bp[path][kidx].ch && cur_ther) in _dpk_track()
2713 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; in _dpk_track()
2715 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) in _dpk_track()
2716 delta_ther[path] = delta_ther[path] * 3 / 2; in _dpk_track()
2718 delta_ther[path] = delta_ther[path] * 5 / 2; in _dpk_track()
2720 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2723 if (rtwdev->is_tssi_mode[path]) { in _dpk_track()
2724 trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); in _dpk_track()
2731 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2734 rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13), in _dpk_track()
2742 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2747 txagc_ofst, delta_ther[path]); in _dpk_track()
2748 tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_track()
2757 ini_diff = txagc_ofst + (delta_ther[path]); in _dpk_track()
2760 R_P0_TXDPD + (path << 13), in _dpk_track()
2763 pwsf[0] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2765 pwsf[1] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2768 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2769 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2772 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2773 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2783 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2786 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2795 u8 tx_scale, ofdm_bkof, path, kpath; in _set_dpd_backoff() local
2805 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _set_dpd_backoff()
2806 if (!(kpath & BIT(path))) in _set_dpd_backoff()
2809 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8), in _set_dpd_backoff()
2812 "[RFK] Set S%d DPD backoff to 0dB\n", path); in _set_dpd_backoff()
2826 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_rf_setting() argument
2831 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2833 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2837 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_set_sys() argument
2848 if (path == RF_PATH_A) in _tssi_set_sys()
2860 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb() argument
2862 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb()
2869 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2871 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb_he_tb()
2877 enum rtw89_rf_path path) in _tssi_set_dck() argument
2879 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dck()
2885 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_set_tmeter_tbl() argument
2939 if (path == RF_PATH_A) { in _tssi_set_tmeter_tbl()
3045 enum rtw89_rf_path path) in _tssi_set_dac_gain_tbl() argument
3047 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dac_gain_tbl()
3053 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_slope_cal_org() argument
3057 if (path == RF_PATH_A) in _tssi_slope_cal_org()
3068 enum rtw89_rf_path path, bool all, in _tssi_alignment_default() argument
3075 if (path == RF_PATH_A) { in _tssi_alignment_default()
3100 enum rtw89_rf_path path) in _tssi_set_tssi_slope() argument
3102 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_tssi_slope()
3108 enum rtw89_rf_path path) in _tssi_set_tssi_track() argument
3110 if (path == RF_PATH_A) in _tssi_set_tssi_track()
3118 enum rtw89_rf_path path) in _tssi_set_txagc_offset_mv_avg() argument
3120 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__, in _tssi_set_txagc_offset_mv_avg()
3121 path); in _tssi_set_txagc_offset_mv_avg()
3123 if (path == RF_PATH_A) in _tssi_set_txagc_offset_mv_avg()
3315 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_de() argument
3327 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx); in _tssi_get_ofdm_de()
3332 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; in _tssi_get_ofdm_de()
3333 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; in _tssi_get_ofdm_de()
3337 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_de()
3338 path, val, de_1st, de_2nd); in _tssi_get_ofdm_de()
3340 val = tssi_info->tssi_mcs[path][gidx]; in _tssi_get_ofdm_de()
3343 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); in _tssi_get_ofdm_de()
3350 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_trim_de() argument
3362 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3363 path, tgidx); in _tssi_get_ofdm_trim_de()
3368 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; in _tssi_get_ofdm_trim_de()
3369 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; in _tssi_get_ofdm_trim_de()
3373 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_trim_de()
3374 path, val, tde_1st, tde_2nd); in _tssi_get_ofdm_trim_de()
3376 val = tssi_info->tssi_trim[path][tgidx]; in _tssi_get_ofdm_trim_de()
3379 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", in _tssi_get_ofdm_trim_de()
3380 path, val); in _tssi_get_ofdm_trim_de()
3406 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3423 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3442 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _tssi_alimentk_dump_result() argument
3447 R_TSSI_PA_K1 + (path << 13), in _tssi_alimentk_dump_result()
3448 rtw89_phy_read32(rtwdev, R_TSSI_PA_K1 + (path << 13)), in _tssi_alimentk_dump_result()
3449 R_TSSI_PA_K2 + (path << 13), in _tssi_alimentk_dump_result()
3450 rtw89_phy_read32(rtwdev, R_TSSI_PA_K2 + (path << 13)), in _tssi_alimentk_dump_result()
3451 R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk_dump_result()
3452 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM1 + (path << 13)), in _tssi_alimentk_dump_result()
3453 R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk_dump_result()
3454 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM3 + (path << 13)), in _tssi_alimentk_dump_result()
3455 R_TSSI_PA_K5 + (path << 13), in _tssi_alimentk_dump_result()
3456 rtw89_phy_read32(rtwdev, R_TSSI_PA_K5 + (path << 13)), in _tssi_alimentk_dump_result()
3457 R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk_dump_result()
3458 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM2 + (path << 13)), in _tssi_alimentk_dump_result()
3459 R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk_dump_result()
3460 rtw89_phy_read32(rtwdev, R_P0_TSSI_ALIM4 + (path << 13)), in _tssi_alimentk_dump_result()
3461 R_TSSI_PA_K8 + (path << 13), in _tssi_alimentk_dump_result()
3462 rtw89_phy_read32(rtwdev, R_TSSI_PA_K8 + (path << 13))); in _tssi_alimentk_dump_result()
3466 enum rtw89_phy_idx phy, enum rtw89_rf_path path, in _tssi_alimentk_done() argument
3474 "======>%s phy=%d path=%d\n", __func__, phy, path); in _tssi_alimentk_done()
3487 if (tssi_info->alignment_done[path][band]) { in _tssi_alimentk_done()
3488 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3489 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk_done()
3490 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3491 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk_done()
3492 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3493 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk_done()
3494 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3495 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk_done()
3498 _tssi_alimentk_dump_result(rtwdev, path); in _tssi_alimentk_done()
3502 enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm, in _tssi_hw_tx() argument
3507 if (path == RF_PATH_A) in _tssi_hw_tx()
3509 else if (path == RF_PATH_B) in _tssi_hw_tx()
3511 else if (path == RF_PATH_AB) in _tssi_hw_tx()
3514 rx_path = RF_ABCD; /* don't change path, but still set others */ in _tssi_hw_tx()
3518 rtw8852bx_bb_cfg_tx_path(rtwdev, path); in _tssi_hw_tx()
3576 enum rtw89_rf_path path, const s16 *power, in _tssi_get_cw_report() argument
3585 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0); in _tssi_get_cw_report()
3586 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1); in _tssi_get_cw_report()
3590 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD); in _tssi_get_cw_report()
3592 "[TSSI PA K] 0x%x = 0x%08x path=%d\n", in _tssi_get_cw_report()
3593 _tssi_trigger[path], tmp, path); in _tssi_get_cw_report()
3596 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true, in _tssi_get_cw_report()
3606 "[TSSI PA K] First HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3607 tx_counter_tmp, path); in _tssi_get_cw_report()
3610 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], in _tssi_get_cw_report()
3622 "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3623 k, tx_counter_tmp, path); in _tssi_get_cw_report()
3628 "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n", in _tssi_get_cw_report()
3629 k, path); in _tssi_get_cw_report()
3631 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan); in _tssi_get_cw_report()
3636 rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], in _tssi_get_cw_report()
3639 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan); in _tssi_get_cw_report()
3645 "[TSSI PA K] Final HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3646 tx_counter_tmp, path); in _tssi_get_cw_report()
3653 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_alimentk() argument
3675 "======> %s channel=%d path=%d\n", __func__, channel, in _tssi_alimentk()
3676 path); in _tssi_alimentk()
3705 ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt, chan); in _tssi_alimentk()
3715 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1], in _tssi_alimentk()
3722 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2], in _tssi_alimentk()
3727 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3], in _tssi_alimentk()
3732 if (path == RF_PATH_A) { in _tssi_alimentk()
3762 tssi_info->alignment_done[path][band] = true; in _tssi_alimentk()
3763 tssi_info->alignment_value[path][band][0] = in _tssi_alimentk()
3764 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3765 tssi_info->alignment_value[path][band][1] = in _tssi_alimentk()
3766 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3767 tssi_info->alignment_value[path][band][2] = in _tssi_alimentk()
3768 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3769 tssi_info->alignment_value[path][band][3] = in _tssi_alimentk()
3770 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3772 tssi_info->check_backup_aligmk[path][ch_idx] = true; in _tssi_alimentk()
3773 tssi_info->alignment_backup_by_ch[path][ch_idx][0] = in _tssi_alimentk()
3774 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3775 tssi_info->alignment_backup_by_ch[path][ch_idx][1] = in _tssi_alimentk()
3776 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3777 tssi_info->alignment_backup_by_ch[path][ch_idx][2] = in _tssi_alimentk()
3778 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3779 tssi_info->alignment_backup_by_ch[path][ch_idx][3] = in _tssi_alimentk()
3780 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3783 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n", in _tssi_alimentk()
3784 path, band, R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk()
3785 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk()
3787 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n", in _tssi_alimentk()
3788 path, band, R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk()
3789 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk()
3791 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", in _tssi_alimentk()
3792 path, band, R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk()
3793 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk()
3795 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n", in _tssi_alimentk()
3796 path, band, R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk()
3797 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk()
3817 u8 path; in rtw8852bt_dpk_init() local
3819 for (path = 0; path < 2; path++) { in rtw8852bt_dpk_init()
3820 dpk->cur_idx[path] = 0; in rtw8852bt_dpk_init()
3821 dpk->max_dpk_txagc[path] = 0x3F; in rtw8852bt_dpk_init()
3831 u8 path; in rtw8852bt_rck() local
3833 for (path = 0; path < RF_PATH_NUM_8852BT; path++) in rtw8852bt_rck()
3834 _rck(rtwdev, path); in rtw8852bt_rck()
4029 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _bw_setting() argument
4037 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _bw_setting()
4040 "[RFK]Invalid RF_0x18 for Path-%d\n", path); in _bw_setting()
4064 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _bw_setting()
4066 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n", in _bw_setting()
4067 bw, path, reg18_addr, in _bw_setting()
4068 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _bw_setting()
4158 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _ch_setting() argument
4167 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _ch_setting()
4180 if (path == RF_PATH_A && dav) in _ch_setting()
4183 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _ch_setting()
4185 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0); in _ch_setting()
4186 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1); in _ch_setting()
4189 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", in _ch_setting()
4190 central_ch, path, reg18_addr, in _ch_setting()
4191 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _ch_setting()
4203 enum rtw89_rf_path path) in _set_rxbb_bw() argument
4205 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); in _set_rxbb_bw()
4206 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12); in _set_rxbb_bw()
4209 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b); in _set_rxbb_bw()
4211 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13); in _set_rxbb_bw()
4213 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb); in _set_rxbb_bw()
4215 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3); in _set_rxbb_bw()
4218 path, rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB)); in _set_rxbb_bw()
4220 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); in _set_rxbb_bw()
4226 u8 kpath, path; in _rxbb_bw() local
4230 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _rxbb_bw()
4231 if (!(kpath & BIT(path))) in _rxbb_bw()
4234 _set_rxbb_bw(rtwdev, bw, path); in _rxbb_bw()