Lines Matching full:path
235 enum rtw89_rf_path path, bool is_bybb) in _rfk_rf_direct_cntrl() argument
238 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rfk_rf_direct_cntrl()
240 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rfk_rf_direct_cntrl()
244 enum rtw89_rf_path path, bool is_bybb) in _rfk_drf_direct_cntrl() argument
247 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _rfk_drf_direct_cntrl()
249 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _rfk_drf_direct_cntrl()
252 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path) in _iqk_check_cal() argument
269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); in _iqk_check_cal()
271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val); in _iqk_check_cal()
295 enum rtw89_rf_path path) in _set_rx_dck() argument
297 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); in _set_rx_dck()
298 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
299 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
305 u8 path, dck_tune; in _rx_dck() local
312 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rx_dck()
313 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rx_dck()
314 dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); in _rx_dck()
316 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
318 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
321 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
322 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
323 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rx_dck()
324 _set_rx_dck(rtwdev, phy, path); in _rx_dck()
325 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); in _rx_dck()
326 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rx_dck()
328 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
330 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
335 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _rck() argument
342 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); in _rck()
344 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rck()
346 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
347 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rck()
350 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); in _rck()
353 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
356 false, rtwdev, path, RR_RCKS, BIT(3)); in _rck()
358 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); in _rck()
363 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); in _rck()
364 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rck()
367 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK)); in _rck()
487 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_addc() argument
493 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_addc()
507 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
587 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_dadc() argument
589 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
593 _check_addc(rtwdev, path); in _check_dadc()
595 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
791 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxk_setting() argument
796 switch (iqk_info->iqk_band[path]) { in _iqk_rxk_setting()
798 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
799 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
800 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
801 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
804 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
805 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
806 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
807 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
815 u8 path, u8 ktype) in _iqk_one_shot() argument
824 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
828 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
832 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
836 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
837 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
840 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
844 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
850 iqk_cmd = 0x408 | (1 << (4 + path)); in _iqk_one_shot()
855 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
863 fail = _iqk_check_cal(rtwdev, path); in _iqk_one_shot()
870 u8 path) in _rxk_group_sel() argument
878 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
880 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _rxk_group_sel()
882 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, in _rxk_group_sel()
884 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, in _rxk_group_sel()
888 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _rxk_group_sel()
890 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, in _rxk_group_sel()
892 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, in _rxk_group_sel()
899 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
901 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
903 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
905 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); in _rxk_group_sel()
907 BIT(16 + gp + path * 4), fail); in _rxk_group_sel()
910 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
913 iqk_info->nb_rxcfir[path] = 0x40000002; in _rxk_group_sel()
914 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
916 iqk_info->is_wb_rxiqk[path] = false; in _rxk_group_sel()
918 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
919 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
921 iqk_info->is_wb_rxiqk[path] = true; in _rxk_group_sel()
928 u8 path) in _iqk_nbrxk() argument
935 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
937 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _iqk_nbrxk()
939 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, in _iqk_nbrxk()
941 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, in _iqk_nbrxk()
945 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _iqk_nbrxk()
947 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, in _iqk_nbrxk()
949 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, in _iqk_nbrxk()
956 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbrxk()
957 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0); in _iqk_nbrxk()
958 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp); in _iqk_nbrxk()
959 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_nbrxk()
962 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); in _iqk_nbrxk()
963 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); in _iqk_nbrxk()
965 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
968 iqk_info->nb_rxcfir[path] = in _iqk_nbrxk()
969 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2; in _iqk_nbrxk()
971 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
976 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxclk_setting() argument
980 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { in _iqk_rxclk_setting()
1015 static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _txk_group_sel() argument
1023 switch (iqk_info->iqk_band[path]) { in _txk_group_sel()
1025 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _txk_group_sel()
1027 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _txk_group_sel()
1029 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _txk_group_sel()
1031 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1035 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _txk_group_sel()
1037 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _txk_group_sel()
1039 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _txk_group_sel()
1041 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1048 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1050 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1052 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1054 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1057 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); in _txk_group_sel()
1059 BIT(8 + gp + path * 4), fail); in _txk_group_sel()
1064 iqk_info->nb_txcfir[path] = 0x40000002; in _txk_group_sel()
1065 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1067 iqk_info->is_wb_txiqk[path] = false; in _txk_group_sel()
1069 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1070 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1072 iqk_info->is_wb_txiqk[path] = true; in _txk_group_sel()
1078 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_nbtxk() argument
1084 switch (iqk_info->iqk_band[path]) { in _iqk_nbtxk()
1086 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _iqk_nbtxk()
1088 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _iqk_nbtxk()
1090 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _iqk_nbtxk()
1092 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_nbtxk()
1096 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _iqk_nbtxk()
1098 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _iqk_nbtxk()
1100 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _iqk_nbtxk()
1102 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_nbtxk()
1109 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbtxk()
1110 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1); in _iqk_nbtxk()
1111 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0); in _iqk_nbtxk()
1112 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); in _iqk_nbtxk()
1114 kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); in _iqk_nbtxk()
1117 iqk_info->nb_txcfir[path] = in _iqk_nbtxk()
1118 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), in _iqk_nbtxk()
1121 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1126 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) in _lok_res_table() argument
1131 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); in _lok_res_table()
1133 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1134 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _lok_res_table()
1135 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1137 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1138 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); in _lok_res_table()
1139 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1140 rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1); in _lok_res_table()
1142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path, in _lok_res_table()
1143 rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK)); in _lok_res_table()
1146 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) in _lok_finetune_check() argument
1157 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); in _lok_finetune_check()
1167 iqk_info->lok_idac[ch][path] = tmp; in _lok_finetune_check()
1169 tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK); in _lok_finetune_check()
1178 iqk_info->lok_vbuf[ch][path] = tmp; in _lok_finetune_check()
1181 "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1182 iqk_info->lok_idac[ch][path]); in _lok_finetune_check()
1184 "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1185 iqk_info->lok_vbuf[ch][path]); in _lok_finetune_check()
1190 static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_lok() argument
1197 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1199 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1200 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); in _iqk_lok()
1203 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1204 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4); in _iqk_lok()
1210 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1212 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1215 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1221 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1222 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE); in _iqk_lok()
1223 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1225 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1227 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1230 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1236 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1237 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); in _iqk_lok()
1239 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1241 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1244 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1250 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1252 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE); in _iqk_lok()
1253 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1255 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1257 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1260 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1266 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1267 _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); in _iqk_lok()
1269 return _lok_finetune_check(rtwdev, path); in _iqk_lok()
1272 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txk_setting() argument
1276 switch (iqk_info->iqk_band[path]) { in _iqk_txk_setting()
1278 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00); in _iqk_txk_setting()
1279 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1280 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); in _iqk_txk_setting()
1281 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1282 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1283 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1284 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00); in _iqk_txk_setting()
1285 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1289 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1290 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1); in _iqk_txk_setting()
1291 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1292 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1293 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80); in _iqk_txk_setting()
1294 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1302 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txclk_setting() argument
1315 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_info_iqk() argument
1321 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1322 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag); in _iqk_info_iqk()
1323 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1324 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag); in _iqk_info_iqk()
1325 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1326 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag); in _iqk_info_iqk()
1327 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1328 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag); in _iqk_info_iqk()
1330 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); in _iqk_info_iqk()
1331 iqk_info->bp_iqkenable[path] = tmp; in _iqk_info_iqk()
1332 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1333 iqk_info->bp_txkresult[path] = tmp; in _iqk_info_iqk()
1334 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1335 iqk_info->bp_rxkresult[path] = tmp; in _iqk_info_iqk()
1339 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4)); in _iqk_info_iqk()
1342 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4), in _iqk_info_iqk()
1346 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_by_path() argument
1354 _iqk_txclk_setting(rtwdev, path); in _iqk_by_path()
1358 _lok_res_table(rtwdev, path, ibias++); in _iqk_by_path()
1359 _iqk_txk_setting(rtwdev, path); in _iqk_by_path()
1360 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path); in _iqk_by_path()
1366 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path); in _iqk_by_path()
1370 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); in _iqk_by_path()
1372 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1375 _iqk_rxclk_setting(rtwdev, path); in _iqk_by_path()
1376 _iqk_rxk_setting(rtwdev, path); in _iqk_by_path()
1378 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); in _iqk_by_path()
1380 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1382 _iqk_info_iqk(rtwdev, phy_idx, path); in _iqk_by_path()
1385 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path, in _iqk_get_ch_info() argument
1396 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1404 idx = iqk_info->iqk_table_idx[path] + 1; in _iqk_get_ch_info()
1410 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_get_ch_info()
1413 iqk_info->iqk_band[path] = chan->band_type; in _iqk_get_ch_info()
1414 iqk_info->iqk_bw[path] = chan->band_width; in _iqk_get_ch_info()
1415 iqk_info->iqk_ch[path] = chan->channel; in _iqk_get_ch_info()
1416 iqk_info->iqk_mcc_ch[idx][path] = chan->channel; in _iqk_get_ch_info()
1417 iqk_info->iqk_table_idx[path] = idx; in _iqk_get_ch_info()
1420 path, reg_rf18, idx); in _iqk_get_ch_info()
1422 path, reg_rf18); in _iqk_get_ch_info()
1426 idx, path, iqk_info->iqk_mcc_ch[idx][path]); in _iqk_get_ch_info()
1434 "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path, in _iqk_get_ch_info()
1439 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16), in _iqk_get_ch_info()
1440 iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1442 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16), in _iqk_get_ch_info()
1443 iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1444 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16), in _iqk_get_ch_info()
1445 iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1448 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_start_iqk() argument
1450 _iqk_by_path(rtwdev, phy_idx, path); in _iqk_start_iqk()
1453 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) in _iqk_restore() argument
1458 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1459 iqk_info->nb_txcfir[path]); in _iqk_restore()
1460 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1461 iqk_info->nb_rxcfir[path]); in _iqk_restore()
1463 0x00000e19 + (path << 4)); in _iqk_restore()
1464 fail = _iqk_check_cal(rtwdev, path); in _iqk_restore()
1474 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1475 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1476 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3); in _iqk_restore()
1477 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1478 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _iqk_restore()
1482 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_afebb_restore() argument
1507 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) in _iqk_preset() argument
1512 idx = iqk_info->iqk_table_idx[path]; in _iqk_preset()
1515 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx); in _iqk_preset()
1516 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx); in _iqk_preset()
1518 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1519 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _iqk_preset()
1523 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path, in _iqk_preset()
1524 rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD)); in _iqk_preset()
1525 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path, in _iqk_preset()
1526 rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD)); in _iqk_preset()
1530 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_macbb_setting() argument
1556 u8 idx, path; in _iqk_init() local
1573 for (path = 0; path < RTW8852B_IQK_SS; path++) { in _iqk_init()
1574 iqk_info->lok_cor_fail[idx][path] = false; in _iqk_init()
1575 iqk_info->lok_fin_fail[idx][path] = false; in _iqk_init()
1576 iqk_info->iqk_tx_fail[idx][path] = false; in _iqk_init()
1577 iqk_info->iqk_rx_fail[idx][path] = false; in _iqk_init()
1578 iqk_info->iqk_mcc_ch[idx][path] = 0x0; in _iqk_init()
1579 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1587 u8 path; in _wait_rx_mode() local
1590 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
1591 if (!(kpath & BIT(path))) in _wait_rx_mode()
1596 rtwdev, path, RR_MOD, RR_MOD_MASK); in _wait_rx_mode()
1598 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret); in _wait_rx_mode()
1612 enum rtw89_phy_idx phy_idx, u8 path, in _doiqk() argument
1628 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx); in _doiqk()
1631 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1632 _iqk_macbb_setting(rtwdev, phy_idx, path); in _doiqk()
1633 _iqk_preset(rtwdev, path); in _doiqk()
1634 _iqk_start_iqk(rtwdev, phy_idx, path); in _doiqk()
1635 _iqk_restore(rtwdev, path); in _doiqk()
1636 _iqk_afebb_restore(rtwdev, phy_idx, path); in _doiqk()
1638 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1665 u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path) in _dpk_bkup_kip() argument
1670 reg_bkup[path][i] = in _dpk_bkup_kip()
1671 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD); in _dpk_bkup_kip()
1673 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_bkup_kip()
1678 const u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path) in _dpk_reload_kip() argument
1683 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD, in _dpk_reload_kip()
1684 reg_bkup[path][i]); in _dpk_reload_kip()
1686 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_reload_kip()
1703 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off) in _dpk_onoff() argument
1706 u8 val, kidx = dpk->cur_idx[path]; in _dpk_onoff()
1708 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; in _dpk_onoff()
1710 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_onoff()
1713 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, in _dpk_onoff()
1718 enum rtw89_rf_path path, enum rtw8852b_dpk_id id) in _dpk_one_shot() argument
1724 dpk_cmd = (id << 8) | (0x19 + (path << 4)); in _dpk_one_shot()
1760 enum rtw89_rf_path path) in _dpk_rx_dck() argument
1762 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1763 _set_rx_dck(rtwdev, phy, path); in _dpk_rx_dck()
1767 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_information() argument
1772 u8 kidx = dpk->cur_idx[path]; in _dpk_information()
1774 dpk->bp[path][kidx].band = chan->band_type; in _dpk_information()
1775 dpk->bp[path][kidx].ch = chan->channel; in _dpk_information()
1776 dpk->bp[path][kidx].bw = chan->band_width; in _dpk_information()
1780 path, dpk->cur_idx[path], phy, in _dpk_information()
1781 rtwdev->is_tssi_mode[path] ? "on" : "off", in _dpk_information()
1783 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1784 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", in _dpk_information()
1785 dpk->bp[path][kidx].ch, in _dpk_information()
1786 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1787 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); in _dpk_information()
1792 enum rtw89_rf_path path, u8 kpath, in _dpk_bb_afe_setting() argument
1810 enum rtw89_rf_path path, u8 kpath, in _dpk_bb_afe_restore() argument
1827 enum rtw89_rf_path path, bool is_pause) in _dpk_tssi_pause() argument
1829 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), in _dpk_tssi_pause()
1832 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, in _dpk_tssi_pause()
1837 enum rtw89_rf_path path) in _dpk_kip_restore() argument
1842 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1); in _dpk_kip_restore()
1844 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); in _dpk_kip_restore()
1848 enum rtw89_rf_path path) in _dpk_lbk_rxiqk() argument
1853 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB); in _dpk_lbk_rxiqk()
1856 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0); in _dpk_lbk_rxiqk()
1858 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _dpk_lbk_rxiqk()
1859 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _dpk_lbk_rxiqk()
1860 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd); in _dpk_lbk_rxiqk()
1861 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1864 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13); in _dpk_lbk_rxiqk()
1866 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00); in _dpk_lbk_rxiqk()
1868 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05); in _dpk_lbk_rxiqk()
1870 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0); in _dpk_lbk_rxiqk()
1871 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1872 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014); in _dpk_lbk_rxiqk()
1878 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); in _dpk_lbk_rxiqk()
1880 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
1884 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
1887 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); in _dpk_lbk_rxiqk()
1888 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5); in _dpk_lbk_rxiqk()
1891 static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path) in _dpk_get_thermal() argument
1895 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1896 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0); in _dpk_get_thermal()
1897 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1901 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL); in _dpk_get_thermal()
1904 dpk->bp[path][kidx].ther_dpk); in _dpk_get_thermal()
1908 enum rtw89_rf_path path, u8 kidx) in _dpk_rf_setting() argument
1912 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { in _dpk_rf_setting()
1913 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1914 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2); in _dpk_rf_setting()
1915 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1916 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1918 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1919 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5); in _dpk_rf_setting()
1920 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1921 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1922 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC); in _dpk_rf_setting()
1923 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0); in _dpk_rf_setting()
1924 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800); in _dpk_rf_setting()
1927 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
1928 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); in _dpk_rf_setting()
1929 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
1933 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), in _dpk_rf_setting()
1934 rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK), in _dpk_rf_setting()
1935 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); in _dpk_rf_setting()
1939 enum rtw89_rf_path path, bool is_bypass) in _dpk_bypass_rxcfir() argument
1942 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1944 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1947 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
1948 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1951 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); in _dpk_bypass_rxcfir()
1952 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); in _dpk_bypass_rxcfir()
1954 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
1955 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1961 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_tpg_sel() argument
1965 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) in _dpk_tpg_sel()
1967 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) in _dpk_tpg_sel()
1973 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : in _dpk_tpg_sel()
1974 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); in _dpk_tpg_sel()
1978 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_table_select() argument
1983 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); in _dpk_table_select()
1989 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_sync_check() argument
2005 path, corr_idx, corr_val); in _dpk_sync_check()
2007 dpk->corr_idx[path][kidx] = corr_idx; in _dpk_sync_check()
2008 dpk->corr_val[path][kidx] = corr_val; in _dpk_sync_check()
2019 path, dc_i, dc_q); in _dpk_sync_check()
2021 dpk->dc_i[path][kidx] = dc_i; in _dpk_sync_check()
2022 dpk->dc_q[path][kidx] = dc_q; in _dpk_sync_check()
2032 enum rtw89_rf_path path, u8 kidx) in _dpk_sync() argument
2034 _dpk_one_shot(rtwdev, phy, path, SYNC); in _dpk_sync()
2036 return _dpk_sync_check(rtwdev, path, kidx); in _dpk_sync()
2109 enum rtw89_rf_path path, u8 kidx) in _dpk_gainloss() argument
2111 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_gainloss()
2112 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); in _dpk_gainloss()
2116 enum rtw89_rf_path path, u8 kidx) in _dpk_kip_preset() argument
2118 _dpk_tpg_sel(rtwdev, path, kidx); in _dpk_kip_preset()
2119 _dpk_one_shot(rtwdev, phy, path, KIP_PRESET); in _dpk_kip_preset()
2123 enum rtw89_rf_path path) in _dpk_kip_pwr_clk_on() argument
2127 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_pwr_clk_on()
2133 enum rtw89_rf_path path, u8 txagc) in _dpk_kip_set_txagc() argument
2135 rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc); in _dpk_kip_set_txagc()
2137 _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC); in _dpk_kip_set_txagc()
2144 enum rtw89_rf_path path) in _dpk_kip_set_rxagc() argument
2148 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _dpk_kip_set_rxagc()
2151 _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC); in _dpk_kip_set_rxagc()
2158 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB)); in _dpk_kip_set_rxagc()
2162 enum rtw89_rf_path path, s8 gain_offset) in _dpk_set_offset() argument
2166 txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK); in _dpk_set_offset()
2175 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_set_offset()
2224 enum rtw89_rf_path path, u8 kidx, u8 init_txagc, in _dpk_agc() argument
2240 if (_dpk_sync(rtwdev, phy, path, kidx)) { in _dpk_agc()
2255 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, in _dpk_agc()
2269 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB, in _dpk_agc()
2275 _dpk_bypass_rxcfir(rtwdev, path, true); in _dpk_agc()
2277 _dpk_lbk_rxiqk(rtwdev, phy, path); in _dpk_agc()
2288 _dpk_gainloss(rtwdev, phy, path, kidx); in _dpk_agc()
2306 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3); in _dpk_agc()
2318 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe); in _dpk_agc()
2324 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx); in _dpk_agc()
2371 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_idl_mpa() argument
2375 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 && in _dpk_idl_mpa()
2376 dpk->bp[path][kidx].band == RTW89_BAND_5G) in _dpk_idl_mpa()
2381 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); in _dpk_idl_mpa()
2385 enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc) in _dpk_fill_result() argument
2391 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_fill_result()
2398 dpk->bp[path][kidx].txagc_dpk = txagc; in _dpk_fill_result()
2399 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), in _dpk_fill_result()
2402 dpk->bp[path][kidx].pwsf = pwsf; in _dpk_fill_result()
2403 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_fill_result()
2406 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2407 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); in _dpk_fill_result()
2409 dpk->bp[path][kidx].gs = gs; in _dpk_fill_result()
2411 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2414 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2417 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2419 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0); in _dpk_fill_result()
2424 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_reload_check() argument
2435 if (cur_band != dpk->bp[path][idx].band || in _dpk_reload_check()
2436 cur_ch != dpk->bp[path][idx].ch) in _dpk_reload_check()
2439 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_reload_check()
2441 dpk->cur_idx[path] = idx; in _dpk_reload_check()
2444 "[DPK] reload S%d[%d] success\n", path, idx); in _dpk_reload_check()
2451 enum rtw89_rf_path path, u8 gain, in _dpk_main() argument
2455 u8 txagc = 0x38, kidx = dpk->cur_idx[path]; in _dpk_main()
2459 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx); in _dpk_main()
2461 _rfk_rf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2462 _rfk_drf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2464 _dpk_kip_pwr_clk_on(rtwdev, path); in _dpk_main()
2465 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_main()
2466 _dpk_rf_setting(rtwdev, gain, path, kidx); in _dpk_main()
2467 _dpk_rx_dck(rtwdev, phy, path); in _dpk_main()
2469 _dpk_kip_preset(rtwdev, phy, path, kidx); in _dpk_main()
2470 _dpk_kip_set_rxagc(rtwdev, phy, path); in _dpk_main()
2471 _dpk_table_select(rtwdev, path, kidx, gain); in _dpk_main()
2473 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx); in _dpk_main()
2479 _dpk_get_thermal(rtwdev, kidx, path); in _dpk_main()
2481 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); in _dpk_main()
2483 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _dpk_main()
2485 _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc); in _dpk_main()
2489 dpk->bp[path][kidx].path_ok = true; in _dpk_main()
2491 dpk->bp[path][kidx].path_ok = false; in _dpk_main()
2493 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2509 u8 path; in _dpk_cal_select() local
2512 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2513 reloaded[path] = _dpk_reload_check(rtwdev, phy, path, in _dpk_cal_select()
2515 if (!reloaded[path] && dpk->bp[path][0].ch) in _dpk_cal_select()
2516 dpk->cur_idx[path] = !dpk->cur_idx[path]; in _dpk_cal_select()
2518 _dpk_onoff(rtwdev, path, false); in _dpk_cal_select()
2521 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) in _dpk_cal_select()
2522 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2527 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2528 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2529 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2530 _dpk_information(rtwdev, phy, path, chanctx_idx); in _dpk_cal_select()
2531 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2532 _dpk_tssi_pause(rtwdev, path, true); in _dpk_cal_select()
2535 _dpk_bb_afe_setting(rtwdev, phy, path, kpath, chanctx_idx); in _dpk_cal_select()
2537 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2538 is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx); in _dpk_cal_select()
2539 _dpk_onoff(rtwdev, path, is_fail); in _dpk_cal_select()
2542 _dpk_bb_afe_restore(rtwdev, phy, path, kpath, chanctx_idx); in _dpk_cal_select()
2545 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2546 _dpk_kip_restore(rtwdev, path); in _dpk_cal_select()
2547 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2548 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2549 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2550 _dpk_tssi_pause(rtwdev, path, false); in _dpk_cal_select()
2579 u8 path, kpath; in _dpk_force_bypass() local
2583 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2584 if (kpath & BIT(path)) in _dpk_force_bypass()
2585 _dpk_onoff(rtwdev, path, true); in _dpk_force_bypass()
2609 u8 path, kidx; in _dpk_track() local
2614 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _dpk_track()
2615 kidx = dpk->cur_idx[path]; in _dpk_track()
2619 path, kidx, dpk->bp[path][kidx].ch); in _dpk_track()
2621 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_track()
2626 if (dpk->bp[path][kidx].ch && cur_ther) in _dpk_track()
2627 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; in _dpk_track()
2629 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) in _dpk_track()
2630 delta_ther[path] = delta_ther[path] * 3 / 2; in _dpk_track()
2632 delta_ther[path] = delta_ther[path] * 5 / 2; in _dpk_track()
2634 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2637 if (rtwdev->is_tssi_mode[path]) { in _dpk_track()
2638 trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); in _dpk_track()
2645 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2648 rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13), in _dpk_track()
2656 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2661 txagc_ofst, delta_ther[path]); in _dpk_track()
2662 tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_track()
2671 ini_diff = txagc_ofst + (delta_ther[path]); in _dpk_track()
2674 R_P0_TXDPD + (path << 13), in _dpk_track()
2677 pwsf[0] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2679 pwsf[1] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2682 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2683 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2687 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2688 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2698 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2701 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2710 u8 tx_scale, ofdm_bkof, path, kpath; in _set_dpd_backoff() local
2720 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _set_dpd_backoff()
2721 if (!(kpath & BIT(path))) in _set_dpd_backoff()
2724 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8), in _set_dpd_backoff()
2727 "[RFK] Set S%d DPD backoff to 0dB\n", path); in _set_dpd_backoff()
2735 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_rf_setting() argument
2740 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2742 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2746 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_set_sys() argument
2752 if (path == RF_PATH_A) in _tssi_set_sys()
2764 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb() argument
2766 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb()
2773 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2775 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb_he_tb()
2781 enum rtw89_rf_path path) in _tssi_set_dck() argument
2783 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dck()
2789 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_set_tmeter_tbl() argument
2842 if (path == RF_PATH_A) { in _tssi_set_tmeter_tbl()
2946 enum rtw89_rf_path path) in _tssi_set_dac_gain_tbl() argument
2948 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dac_gain_tbl()
2954 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_slope_cal_org() argument
2958 if (path == RF_PATH_A) in _tssi_slope_cal_org()
2969 enum rtw89_rf_path path, bool all, in _tssi_alignment_default() argument
2976 if (path == RF_PATH_A) { in _tssi_alignment_default()
3027 enum rtw89_rf_path path) in _tssi_set_tssi_slope() argument
3029 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_tssi_slope()
3035 enum rtw89_rf_path path) in _tssi_set_tssi_track() argument
3037 if (path == RF_PATH_A) in _tssi_set_tssi_track()
3045 enum rtw89_rf_path path) in _tssi_set_txagc_offset_mv_avg() argument
3047 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__, in _tssi_set_txagc_offset_mv_avg()
3048 path); in _tssi_set_txagc_offset_mv_avg()
3050 if (path == RF_PATH_A) in _tssi_set_txagc_offset_mv_avg()
3240 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_de() argument
3252 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx); in _tssi_get_ofdm_de()
3257 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; in _tssi_get_ofdm_de()
3258 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; in _tssi_get_ofdm_de()
3262 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_de()
3263 path, val, de_1st, de_2nd); in _tssi_get_ofdm_de()
3265 val = tssi_info->tssi_mcs[path][gidx]; in _tssi_get_ofdm_de()
3268 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); in _tssi_get_ofdm_de()
3275 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_trim_de() argument
3287 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3288 path, tgidx); in _tssi_get_ofdm_trim_de()
3293 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; in _tssi_get_ofdm_trim_de()
3294 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; in _tssi_get_ofdm_trim_de()
3298 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_trim_de()
3299 path, val, tde_1st, tde_2nd); in _tssi_get_ofdm_trim_de()
3301 val = tssi_info->tssi_trim[path][tgidx]; in _tssi_get_ofdm_trim_de()
3304 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", in _tssi_get_ofdm_trim_de()
3305 path, val); in _tssi_get_ofdm_trim_de()
3331 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3348 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3366 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _tssi_alimentk_dump_result() argument
3371 R_TSSI_PA_K1 + (path << 13), in _tssi_alimentk_dump_result()
3372 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3373 R_TSSI_PA_K2 + (path << 13), in _tssi_alimentk_dump_result()
3374 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3375 R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk_dump_result()
3376 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3377 R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk_dump_result()
3378 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3379 R_TSSI_PA_K5 + (path << 13), in _tssi_alimentk_dump_result()
3380 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3381 R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk_dump_result()
3382 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3383 R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk_dump_result()
3384 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3385 R_TSSI_PA_K8 + (path << 13), in _tssi_alimentk_dump_result()
3386 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD)); in _tssi_alimentk_dump_result()
3390 enum rtw89_phy_idx phy, enum rtw89_rf_path path, in _tssi_alimentk_done() argument
3398 "======>%s phy=%d path=%d\n", __func__, phy, path); in _tssi_alimentk_done()
3411 if (tssi_info->alignment_done[path][band]) { in _tssi_alimentk_done()
3412 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3413 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk_done()
3414 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3415 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk_done()
3416 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3417 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk_done()
3418 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3419 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk_done()
3422 _tssi_alimentk_dump_result(rtwdev, path); in _tssi_alimentk_done()
3426 enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm, in _tssi_hw_tx() argument
3431 if (path == RF_PATH_A) in _tssi_hw_tx()
3433 else if (path == RF_PATH_B) in _tssi_hw_tx()
3435 else if (path == RF_PATH_AB) in _tssi_hw_tx()
3438 rx_path = RF_ABCD; /* don't change path, but still set others */ in _tssi_hw_tx()
3442 rtw8852bx_bb_cfg_tx_path(rtwdev, path); in _tssi_hw_tx()
3500 enum rtw89_rf_path path, const s16 *power, in _tssi_get_cw_report() argument
3509 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0); in _tssi_get_cw_report()
3510 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1); in _tssi_get_cw_report()
3514 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD); in _tssi_get_cw_report()
3516 "[TSSI PA K] 0x%x = 0x%08x path=%d\n", in _tssi_get_cw_report()
3517 _tssi_trigger[path], tmp, path); in _tssi_get_cw_report()
3520 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true, chan); in _tssi_get_cw_report()
3529 "[TSSI PA K] First HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3530 tx_counter_tmp, path); in _tssi_get_cw_report()
3533 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], in _tssi_get_cw_report()
3545 "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3546 k, tx_counter_tmp, path); in _tssi_get_cw_report()
3551 "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n", in _tssi_get_cw_report()
3552 k, path); in _tssi_get_cw_report()
3554 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan); in _tssi_get_cw_report()
3559 rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT); in _tssi_get_cw_report()
3561 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan); in _tssi_get_cw_report()
3567 "[TSSI PA K] Final HWTXcounter=%d path=%d\n", in _tssi_get_cw_report()
3568 tx_counter_tmp, path); in _tssi_get_cw_report()
3575 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_alimentk() argument
3597 "======> %s channel=%d path=%d\n", __func__, channel, in _tssi_alimentk()
3598 path); in _tssi_alimentk()
3600 if (tssi_info->check_backup_aligmk[path][ch_idx]) { in _tssi_alimentk()
3601 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD, in _tssi_alimentk()
3602 tssi_info->alignment_backup_by_ch[path][ch_idx][0]); in _tssi_alimentk()
3603 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD, in _tssi_alimentk()
3604 tssi_info->alignment_backup_by_ch[path][ch_idx][1]); in _tssi_alimentk()
3605 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD, in _tssi_alimentk()
3606 tssi_info->alignment_backup_by_ch[path][ch_idx][2]); in _tssi_alimentk()
3607 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD, in _tssi_alimentk()
3608 tssi_info->alignment_backup_by_ch[path][ch_idx][3]); in _tssi_alimentk()
3612 _tssi_alimentk_dump_result(rtwdev, path); in _tssi_alimentk()
3642 ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt, chan); in _tssi_alimentk()
3652 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1], in _tssi_alimentk()
3659 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2], in _tssi_alimentk()
3664 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3], in _tssi_alimentk()
3669 if (path == RF_PATH_A) { in _tssi_alimentk()
3699 tssi_info->alignment_done[path][band] = true; in _tssi_alimentk()
3700 tssi_info->alignment_value[path][band][0] = in _tssi_alimentk()
3701 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3702 tssi_info->alignment_value[path][band][1] = in _tssi_alimentk()
3703 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3704 tssi_info->alignment_value[path][band][2] = in _tssi_alimentk()
3705 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3706 tssi_info->alignment_value[path][band][3] = in _tssi_alimentk()
3707 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3709 tssi_info->check_backup_aligmk[path][ch_idx] = true; in _tssi_alimentk()
3710 tssi_info->alignment_backup_by_ch[path][ch_idx][0] = in _tssi_alimentk()
3711 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3712 tssi_info->alignment_backup_by_ch[path][ch_idx][1] = in _tssi_alimentk()
3713 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3714 tssi_info->alignment_backup_by_ch[path][ch_idx][2] = in _tssi_alimentk()
3715 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3716 tssi_info->alignment_backup_by_ch[path][ch_idx][3] = in _tssi_alimentk()
3717 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3720 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n", in _tssi_alimentk()
3721 path, band, R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk()
3722 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk()
3724 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n", in _tssi_alimentk()
3725 path, band, R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk()
3726 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk()
3728 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", in _tssi_alimentk()
3729 path, band, R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk()
3730 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk()
3732 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n", in _tssi_alimentk()
3733 path, band, R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk()
3734 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk()
3756 u8 path; in rtw8852b_rck() local
3758 for (path = 0; path < RF_PATH_NUM_8852B; path++) in rtw8852b_rck()
3759 _rck(rtwdev, path); in rtw8852b_rck()
3957 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _bw_setting() argument
3965 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _bw_setting()
3968 "[RFK]Invalid RF_0x18 for Path-%d\n", path); in _bw_setting()
3992 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _bw_setting()
3994 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n", in _bw_setting()
3995 bw, path, reg18_addr, in _bw_setting()
3996 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _bw_setting()
4085 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _ch_setting() argument
4094 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _ch_setting()
4107 if (path == RF_PATH_A && dav) in _ch_setting()
4110 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _ch_setting()
4112 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0); in _ch_setting()
4113 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1); in _ch_setting()
4116 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", in _ch_setting()
4117 central_ch, path, reg18_addr, in _ch_setting()
4118 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _ch_setting()
4130 enum rtw89_rf_path path) in _set_rxbb_bw() argument
4132 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); in _set_rxbb_bw()
4133 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12); in _set_rxbb_bw()
4136 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b); in _set_rxbb_bw()
4138 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13); in _set_rxbb_bw()
4140 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb); in _set_rxbb_bw()
4142 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3); in _set_rxbb_bw()
4144 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path, in _set_rxbb_bw()
4145 rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB)); in _set_rxbb_bw()
4147 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); in _set_rxbb_bw()
4153 u8 kpath, path; in _rxbb_bw() local
4157 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rxbb_bw()
4158 if (!(kpath & BIT(path))) in _rxbb_bw()
4161 _set_rxbb_bw(rtwdev, bw, path); in _rxbb_bw()