Lines Matching full:path
94 u8 path; in _wait_rx_mode() local
98 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
99 if (!(kpath & BIT(path))) in _wait_rx_mode()
103 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
107 path, ret); in _wait_rx_mode()
254 enum rtw89_rf_path path, u8 index) in _dack_reload_by_path() argument
266 if (path == RF_PATH_A) in _dack_reload_by_path()
275 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8); in _dack_reload_by_path()
283 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8); in _dack_reload_by_path()
291 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8); in _dack_reload_by_path()
299 tmp |= dack->msbk_d[path][index][i] << (i * 8); in _dack_reload_by_path()
306 tmp = (dack->biask_d[path][index] << 22) | in _dack_reload_by_path()
307 (dack->dadck_d[path][index] << 14); in _dack_reload_by_path()
312 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _dack_reload() argument
317 _dack_reload_by_path(rtwdev, path, i); in _dack_reload()
319 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _dack_reload()
325 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_addc() argument
331 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_addc()
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
395 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_dadc() argument
397 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
401 _check_addc(rtwdev, path); in _check_dadc()
403 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
552 static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path) in _iqk_read_fft_dbcc0() argument
572 path, i, fft[i]); in _iqk_read_fft_dbcc0()
575 static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path) in _iqk_read_xym_dbcc0() argument
581 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); in _iqk_read_xym_dbcc0()
587 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_read_xym_dbcc0()
589 path, BIT(path), tmp); in _iqk_read_xym_dbcc0()
593 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_read_xym_dbcc0()
598 static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, in _iqk_read_txcfir_dbcc0() argument
609 if (path >= RTW8852A_IQK_SS) { in _iqk_read_txcfir_dbcc0()
610 rtw89_warn(rtwdev, "cfir path %d out of range\n", path); in _iqk_read_txcfir_dbcc0()
619 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_txcfir_dbcc0()
621 base_addr = base_addrs[path][group]; in _iqk_read_txcfir_dbcc0()
630 if (path == 0x0) { in _iqk_read_txcfir_dbcc0()
651 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); in _iqk_read_txcfir_dbcc0()
652 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc); in _iqk_read_txcfir_dbcc0()
654 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); in _iqk_read_txcfir_dbcc0()
655 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_txcfir_dbcc0()
656 BIT(path), tmp); in _iqk_read_txcfir_dbcc0()
659 static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, in _iqk_read_rxcfir_dbcc0() argument
670 if (path >= RTW8852A_IQK_SS) { in _iqk_read_rxcfir_dbcc0()
671 rtw89_warn(rtwdev, "cfir path %d out of range\n", path); in _iqk_read_rxcfir_dbcc0()
680 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_rxcfir_dbcc0()
682 base_addr = base_addrs[path][group]; in _iqk_read_rxcfir_dbcc0()
690 if (path == 0x0) { in _iqk_read_rxcfir_dbcc0()
711 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); in _iqk_read_rxcfir_dbcc0()
712 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd); in _iqk_read_rxcfir_dbcc0()
713 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); in _iqk_read_rxcfir_dbcc0()
714 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_rxcfir_dbcc0()
715 BIT(path), tmp); in _iqk_read_rxcfir_dbcc0()
718 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path) in _iqk_sram() argument
744 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxk_setting() argument
749 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _iqk_rxk_setting()
762 switch (iqk_info->iqk_band[path]) { in _iqk_rxk_setting()
764 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); in _iqk_rxk_setting()
765 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
768 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); in _iqk_rxk_setting()
769 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5); in _iqk_rxk_setting()
770 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
775 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
776 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _iqk_rxk_setting()
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_rxk_setting()
779 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _iqk_rxk_setting()
783 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) in _iqk_check_cal() argument
794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); in _iqk_check_cal()
797 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); in _iqk_check_cal()
803 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype, in _iqk_one_shot() argument
809 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path, chanctx_idx); in _iqk_one_shot()
812 if (path == RF_PATH_A) in _iqk_one_shot()
820 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
825 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
830 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
835 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
836 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
839 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
844 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
850 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
855 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
864 fail = _iqk_check_cal(rtwdev, path, ktype); in _iqk_one_shot()
866 _iqk_read_xym_dbcc0(rtwdev, path); in _iqk_one_shot()
868 _iqk_read_fft_dbcc0(rtwdev, path); in _iqk_one_shot()
870 _iqk_sram(rtwdev, path); in _iqk_one_shot()
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
875 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
876 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
880 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
881 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
893 enum rtw89_phy_idx phy_idx, u8 path, in _rxk_group_sel() argument
908 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
910 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]); in _rxk_group_sel()
911 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]); in _rxk_group_sel()
912 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]); in _rxk_group_sel()
915 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]); in _rxk_group_sel()
916 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]); in _rxk_group_sel()
917 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]); in _rxk_group_sel()
923 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _rxk_group_sel()
927 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); in _rxk_group_sel()
928 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _rxk_group_sel()
929 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _rxk_group_sel()
930 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); in _rxk_group_sel()
933 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK, chanctx_idx); in _rxk_group_sel()
934 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); in _rxk_group_sel()
937 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _rxk_group_sel()
940 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
943 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
944 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
945 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _rxk_group_sel()
950 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
951 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
953 iqk_info->is_wb_rxiqk[path] = true; in _rxk_group_sel()
958 enum rtw89_phy_idx phy_idx, u8 path, in _iqk_nbrxk() argument
972 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
974 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g); in _iqk_nbrxk()
975 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g); in _iqk_nbrxk()
976 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g); in _iqk_nbrxk()
979 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a); in _iqk_nbrxk()
980 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a); in _iqk_nbrxk()
981 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a); in _iqk_nbrxk()
987 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_nbrxk()
991 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); in _iqk_nbrxk()
992 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_nbrxk()
993 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _iqk_nbrxk()
994 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_nbrxk()
998 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK, chanctx_idx); in _iqk_nbrxk()
1000 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_nbrxk()
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1006 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
1007 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1008 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _iqk_nbrxk()
1014 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_nbrxk()
1015 iqk_info->nb_rxcfir[path] = tmp | 0x2; in _iqk_nbrxk()
1017 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
1022 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxclk_setting() argument
1026 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { in _iqk_rxclk_setting()
1028 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), in _iqk_rxclk_setting()
1030 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1032 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1036 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), in _iqk_rxclk_setting()
1038 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1040 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1047 enum rtw89_phy_idx phy_idx, u8 path, in _txk_group_sel() argument
1061 switch (iqk_info->iqk_band[path]) { in _txk_group_sel()
1063 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _txk_group_sel()
1065 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, in _txk_group_sel()
1067 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, in _txk_group_sel()
1069 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, in _txk_group_sel()
1071 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1075 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _txk_group_sel()
1077 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, in _txk_group_sel()
1079 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1085 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _txk_group_sel()
1086 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _txk_group_sel()
1087 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _txk_group_sel()
1088 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1091 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK, chanctx_idx); in _txk_group_sel()
1092 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail); in _txk_group_sel()
1095 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1096 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1098 iqk_info->is_wb_txiqk[path] = true; in _txk_group_sel()
1099 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _txk_group_sel()
1100 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _txk_group_sel()
1101 BIT(path), tmp); in _txk_group_sel()
1106 enum rtw89_phy_idx phy_idx, u8 path, in _iqk_nbtxk() argument
1118 switch (iqk_info->iqk_band[path]) { in _iqk_nbtxk()
1120 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _iqk_nbtxk()
1122 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain); in _iqk_nbtxk()
1123 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr); in _iqk_nbtxk()
1124 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr); in _iqk_nbtxk()
1127 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _iqk_nbtxk()
1129 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain); in _iqk_nbtxk()
1134 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _iqk_nbtxk()
1135 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_nbtxk()
1136 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _iqk_nbtxk()
1137 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group); in _iqk_nbtxk()
1138 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_nbtxk()
1140 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK, chanctx_idx); in _iqk_nbtxk()
1142 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_nbtxk()
1143 iqk_info->nb_txcfir[path] = tmp | 0x2; in _iqk_nbtxk()
1145 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1147 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_nbtxk()
1148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _iqk_nbtxk()
1149 BIT(path), tmp); in _iqk_nbtxk()
1153 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) in _lok_res_table() argument
1157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); in _lok_res_table()
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1159 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _lok_res_table()
1160 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1162 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1163 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); in _lok_res_table()
1164 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1167 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) in _lok_finetune_check() argument
1174 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); in _lok_finetune_check()
1176 path, tmp); in _lok_finetune_check()
1179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i); in _lok_finetune_check()
1180 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q); in _lok_finetune_check()
1188 enum rtw89_phy_idx phy_idx, u8 path, in _iqk_lok() argument
1197 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1199 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0); in _iqk_lok()
1203 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0); in _iqk_lok()
1210 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_lok()
1213 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _iqk_lok()
1214 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_lok()
1215 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1); in _iqk_lok()
1216 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0); in _iqk_lok()
1219 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_lok()
1220 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE, chanctx_idx); in _iqk_lok()
1221 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1223 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_lok()
1224 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE, chanctx_idx); in _iqk_lok()
1225 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1226 fail = _lok_finetune_check(rtwdev, path); in _iqk_lok()
1230 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txk_setting() argument
1234 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _iqk_txk_setting()
1244 switch (iqk_info->iqk_band[path]) { in _iqk_txk_setting()
1246 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00); in _iqk_txk_setting()
1247 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1248 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1249 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1); in _iqk_txk_setting()
1250 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1251 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1252 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1253 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1254 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000); in _iqk_txk_setting()
1255 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1256 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1257 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, in _iqk_txk_setting()
1262 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1263 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1264 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7); in _iqk_txk_setting()
1265 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1266 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1267 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1268 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100); in _iqk_txk_setting()
1269 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1270 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1271 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1); in _iqk_txk_setting()
1272 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0); in _iqk_txk_setting()
1273 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, in _iqk_txk_setting()
1282 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txclk_setting() argument
1284 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _iqk_txclk_setting()
1288 u8 path) in _iqk_info_iqk() argument
1294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path, in _iqk_info_iqk()
1295 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path])); in _iqk_info_iqk()
1296 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path, in _iqk_info_iqk()
1297 iqk_info->lok_cor_fail[0][path]); in _iqk_info_iqk()
1298 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, in _iqk_info_iqk()
1299 iqk_info->lok_fin_fail[0][path]); in _iqk_info_iqk()
1300 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path, in _iqk_info_iqk()
1301 iqk_info->iqk_tx_fail[0][path]); in _iqk_info_iqk()
1302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path, in _iqk_info_iqk()
1303 iqk_info->iqk_rx_fail[0][path]); in _iqk_info_iqk()
1304 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1305 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag); in _iqk_info_iqk()
1306 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1307 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag); in _iqk_info_iqk()
1308 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1309 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag); in _iqk_info_iqk()
1310 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1311 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag); in _iqk_info_iqk()
1313 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); in _iqk_info_iqk()
1314 iqk_info->bp_iqkenable[path] = tmp; in _iqk_info_iqk()
1315 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1316 iqk_info->bp_txkresult[path] = tmp; in _iqk_info_iqk()
1317 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1318 iqk_info->bp_rxkresult[path] = tmp; in _iqk_info_iqk()
1323 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4)); in _iqk_info_iqk()
1326 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4), in _iqk_info_iqk()
1331 void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path, in _iqk_by_path() argument
1339 _iqk_txclk_setting(rtwdev, path); in _iqk_by_path()
1342 _lok_res_table(rtwdev, path, ibias++); in _iqk_by_path()
1343 _iqk_txk_setting(rtwdev, path); in _iqk_by_path()
1344 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path, chanctx_idx); in _iqk_by_path()
1349 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path, in _iqk_by_path()
1352 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path, in _iqk_by_path()
1355 _iqk_rxclk_setting(rtwdev, path); in _iqk_by_path()
1356 _iqk_rxk_setting(rtwdev, path); in _iqk_by_path()
1357 if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G) in _iqk_by_path()
1358 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path, in _iqk_by_path()
1361 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path, in _iqk_by_path()
1364 _iqk_info_iqk(rtwdev, phy_idx, path); in _iqk_by_path()
1368 enum rtw89_phy_idx phy, u8 path, in _iqk_get_ch_info() argument
1379 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1385 idx = iqk_info->iqk_table_idx[path] + 1; in _iqk_get_ch_info()
1389 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_get_ch_info()
1393 iqk_info->iqk_band[path] = chan->band_type; in _iqk_get_ch_info()
1394 iqk_info->iqk_bw[path] = chan->band_width; in _iqk_get_ch_info()
1395 iqk_info->iqk_ch[path] = chan->channel; in _iqk_get_ch_info()
1398 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, in _iqk_get_ch_info()
1399 iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1401 path, iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1403 path, iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1405 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy, in _iqk_get_ch_info()
1407 iqk_info->iqk_band[path] == 0 ? "2G" : in _iqk_get_ch_info()
1408 iqk_info->iqk_band[path] == 1 ? "5G" : "6G", in _iqk_get_ch_info()
1409 iqk_info->iqk_ch[path], in _iqk_get_ch_info()
1410 iqk_info->iqk_bw[path] == 0 ? "20M" : in _iqk_get_ch_info()
1411 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"); in _iqk_get_ch_info()
1418 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16), in _iqk_get_ch_info()
1419 (u8)iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1420 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16), in _iqk_get_ch_info()
1421 (u8)iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1422 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16), in _iqk_get_ch_info()
1423 (u8)iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1429 u8 path, enum rtw89_chanctx_idx chanctx_idx) in _iqk_start_iqk() argument
1431 _iqk_by_path(rtwdev, phy_idx, path, chanctx_idx); in _iqk_start_iqk()
1434 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) in _iqk_restore() argument
1438 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1439 iqk_info->nb_txcfir[path]); in _iqk_restore()
1440 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1441 iqk_info->nb_rxcfir[path]); in _iqk_restore()
1447 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _iqk_restore()
1448 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); in _iqk_restore()
1449 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4); in _iqk_restore()
1450 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_restore()
1451 rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW); in _iqk_restore()
1452 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002); in _iqk_restore()
1453 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1454 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0); in _iqk_restore()
1455 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1456 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _iqk_restore()
1457 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0); in _iqk_restore()
1458 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0); in _iqk_restore()
1459 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1463 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_afebb_restore() argument
1482 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) in _iqk_preset() argument
1485 u8 idx = iqk_info->iqk_table_idx[path]; in _iqk_preset()
1488 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _iqk_preset()
1489 B_COEF_SEL_IQC, path & 0x1); in _iqk_preset()
1490 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_preset()
1491 B_CFIR_LUT_G2, path & 0x1); in _iqk_preset()
1493 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _iqk_preset()
1495 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_preset()
1498 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1504 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD); in _iqk_preset()
1508 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_macbb_setting() argument
1529 static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path, in _iqk_dbcc() argument
1537 if (path == 0x0) in _iqk_dbcc()
1542 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx); in _iqk_dbcc()
1543 _iqk_macbb_setting(rtwdev, phy_idx, path); in _iqk_dbcc()
1544 _iqk_preset(rtwdev, path); in _iqk_dbcc()
1545 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx); in _iqk_dbcc()
1546 _iqk_restore(rtwdev, path); in _iqk_dbcc()
1547 _iqk_afebb_restore(rtwdev, phy_idx, path); in _iqk_dbcc()
1550 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _rck() argument
1556 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); in _rck()
1558 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rck()
1560 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
1561 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rck()
1564 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); in _rck()
1567 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
1570 false, rtwdev, path, 0x1c, BIT(3)); in _rck()
1574 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); in _rck()
1575 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); in _rck()
1578 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4); in _rck()
1580 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1); in _rck()
1581 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0); in _rck()
1583 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rck()
1587 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK), in _rck()
1588 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK), in _rck()
1589 rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK)); in _rck()
1595 u8 ch, path; in _iqk_init() local
1612 for (path = 0; path < RTW8852A_IQK_SS; path++) { in _iqk_init()
1613 iqk_info->lok_cor_fail[ch][path] = false; in _iqk_init()
1614 iqk_info->lok_fin_fail[ch][path] = false; in _iqk_init()
1615 iqk_info->iqk_tx_fail[ch][path] = false; in _iqk_init()
1616 iqk_info->iqk_rx_fail[ch][path] = false; in _iqk_init()
1617 iqk_info->iqk_mcc_ch[ch][path] = 0x0; in _iqk_init()
1618 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1624 enum rtw89_phy_idx phy_idx, u8 path, in _doiqk() argument
1640 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx); in _doiqk()
1642 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1643 _iqk_macbb_setting(rtwdev, phy_idx, path); in _doiqk()
1644 _iqk_preset(rtwdev, path); in _doiqk()
1645 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx); in _doiqk()
1646 _iqk_restore(rtwdev, path); in _doiqk()
1647 _iqk_afebb_restore(rtwdev, phy_idx, path); in _doiqk()
1649 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1675 enum rtw89_rf_path path, bool is_afe, in _set_rx_dck() argument
1678 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx); in _set_rx_dck()
1683 path, is_afe ? "AFE" : "RFC"); in _set_rx_dck()
1685 ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD); in _set_rx_dck()
1688 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _set_rx_dck()
1689 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _set_rx_dck()
1690 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
1692 rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN); in _set_rx_dck()
1693 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13), in _set_rx_dck()
1702 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f); in _set_rx_dck()
1703 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe); in _set_rx_dck()
1707 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1708 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
1714 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1717 rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _set_rx_dck()
1718 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
1726 u8 path, kpath, dck_tune; in _rx_dck() local
1736 for (path = 0; path < 2; path++) { in _rx_dck()
1737 if (!(kpath & BIT(path))) in _rx_dck()
1740 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rx_dck()
1741 dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); in _rx_dck()
1743 if (rtwdev->is_tssi_mode[path]) { in _rx_dck()
1744 addr = 0x5818 + (path << 13); in _rx_dck()
1749 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
1750 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
1751 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rx_dck()
1752 _set_rx_dck(rtwdev, phy, path, is_afe, chanctx_idx); in _rx_dck()
1753 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); in _rx_dck()
1754 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rx_dck()
1756 if (rtwdev->is_tssi_mode[path]) { in _rx_dck()
1757 addr = 0x5818 + (path << 13); in _rx_dck()
1780 enum rtw89_rf_path path, bool is_bybb) in _rf_direct_cntrl() argument
1783 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rf_direct_cntrl()
1785 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rf_direct_cntrl()
1789 enum rtw89_rf_path path, bool off);
1793 u8 path) in _dpk_bkup_kip() argument
1798 reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev, in _dpk_bkup_kip()
1799 reg[i] + (path << 8), in _dpk_bkup_kip()
1802 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_bkup_kip()
1807 u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path) in _dpk_reload_kip() argument
1812 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), in _dpk_reload_kip()
1813 MASKDWORD, reg_bkup[path][i]); in _dpk_reload_kip()
1815 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_reload_kip()
1820 enum rtw89_rf_path path, enum rtw8852a_dpk_id id, in _dpk_one_shot() argument
1823 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx); in _dpk_one_shot()
1828 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); in _dpk_one_shot()
1862 enum rtw89_rf_path path, in _dpk_rx_dck() argument
1865 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1866 _set_rx_dck(rtwdev, phy, path, false, chanctx_idx); in _dpk_rx_dck()
1871 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_information() argument
1875 u8 kidx = dpk->cur_idx[path]; in _dpk_information()
1877 dpk->bp[path][kidx].band = chan->band_type; in _dpk_information()
1878 dpk->bp[path][kidx].ch = chan->channel; in _dpk_information()
1879 dpk->bp[path][kidx].bw = chan->band_width; in _dpk_information()
1883 path, dpk->cur_idx[path], phy, in _dpk_information()
1884 rtwdev->is_tssi_mode[path] ? "on" : "off", in _dpk_information()
1886 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1887 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", in _dpk_information()
1888 dpk->bp[path][kidx].ch, in _dpk_information()
1889 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1890 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); in _dpk_information()
1895 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_setting() argument
1926 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_restore() argument
1946 enum rtw89_rf_path path, bool is_pause) in _dpk_tssi_pause() argument
1948 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), in _dpk_tssi_pause()
1951 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, in _dpk_tssi_pause()
1956 enum rtw89_rf_path path, u8 kidx) in _dpk_kip_setting() argument
1961 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_setting()
1963 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/ in _dpk_kip_setting()
1964 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2), in _dpk_kip_setting()
1966 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_kip_setting()
1970 path, kidx); in _dpk_kip_setting()
1974 enum rtw89_rf_path path) in _dpk_kip_restore() argument
1978 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _dpk_kip_restore()
1982 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1); in _dpk_kip_restore()
1984 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); in _dpk_kip_restore()
1989 enum rtw89_rf_path path, in _dpk_lbk_rxiqk() argument
1994 cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); in _dpk_lbk_rxiqk()
1998 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _dpk_lbk_rxiqk()
1999 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
2000 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2); in _dpk_lbk_rxiqk()
2001 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, in _dpk_lbk_rxiqk()
2002 rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK)); in _dpk_lbk_rxiqk()
2003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _dpk_lbk_rxiqk()
2004 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
2005 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _dpk_lbk_rxiqk()
2009 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f); in _dpk_lbk_rxiqk()
2012 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3); in _dpk_lbk_rxiqk()
2014 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1); in _dpk_lbk_rxiqk()
2016 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0); in _dpk_lbk_rxiqk()
2020 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK, chanctx_idx); in _dpk_lbk_rxiqk()
2022 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
2025 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
2026 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0); in _dpk_lbk_rxiqk()
2027 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/ in _dpk_lbk_rxiqk()
2028 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK); in _dpk_lbk_rxiqk()
2034 enum rtw89_rf_path path) in _dpk_get_thermal() argument
2038 dpk->bp[path][kidx].ther_dpk = in _dpk_get_thermal()
2039 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_get_thermal()
2042 dpk->bp[path][kidx].ther_dpk); in _dpk_get_thermal()
2046 enum rtw89_rf_path path) in _dpk_set_tx_pwr() argument
2050 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori); in _dpk_set_tx_pwr()
2056 enum rtw89_rf_path path, u8 kidx) in _dpk_rf_setting() argument
2060 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { in _dpk_rf_setting()
2061 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b); in _dpk_rf_setting()
2062 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0); in _dpk_rf_setting()
2063 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); in _dpk_rf_setting()
2064 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0); in _dpk_rf_setting()
2066 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e); in _dpk_rf_setting()
2067 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7); in _dpk_rf_setting()
2068 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3); in _dpk_rf_setting()
2069 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3); in _dpk_rf_setting()
2071 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
2072 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); in _dpk_rf_setting()
2073 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
2077 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), in _dpk_rf_setting()
2078 rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK), in _dpk_rf_setting()
2079 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); in _dpk_rf_setting()
2083 enum rtw89_rf_path path, bool is_manual) in _dpk_manual_txcfir() argument
2088 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1); in _dpk_manual_txcfir()
2089 tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD); in _dpk_manual_txcfir()
2090 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), in _dpk_manual_txcfir()
2093 tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB); in _dpk_manual_txcfir()
2094 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), in _dpk_manual_txcfir()
2097 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), in _dpk_manual_txcfir()
2099 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), in _dpk_manual_txcfir()
2102 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1); in _dpk_manual_txcfir()
2108 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); in _dpk_manual_txcfir()
2115 enum rtw89_rf_path path, bool is_bypass) in _dpk_bypass_rxcfir() argument
2118 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2120 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2123 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
2124 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2127 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); in _dpk_bypass_rxcfir()
2128 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); in _dpk_bypass_rxcfir()
2130 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
2131 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2137 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_tpg_sel() argument
2141 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) in _dpk_tpg_sel()
2143 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) in _dpk_tpg_sel()
2149 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : in _dpk_tpg_sel()
2150 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); in _dpk_tpg_sel()
2154 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_table_select() argument
2159 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); in _dpk_table_select()
2166 enum rtw89_rf_path path) in _dpk_sync_check() argument
2181 "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx, in _dpk_sync_check()
2184 dpk->corr_idx[path][0] = corr_idx; in _dpk_sync_check()
2185 dpk->corr_val[path][0] = corr_val; in _dpk_sync_check()
2196 path, dc_i, dc_q); in _dpk_sync_check()
2198 dpk->dc_i[path][0] = dc_i; in _dpk_sync_check()
2199 dpk->dc_q[path][0] = dc_q; in _dpk_sync_check()
2209 enum rtw89_rf_path path, u8 kidx, in _dpk_sync() argument
2212 _dpk_tpg_sel(rtwdev, path, kidx); in _dpk_sync()
2213 _dpk_one_shot(rtwdev, phy, path, SYNC, chanctx_idx); in _dpk_sync()
2214 return _dpk_sync_check(rtwdev, path); /*1= fail*/ in _dpk_sync()
2265 enum rtw89_phy_idx phy, enum rtw89_rf_path path, in _dpk_gainloss() argument
2268 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_gainloss()
2269 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS, chanctx_idx); in _dpk_gainloss()
2277 enum rtw89_rf_path path, s8 gain_offset) in _dpk_set_offset() argument
2281 txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK); in _dpk_set_offset()
2290 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc); in _dpk_set_offset()
2345 enum rtw89_rf_path path, u8 kidx, u8 init_txagc, in _dpk_agc() argument
2368 if (_dpk_sync(rtwdev, phy, path, kidx, chanctx_idx)) { in _dpk_agc()
2383 tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); in _dpk_agc()
2396 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb); in _dpk_agc()
2402 _dpk_bypass_rxcfir(rtwdev, path, true); in _dpk_agc()
2404 _dpk_lbk_rxiqk(rtwdev, phy, path, in _dpk_agc()
2416 _dpk_gainloss(rtwdev, phy, path, kidx, chanctx_idx); in _dpk_agc()
2434 tmp_txagc = _dpk_set_offset(rtwdev, path, 3); in _dpk_agc()
2446 tmp_txagc = _dpk_set_offset(rtwdev, path, -2); in _dpk_agc()
2453 tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx); in _dpk_agc()
2500 enum rtw89_rf_path path, u8 kidx, u8 gain, in _dpk_idl_mpa() argument
2504 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_idl_mpa()
2505 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL, chanctx_idx); in _dpk_idl_mpa()
2509 enum rtw89_rf_path path, u8 kidx, u8 gain, in _dpk_fill_result() argument
2517 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx); in _dpk_fill_result()
2523 dpk->bp[path][kidx].txagc_dpk = txagc; in _dpk_fill_result()
2524 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), in _dpk_fill_result()
2527 dpk->bp[path][kidx].pwsf = pwsf; in _dpk_fill_result()
2528 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_fill_result()
2531 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2532 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD); in _dpk_fill_result()
2534 dpk->bp[path][kidx].gs = gs; in _dpk_fill_result()
2535 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2538 rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD); in _dpk_fill_result()
2544 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx) in _dpk_reload_check() argument
2555 if (cur_band != dpk->bp[path][idx].band || in _dpk_reload_check()
2556 cur_ch != dpk->bp[path][idx].ch) in _dpk_reload_check()
2559 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_reload_check()
2561 dpk->cur_idx[path] = idx; in _dpk_reload_check()
2564 "[DPK] reload S%d[%d] success\n", path, idx); in _dpk_reload_check()
2571 enum rtw89_rf_path path, u8 gain, in _dpk_main() argument
2575 u8 txagc = 0, kidx = dpk->cur_idx[path]; in _dpk_main()
2579 "[DPK] ========= S%d[%d] DPK Start =========\n", path, in _dpk_main()
2582 _rf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2583 txagc = _dpk_set_tx_pwr(rtwdev, gain, path); in _dpk_main()
2584 _dpk_rf_setting(rtwdev, gain, path, kidx); in _dpk_main()
2585 _dpk_rx_dck(rtwdev, phy, path, chanctx_idx); in _dpk_main()
2587 _dpk_kip_setting(rtwdev, path, kidx); in _dpk_main()
2588 _dpk_manual_txcfir(rtwdev, path, true); in _dpk_main()
2589 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx); in _dpk_main()
2592 _dpk_get_thermal(rtwdev, kidx, path); in _dpk_main()
2594 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain, chanctx_idx); in _dpk_main()
2595 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _dpk_main()
2596 _dpk_fill_result(rtwdev, path, kidx, gain, txagc); in _dpk_main()
2597 _dpk_manual_txcfir(rtwdev, path, false); in _dpk_main()
2600 dpk->bp[path][kidx].path_ok = true; in _dpk_main()
2602 dpk->bp[path][kidx].path_ok = false; in _dpk_main()
2604 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2619 u8 path; in _dpk_cal_select() local
2623 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2624 if (!(kpath & BIT(path))) in _dpk_cal_select()
2627 reloaded[path] = _dpk_reload_check(rtwdev, phy, path, in _dpk_cal_select()
2629 if (!reloaded[path] && dpk->bp[path][0].ch != 0) in _dpk_cal_select()
2630 dpk->cur_idx[path] = !dpk->cur_idx[path]; in _dpk_cal_select()
2632 _dpk_onoff(rtwdev, path, false); in _dpk_cal_select()
2635 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) in _dpk_cal_select()
2636 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2646 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2647 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2649 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2650 _dpk_tssi_pause(rtwdev, path, true); in _dpk_cal_select()
2651 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2652 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2653 _dpk_information(rtwdev, phy, path, chanctx_idx); in _dpk_cal_select()
2656 _dpk_bb_afe_setting(rtwdev, phy, path, kpath); in _dpk_cal_select()
2658 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2659 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2662 is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx); in _dpk_cal_select()
2663 _dpk_onoff(rtwdev, path, is_fail); in _dpk_cal_select()
2666 _dpk_bb_afe_restore(rtwdev, phy, path, kpath); in _dpk_cal_select()
2669 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2670 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2673 _dpk_kip_restore(rtwdev, path); in _dpk_cal_select()
2674 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2675 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2676 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2677 _dpk_tssi_pause(rtwdev, path, false); in _dpk_cal_select()
2702 u8 path, kpath; in _dpk_force_bypass() local
2706 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2707 if (kpath & BIT(path)) in _dpk_force_bypass()
2708 _dpk_onoff(rtwdev, path, true); in _dpk_force_bypass()
2728 enum rtw89_rf_path path, bool off) in _dpk_onoff() argument
2731 u8 val, kidx = dpk->cur_idx[path]; in _dpk_onoff()
2733 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; in _dpk_onoff()
2735 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_onoff()
2738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, in _dpk_onoff()
2746 u8 path, kidx; in _dpk_track() local
2753 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_track()
2754 kidx = dpk->cur_idx[path]; in _dpk_track()
2758 path, kidx, dpk->bp[path][kidx].ch); in _dpk_track()
2760 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_track()
2765 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) in _dpk_track()
2766 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; in _dpk_track()
2768 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) in _dpk_track()
2769 delta_ther[path] = delta_ther[path] * 3 / 2; in _dpk_track()
2771 delta_ther[path] = delta_ther[path] * 5 / 2; in _dpk_track()
2773 txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2776 if (rtwdev->is_tssi_mode[path]) { in _dpk_track()
2777 trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); in _dpk_track()
2785 R_TXAGC_BB + (path << 13), in _dpk_track()
2789 R_TXAGC_TP + (path << 13), in _dpk_track()
2798 R_TXAGC_BB + (path << 13), in _dpk_track()
2803 txagc_ofst, delta_ther[path]); in _dpk_track()
2805 if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_track()
2810 ini_diff = txagc_ofst + delta_ther[path]; in _dpk_track()
2812 if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13), in _dpk_track()
2814 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - in _dpk_track()
2816 tssi_info->extra_ofst[path]; in _dpk_track()
2817 pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - in _dpk_track()
2819 tssi_info->extra_ofst[path]; in _dpk_track()
2821 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff + in _dpk_track()
2822 tssi_info->extra_ofst[path]; in _dpk_track()
2823 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff + in _dpk_track()
2824 tssi_info->extra_ofst[path]; in _dpk_track()
2828 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2829 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2838 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2840 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2847 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_rf_setting() argument
2852 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2854 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2869 enum rtw89_rf_path path, in _tssi_ini_txpwr_ctrl_bb() argument
2874 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb()
2884 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2886 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb_he_tb()
2892 enum rtw89_rf_path path) in _tssi_set_dck() argument
2894 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dck()
2900 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_set_tmeter_tbl() argument
2953 if (path == RF_PATH_A) { in _tssi_set_tmeter_tbl()
3057 enum rtw89_rf_path path) in _tssi_set_dac_gain_tbl() argument
3059 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dac_gain_tbl()
3065 enum rtw89_rf_path path) in _tssi_slope_cal_org() argument
3067 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_slope_cal_org()
3073 enum rtw89_rf_path path) in _tssi_set_rf_gap_tbl() argument
3075 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_rf_gap_tbl()
3081 enum rtw89_rf_path path) in _tssi_set_slope() argument
3083 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_slope()
3089 enum rtw89_rf_path path) in _tssi_set_track() argument
3091 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_track()
3098 enum rtw89_rf_path path) in _tssi_set_txagc_offset_mv_avg() argument
3100 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_txagc_offset_mv_avg()
3106 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_pak() argument
3113 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3118 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3123 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3128 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3281 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_de() argument
3293 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", in _tssi_get_ofdm_de()
3294 path, gidx); in _tssi_get_ofdm_de()
3299 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; in _tssi_get_ofdm_de()
3300 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; in _tssi_get_ofdm_de()
3304 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_de()
3305 path, val, de_1st, de_2nd); in _tssi_get_ofdm_de()
3307 val = tssi_info->tssi_mcs[path][gidx]; in _tssi_get_ofdm_de()
3310 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); in _tssi_get_ofdm_de()
3318 enum rtw89_rf_path path, const struct rtw89_chan *chan) in _tssi_get_ofdm_trim_de() argument
3330 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3331 path, tgidx); in _tssi_get_ofdm_trim_de()
3336 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; in _tssi_get_ofdm_trim_de()
3337 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; in _tssi_get_ofdm_trim_de()
3341 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", in _tssi_get_ofdm_trim_de()
3342 path, val, tde_1st, tde_2nd); in _tssi_get_ofdm_trim_de()
3344 val = tssi_info->tssi_trim[path][tgidx]; in _tssi_get_ofdm_trim_de()
3347 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", in _tssi_get_ofdm_trim_de()
3348 path, val); in _tssi_get_ofdm_trim_de()
3382 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3399 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3425 u8 path; in _tssi_track() local
3438 for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) { in _tssi_track()
3439 if (!tssi_info->tssi_tracking_check[path]) { in _tssi_track()
3445 R_TSSI_THER + (path << 13), in _tssi_track()
3448 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0) in _tssi_track()
3451 delta_ther = cur_ther - tssi_info->base_thermal[path]; in _tssi_track()
3455 tssi_info->extra_ofst[path] = gain_offset; in _tssi_track()
3458 "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n", in _tssi_track()
3459 tssi_info->base_thermal[path], gain_offset, path); in _tssi_track()
3469 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13), in _tssi_track()
3472 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), in _tssi_track()
3475 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13), in _tssi_track()
3478 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), in _tssi_track()
3523 u8 path, s16 pwr_dbm, u8 enable, const struct rtw89_chan *chan) in _tssi_hw_tx() argument
3526 rtw8852a_bb_cfg_tx_path(rtwdev, path); in _tssi_hw_tx()
3621 u8 path; in rtw8852a_rck() local
3623 for (path = 0; path < 2; path++) in rtw8852a_rck()
3624 _rck(rtwdev, path); in rtw8852a_rck()