Lines Matching +full:0 +full:xf0ffffff

8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
53 #define R_AX_EFUSE_CTRL_1 0x0038
62 #define R_AX_EFUSE_CTRL 0x0030
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
69 #define R_AX_EFUSE_CTRL_1_V1 0x0038
80 #define R_AX_GPIO_MUXCFG 0x0040
93 #define MAC_AX_BT_MODE_0_3 0
95 #define MAC_AX_RTK_MODE 0
100 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
102 #define R_AX_DBG_CTRL 0x0058
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
110 #define R_AX_GPIO_EXT_CTRL 0x0060
116 #define B_AX_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
119 #define R_AX_SYS_SDIO_CTRL 0x0070
127 #define R_AX_HCI_OPT_CTRL 0x0074
131 #define R_AX_HCI_BG_CTRL 0x0078
137 #define B_AX_R_AX_BG GENMASK(1, 0)
139 #define R_AX_HCI_LDO_CTRL 0x007A
140 #define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
142 #define R_AX_PLATFORM_ENABLE 0x0088
146 #define B_AX_PLATFORM_EN BIT(0)
148 #define R_AX_WLLPS_CTRL 0x0090
152 #define SW_LPS_OPTION 0x0001A0B2
154 #define R_AX_SCOREBOARD  0x00AC
157 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
158 #define B_MAC_AX_BTGS1_NOTIFY BIT(0)
159 #define MAC_AX_NOTIFY_TP_MAJOR 0x81
160 #define MAC_AX_NOTIFY_PWR_MAJOR 0x80
162 #define R_AX_DBG_PORT_SEL 0x00C0
163 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
165 #define R_AX_PMC_DBG_CTRL2 0x00CC
168 #define R_AX_PCIE_MIO_INTF 0x00E4
173 #define MIO_WRITE_BYTE_ALL 0xF
174 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
177 #define R_AX_PCIE_MIO_INTD 0x00E8
178 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
180 #define R_AX_SYS_CFG1 0x00F0
183 #define R_AX_SYS_STATUS1 0x00F4
186 #define MAC_AX_HCI_SEL_SDIO_UART 0
192 #define R_AX_HALT_H2C_CTRL 0x0160
193 #define R_AX_HALT_H2C 0x0168
194 #define B_AX_HALT_H2C_TRIGGER BIT(0)
195 #define R_AX_HALT_C2H_CTRL 0x0164
196 #define R_AX_HALT_C2H 0x016C
198 #define R_AX_WCPU_FW_CTRL 0x01E0
204 #define B_AX_WCPU_FWDL_EN BIT(0)
206 #define R_AX_RPWM 0x01E4
207 #define R_AX_PCIE_HRPWM 0x10C0
212 #define PS_RPWM_STATE 0x7
216 #define PS_CPWM_STATE GENMASK(2, 0)
219 #define R_AX_BOOT_REASON 0x01E6
220 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
222 #define R_AX_LDM 0x01E8
225 #define R_AX_UDM0 0x01F0
226 #define R_AX_UDM1 0x01F4
231 #define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
232 #define R_AX_UDM2 0x01F8
233 #define R_AX_UDM3 0x01FC
235 #define R_AX_SPS_DIG_ON_CTRL0 0x0200
239 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
241 #define R_AX_SPSLDO_ON_CTRL1 0x0204
244 #define R_AX_LDO_AON_CTRL0 0x0218
247 #define R_AX_SPSANA_ON_CTRL1 0x0224
249 #define R_AX_SPS_ANA_ON_CTRL2 0x0228
250 #define RTL8852B_RFE_05_SPS_ANA 0x4A82
252 #define R_AX_WLAN_XTAL_SI_CTRL 0x0270
258 #define XTAL_SI_NORMAL_WRITE 0x00
259 #define XTAL_SI_NORMAL_READ 0x01
262 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
264 #define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
265 #define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
267 #define R_AX_XTAL_ON_CTRL0 0x0280
271 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
273 #define R_AX_XTAL_ON_CTRL3 0x028C
277 #define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
279 #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
281 #define R_AX_GPIO8_15_FUNC_SEL 0x02D4
284 #define R_AX_EECS_EESK_FUNC_SEL 0x02D8
287 #define R_AX_GPIO16_23_FUNC_SEL 0x02D8
289 #define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
291 #define R_AX_LED1_FUNC_SEL 0x02DC
293 #define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
295 #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
300 #define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
304 #define R_AX_WLRF_CTRL 0x02F0
311 #define R_AX_IC_PWR_STATE 0x03F0
317 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
319 #define R_AX_SPS_DIG_OFF_CTRL0 0x0400
321 #define B_AX_C1_L1_MASK GENMASK(1, 0)
323 #define R_AX_AFE_OFF_CTRL1 0x0444
328 #define R_AX_DBG_WOW 0x0504
331 #define R_AX_SEC_CTRL 0x0C00
334 #define R_AX_FILTER_MODEL_ADDR 0x0C04
336 #define R_AX_HAXI_INIT_CFG1 0x1000
340 #define DMA_MOD_PCIE_1B 0x0
341 #define DMA_MOD_PCIE_4B 0x1
342 #define DMA_MOD_USB 0x2
343 #define DMA_MOD_SDIO 0x3
352 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
354 #define R_AX_HAXI_DMA_STOP1 0x1010
368 #define R_AX_HAXI_DMA_BUSY1 0x101C
383 #define R_AX_PCIE_DBG_CTRL 0x11C0
388 #define B_AX_EN_STUCK_DBG BIT(0)
390 #define R_AX_HAXI_DMA_STOP2 0x11C0
392 #define B_AX_STOP_CH10 BIT(0)
394 #define R_AX_HAXI_DMA_BUSY2 0x11C8
396 #define B_AX_CH10_BUSY BIT(0)
398 #define R_AX_HAXI_DMA_BUSY3 0x1208
400 #define B_AX_RXQ_BUSY BIT(0)
402 #define R_AX_LTR_DEC_CTRL 0x1600
415 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
418 #define R_AX_LTR_LATENCY_IDX0 0x1604
419 #define R_AX_LTR_LATENCY_IDX1 0x1608
420 #define R_AX_LTR_LATENCY_IDX2 0x160C
421 #define R_AX_LTR_LATENCY_IDX3 0x1610
423 #define R_AX_HCI_FC_CTRL_V1 0x1700
424 #define R_AX_CH_PAGE_CTRL_V1 0x1704
426 #define R_AX_ACH0_PAGE_CTRL_V1 0x1710
427 #define R_AX_ACH1_PAGE_CTRL_V1 0x1714
428 #define R_AX_ACH2_PAGE_CTRL_V1 0x1718
429 #define R_AX_ACH3_PAGE_CTRL_V1 0x171C
430 #define R_AX_ACH4_PAGE_CTRL_V1 0x1720
431 #define R_AX_ACH5_PAGE_CTRL_V1 0x1724
432 #define R_AX_ACH6_PAGE_CTRL_V1 0x1728
433 #define R_AX_ACH7_PAGE_CTRL_V1 0x172C
434 #define R_AX_CH8_PAGE_CTRL_V1 0x1730
435 #define R_AX_CH9_PAGE_CTRL_V1 0x1734
436 #define R_AX_CH10_PAGE_CTRL_V1 0x1738
437 #define R_AX_CH11_PAGE_CTRL_V1 0x173C
439 #define R_AX_ACH0_PAGE_INFO_V1 0x1750
440 #define R_AX_ACH1_PAGE_INFO_V1 0x1754
441 #define R_AX_ACH2_PAGE_INFO_V1 0x1758
442 #define R_AX_ACH3_PAGE_INFO_V1 0x175C
443 #define R_AX_ACH4_PAGE_INFO_V1 0x1760
444 #define R_AX_ACH5_PAGE_INFO_V1 0x1764
445 #define R_AX_ACH6_PAGE_INFO_V1 0x1768
446 #define R_AX_ACH7_PAGE_INFO_V1 0x176C
447 #define R_AX_CH8_PAGE_INFO_V1 0x1770
448 #define R_AX_CH9_PAGE_INFO_V1 0x1774
449 #define R_AX_CH10_PAGE_INFO_V1 0x1778
450 #define R_AX_CH11_PAGE_INFO_V1 0x177C
451 #define R_AX_CH12_PAGE_INFO_V1 0x1780
453 #define R_AX_PUB_PAGE_INFO3_V1 0x178C
454 #define R_AX_PUB_PAGE_CTRL1_V1 0x1790
455 #define R_AX_PUB_PAGE_CTRL2_V1 0x1794
456 #define R_AX_PUB_PAGE_INFO1_V1 0x1798
457 #define R_AX_PUB_PAGE_INFO2_V1 0x179C
458 #define R_AX_WP_PAGE_CTRL1_V1 0x17A0
459 #define R_AX_WP_PAGE_CTRL2_V1 0x17A4
460 #define R_AX_WP_PAGE_INFO1_V1 0x17A8
462 #define R_AX_H2CREG_DATA0_V1 0x7140
463 #define R_AX_H2CREG_DATA1_V1 0x7144
464 #define R_AX_H2CREG_DATA2_V1 0x7148
465 #define R_AX_H2CREG_DATA3_V1 0x714C
466 #define R_AX_C2HREG_DATA0_V1 0x7150
467 #define R_AX_C2HREG_DATA1_V1 0x7154
468 #define R_AX_C2HREG_DATA2_V1 0x7158
469 #define R_AX_C2HREG_DATA3_V1 0x715C
470 #define R_AX_H2CREG_CTRL_V1 0x7160
471 #define R_AX_C2HREG_CTRL_V1 0x7164
473 #define R_AX_HCI_FUNC_EN_V1 0x7880
475 #define R_AX_PHYREG_SET 0x8040
476 #define PHYREG_SET_ALL_CYCLE 0x8
477 #define PHYREG_SET_XYN_CYCLE 0xE
479 #define R_AX_HD0IMR 0x8110
483 #define B_AX_C2H_INT_EN BIT(0)
484 #define R_AX_HD0ISR 0x8114
485 #define B_AX_C2H_INT BIT(0)
487 #define R_AX_H2CREG_DATA0 0x8140
488 #define R_AX_H2CREG_DATA1 0x8144
489 #define R_AX_H2CREG_DATA2 0x8148
490 #define R_AX_H2CREG_DATA3 0x814C
491 #define R_AX_C2HREG_DATA0 0x8150
492 #define R_AX_C2HREG_DATA1 0x8154
493 #define R_AX_C2HREG_DATA2 0x8158
494 #define R_AX_C2HREG_DATA3 0x815C
495 #define R_AX_H2CREG_CTRL 0x8160
496 #define B_AX_H2CREG_TRIGGER BIT(0)
497 #define R_AX_C2HREG_CTRL 0x8164
498 #define B_AX_C2HREG_TRIGGER BIT(0)
499 #define R_AX_CPWM 0x8170
501 #define R_AX_HCI_FUNC_EN 0x8380
503 #define B_AX_HCI_TXDMA_EN BIT(0)
505 #define R_AX_BOOT_DBG 0x83F0
507 #define R_AX_DMAC_FUNC_EN 0x8400
528 #define R_AX_DMAC_CLK_EN 0x8404
541 #define PCI_LTR_IDLE_TIMER_1US 0
549 #define PCI_LTR_IDLE_TIMER_R_ERR 0xFD
550 #define PCI_LTR_IDLE_TIMER_DEF 0xFE
551 #define PCI_LTR_IDLE_TIMER_IGNORE 0xFF
553 #define PCI_LTR_SPC_10US 0
557 #define PCI_LTR_SPC_R_ERR 0xFD
558 #define PCI_LTR_SPC_DEF 0xFE
559 #define PCI_LTR_SPC_IGNORE 0xFF
561 #define R_AX_LTR_CTRL_0 0x8410
569 #define B_AX_LTR_HW_EN BIT(0)
571 #define R_AX_LTR_CTRL_1 0x8414
573 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
575 #define R_AX_LTR_IDLE_LATENCY 0x8418
577 #define R_AX_LTR_ACTIVE_LATENCY 0x841C
579 #define R_AX_SER_DBG_INFO 0x8424
582 #define R_AX_DLE_EMPTY0 0x8430
602 #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
604 #define R_AX_DLE_EMPTY1 0x8434
615 #define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
617 #define R_AX_DMAC_ERR_IMR 0x8520
628 #define B_AX_WDRLS_ERR_INT_EN BIT(0)
629 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
630 #define DMAC_ERR_IMR_DIS 0
632 #define R_AX_DMAC_ERR_ISR 0x8524
647 #define B_AX_WDRLS_ERR_FLAG BIT(0)
649 #define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
652 #define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
653 #define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
654 #define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
655 #define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
656 #define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
658 #define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
688 #define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
761 #define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
798 #define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
827 #define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
887 #define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
923 #define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
941 #define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
1023 #define R_AX_DISPATCHER_DBG_PORT 0x8860
1026 #define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
1028 #define R_AX_RX_FUNCTION_STOP 0x8920
1029 #define B_AX_HDR_RX_STOP BIT(0)
1031 #define R_AX_HCI_FC_CTRL 0x8A00
1038 #define B_AX_HCI_FC_EN BIT(0)
1040 #define R_AX_CH_PAGE_CTRL 0x8A04
1042 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
1045 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
1047 #define R_AX_ACH0_PAGE_CTRL 0x8A10
1048 #define R_AX_ACH1_PAGE_CTRL 0x8A14
1049 #define R_AX_ACH2_PAGE_CTRL 0x8A18
1050 #define R_AX_ACH3_PAGE_CTRL 0x8A1C
1051 #define R_AX_ACH4_PAGE_CTRL 0x8A20
1052 #define R_AX_ACH5_PAGE_CTRL 0x8A24
1053 #define R_AX_ACH6_PAGE_CTRL 0x8A28
1054 #define R_AX_ACH7_PAGE_CTRL 0x8A2C
1055 #define R_AX_CH8_PAGE_CTRL 0x8A30
1056 #define R_AX_CH9_PAGE_CTRL 0x8A34
1057 #define R_AX_CH10_PAGE_CTRL 0x8A38
1058 #define R_AX_CH11_PAGE_CTRL 0x8A3C
1061 #define B_AX_USE_PG_MASK GENMASK(12, 0)
1062 #define R_AX_ACH0_PAGE_INFO 0x8A50
1063 #define R_AX_ACH1_PAGE_INFO 0x8A54
1064 #define R_AX_ACH2_PAGE_INFO 0x8A58
1065 #define R_AX_ACH3_PAGE_INFO 0x8A5C
1066 #define R_AX_ACH4_PAGE_INFO 0x8A60
1067 #define R_AX_ACH5_PAGE_INFO 0x8A64
1068 #define R_AX_ACH6_PAGE_INFO 0x8A68
1069 #define R_AX_ACH7_PAGE_INFO 0x8A6C
1070 #define R_AX_CH8_PAGE_INFO 0x8A70
1071 #define R_AX_CH9_PAGE_INFO 0x8A74
1072 #define R_AX_CH10_PAGE_INFO 0x8A78
1073 #define R_AX_CH11_PAGE_INFO 0x8A7C
1074 #define R_AX_CH12_PAGE_INFO 0x8A80
1076 #define R_AX_PUB_PAGE_INFO3 0x8A8C
1078 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
1080 #define R_AX_PUB_PAGE_CTRL1 0x8A90
1082 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
1084 #define R_AX_PUB_PAGE_CTRL2 0x8A94
1085 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
1087 #define R_AX_PUB_PAGE_INFO1 0x8A98
1089 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
1091 #define R_AX_PUB_PAGE_INFO2 0x8A9C
1092 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
1094 #define R_AX_WP_PAGE_CTRL1 0x8AA0
1096 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
1098 #define R_AX_WP_PAGE_CTRL2 0x8AA4
1099 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
1101 #define R_AX_WP_PAGE_INFO1 0x8AA8
1104 #define R_AX_WDE_PKTBUF_CFG 0x8C08
1106 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
1109 #define R_AX_WDE_ERRFLAG_MSG 0x8C30
1110 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1112 #define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
1118 #define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
1120 #define R_AX_WDE_ERR_IMR 0x8C38
1141 #define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1296 #define R_AX_WDE_ERR_ISR 0x8C3C
1316 #define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
1319 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1320 #define R_AX_WDE_QTA0_CFG 0x8C40
1321 #define R_AX_WDE_QTA1_CFG 0x8C44
1322 #define R_AX_WDE_QTA2_CFG 0x8C48
1323 #define R_AX_WDE_QTA3_CFG 0x8C4C
1324 #define R_AX_WDE_QTA4_CFG 0x8C50
1326 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1327 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1330 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1331 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1333 #define R_AX_WDE_INI_STATUS 0x8D00
1335 #define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
1337 #define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
1340 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1341 #define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
1342 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1344 #define R_AX_PLE_PKTBUF_CFG 0x9008
1346 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1349 #define R_AX_PLE_DBGERR_LOCKEN 0x9020
1357 #define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
1359 #define R_AX_PLE_DBGERR_STS 0x9024
1367 #define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
1369 #define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
1375 #define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
1377 #define R_AX_PLE_ERRFLAG_MSG 0x9030
1378 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1402 #define R_AX_PLE_ERR_IMR 0x9038
1422 #define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1521 #define R_AX_PLE_ERR_FLAG_ISR 0x903C
1523 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1524 #define R_AX_PLE_QTA0_CFG 0x9040
1525 #define R_AX_PLE_QTA1_CFG 0x9044
1526 #define R_AX_PLE_QTA2_CFG 0x9048
1527 #define R_AX_PLE_QTA3_CFG 0x904C
1528 #define R_AX_PLE_QTA4_CFG 0x9050
1529 #define R_AX_PLE_QTA5_CFG 0x9054
1530 #define R_AX_PLE_QTA6_CFG 0x9058
1532 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1533 #define R_AX_PLE_QTA7_CFG 0x905C
1535 #define B_AX_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
1536 #define R_AX_PLE_QTA8_CFG 0x9060
1537 #define R_AX_PLE_QTA9_CFG 0x9064
1538 #define R_AX_PLE_QTA10_CFG 0x9068
1539 #define R_AX_PLE_QTA11_CFG 0x906C
1541 #define R_AX_PLE_INI_STATUS 0x9100
1543 #define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
1545 #define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
1548 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1549 #define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
1550 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1552 #define R_AX_WDRLS_CFG 0x9408
1554 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1556 #define R_AX_RLSRPT0_CFG0 0x9410
1560 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1562 #define R_AX_RLSRPT0_CFG1 0x9414
1564 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1566 #define R_AX_WDRLS_ERR_IMR 0x9430
1575 #define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
1603 #define R_AX_WDRLS_ERR_ISR 0x9434
1605 #define R_AX_BBRPT_COM_ERR_IMR 0x9608
1607 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1609 #define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
1611 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1613 #define R_AX_BBRPT_COM_ERR_ISR 0x960C
1614 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
1616 #define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
1624 #define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
1626 #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
1634 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1644 #define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
1660 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1670 #define R_AX_BBRPT_DFS_ERR_IMR 0x9638
1671 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1673 #define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
1675 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1677 #define R_AX_BBRPT_DFS_ERR_ISR 0x963C
1678 #define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
1680 #define R_AX_LA_ERRFLAG 0x966C
1682 #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
1684 #define R_AX_WD_BUF_REQ 0x9800
1685 #define R_AX_PL_BUF_REQ 0x9820
1688 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1690 #define R_AX_WD_BUF_STATUS 0x9804
1691 #define R_AX_PL_BUF_STATUS 0x9824
1693 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1694 #define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)
1696 #define R_AX_WD_CPUQ_OP_0 0x9810
1697 #define R_AX_PL_CPUQ_OP_0 0x9830
1701 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1703 #define R_AX_WD_CPUQ_OP_1 0x9814
1704 #define R_AX_PL_CPUQ_OP_1 0x9834
1708 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1710 #define R_AX_WD_CPUQ_OP_2 0x9818
1711 #define R_AX_PL_CPUQ_OP_2 0x9838
1713 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1715 #define R_AX_WD_CPUQ_OP_STATUS 0x981C
1716 #define R_AX_PL_CPUQ_OP_STATUS 0x983C
1718 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1720 #define R_AX_CPUIO_ERR_IMR 0x9840
1724 #define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
1734 #define R_AX_CPUIO_ERR_ISR 0x9844
1736 #define R_AX_SEC_ERR_IMR_ISR 0x991C
1738 #define R_AX_PKTIN_SETTING 0x9A00
1741 #define R_AX_PKTIN_ERR_IMR 0x9A20
1742 #define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
1744 #define R_AX_PKTIN_ERR_ISR 0x9A24
1746 #define R_AX_MPDU_TX_ERR_ISR 0x9BF0
1747 #define R_AX_MPDU_TX_ERR_IMR 0x9BF4
1765 #define R_AX_MPDU_PROC 0x9C00
1767 #define B_AX_APPEND_FCS BIT(0)
1769 #define R_AX_ACTION_FWD0 0x9C04
1770 #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
1772 #define R_AX_ACTION_FWD1 0x9C08
1774 #define R_AX_TF_FWD 0x9C14
1775 #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
1777 #define R_AX_HW_RPT_FWD 0x9C18
1778 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1782 #define R_AX_CUT_AMSDU_CTRL 0x9C40
1783 #define TRXCFG_MPDU_PROC_CUT_CTRL	0x010E05F0
1785 #define R_AX_WOW_CTRL 0x9C50
1788 #define R_AX_MPDU_RX_ERR_ISR 0x9CF0
1789 #define R_AX_MPDU_RX_ERR_IMR 0x9CF4
1792 #define B_AX_GETPKTID_ERR_INT_EN BIT(0)
1795 #define R_AX_SEC_ENG_CTRL 0x9D00
1806 #define B_AX_SEC_TX_ENC BIT(0)
1808 #define R_AX_SEC_MPDU_PROC 0x9D04
1810 #define B_AX_APPEND_MIC BIT(0)
1812 #define R_AX_SEC_CAM_ACCESS 0x9D10
1813 #define R_AX_SEC_CAM_RDATA 0x9D14
1814 #define R_AX_SEC_CAM_WDATA 0x9D18
1816 #define R_AX_SEC_DEBUG 0x9D1C
1819 #define R_AX_SEC_DEBUG1 0x9D1C
1821 #define AX_TX_TO_VAL  0x2
1823 #define R_AX_SEC_TX_DEBUG 0x9D20
1824 #define R_AX_SEC_RX_DEBUG 0x9D24
1825 #define R_AX_SEC_TRX_PKT_CNT 0x9D28
1827 #define R_AX_SEC_DEBUG2 0x9D28
1829 #define B_AX_DBG_READ_MSK 0x3fffffff
1831 #define R_AX_SEC_TRX_BLK_CNT 0x9D2C
1833 #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
1835 #define B_AX_TX_HANG_IMR BIT(0)
1837 #define R_AX_SEC_ERROR_FLAG 0x9D30
1839 #define B_AX_TX_HANG_ERROR_V1 BIT(0)
1841 #define R_AX_SS_CTRL 0x9E10
1845 #define B_AX_SS_EN BIT(0)
1847 #define R_AX_SS2FINFO_PATH 0x9E50
1852 #define SS2F_PATH_WLCPU 0x0A
1853 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1855 #define R_AX_SS_MACID_PAUSE_0 0x9EB0
1856 #define B_AX_SS_MACID31_0_PAUSE_SH 0
1857 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1859 #define R_AX_SS_MACID_PAUSE_1 0x9EB4
1860 #define B_AX_SS_MACID63_32_PAUSE_SH 0
1861 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1863 #define R_AX_SS_MACID_PAUSE_2 0x9EB8
1864 #define B_AX_SS_MACID95_64_PAUSE_SH 0
1865 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1867 #define R_AX_SS_MACID_PAUSE_3 0x9EBC
1868 #define B_AX_SS_MACID127_96_PAUSE_SH 0
1869 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1871 #define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
1874 #define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
1879 #define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
1881 #define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
1893 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
1913 #define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
1919 #define R_AX_DBG_FUN_INTF_CTL 0x9F30
1922 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1923 #define R_AX_DBG_FUN_INTF_DATA 0x9F34
1924 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1926 #define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48
1932 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1934 #define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
1937 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1939 #define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
1951 #define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0)
1974 #define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
1994 #define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
1996 #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
2001 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
2003 #define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
2005 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
2007 #define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
2019 #define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0)
2043 #define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
2063 #define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
2065 #define R_AX_AFE_CTRL1 0x0024
2071 #define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
2073 #define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
2079 #define R_AX_CMAC_REG_START 0xC000
2081 #define R_AX_CMAC_FUNC_EN 0xC000
2082 #define R_AX_CMAC_FUNC_EN_C1 0xE000
2093 #define B_AX_RMAC_EN BIT(0)
2095 #define R_AX_CK_EN 0xC004
2096 #define R_AX_CK_EN_C1 0xE004
2097 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2104 #define B_AX_RMAC_CKEN BIT(0)
2106 #define R_AX_WMAC_RFMOD 0xC010
2107 #define R_AX_WMAC_RFMOD_C1 0xE010
2108 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
2109 #define AX_WMAC_RFMOD_20M 0
2114 #define R_AX_GID_POSITION0 0xC070
2115 #define R_AX_GID_POSITION0_C1 0xE070
2116 #define R_AX_GID_POSITION1 0xC074
2117 #define R_AX_GID_POSITION1_C1 0xE074
2118 #define R_AX_GID_POSITION2 0xC078
2119 #define R_AX_GID_POSITION2_C1 0xE078
2120 #define R_AX_GID_POSITION3 0xC07C
2121 #define R_AX_GID_POSITION3_C1 0xE07C
2122 #define R_AX_GID_POSITION_EN0 0xC080
2123 #define R_AX_GID_POSITION_EN0_C1 0xE080
2124 #define R_AX_GID_POSITION_EN1 0xC084
2125 #define R_AX_GID_POSITION_EN1_C1 0xE084
2127 #define R_AX_TX_SUB_CARRIER_VALUE 0xC088
2128 #define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
2131 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
2133 #define R_AX_PTCL_RRSR1 0xC090
2134 #define R_AX_PTCL_RRSR1_C1 0xE090
2138 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
2140 #define R_AX_CMAC_ERR_IMR 0xC160
2141 #define R_AX_CMAC_ERR_IMR_C1 0xE160
2148 #define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
2149 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2150 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2151 #define CMAC0_ERR_IMR_DIS 0
2152 #define CMAC1_ERR_IMR_DIS 0
2154 #define R_AX_CMAC_ERR_ISR 0xC164
2155 #define R_AX_CMAC_ERR_ISR_C1 0xE164
2162 #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
2164 #define R_AX_PORT0_TSF_SYNC 0xC2A0
2165 #define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
2166 #define R_AX_PORT1_TSF_SYNC 0xC2A4
2167 #define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
2168 #define R_AX_PORT2_TSF_SYNC 0xC2A8
2169 #define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
2170 #define R_AX_PORT3_TSF_SYNC 0xC2AC
2171 #define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
2172 #define R_AX_PORT4_TSF_SYNC 0xC2B0
2173 #define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
2179 #define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
2181 #define R_AX_MACID_SLEEP_0 0xC2C0
2182 #define R_AX_MACID_SLEEP_0_C1 0xE2C0
2183 #define B_AX_MACID31_0_SLEEP_SH 0
2184 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2186 #define R_AX_MACID_SLEEP_1 0xC2C4
2187 #define R_AX_MACID_SLEEP_1_C1 0xE2C4
2188 #define B_AX_MACID63_32_SLEEP_SH 0
2189 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2191 #define R_AX_MACID_SLEEP_2 0xC2C8
2192 #define R_AX_MACID_SLEEP_2_C1 0xE2C8
2193 #define B_AX_MACID95_64_SLEEP_SH 0
2194 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2196 #define R_AX_MACID_SLEEP_3 0xC2CC
2197 #define R_AX_MACID_SLEEP_3_C1 0xE2CC
2198 #define B_AX_MACID127_96_SLEEP_SH 0
2199 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2201 #define SCH_PREBKF_24US 0x18
2202 #define R_AX_PREBKF_CFG_0 0xC338
2203 #define R_AX_PREBKF_CFG_0_C1 0xE338
2204 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2206 #define R_AX_PREBKF_CFG_1 0xC33C
2207 #define R_AX_PREBKF_CFG_1_C1 0xE33C
2211 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
2212 #define SIFS_MACTXEN_T1 0x47
2213 #define SIFS_MACTXEN_T1_V1 0x41
2215 #define R_AX_CCA_CFG_0 0xC340
2216 #define R_AX_CCA_CFG_0_C1 0xE340
2223 #define B_AX_CCA_EN BIT(0)
2225 #define R_AX_CTN_TXEN 0xC348
2226 #define R_AX_CTN_TXEN_C1 0xE348
2242 #define B_AX_CTN_TXEN_BE_0 BIT(0)
2243 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
2245 #define R_AX_MUEDCA_BE_PARAM_0 0xC350
2246 #define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
2249 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2251 #define R_AX_MUEDCA_BK_PARAM_0 0xC354
2252 #define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
2253 #define R_AX_MUEDCA_VI_PARAM_0 0xC358
2254 #define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
2255 #define R_AX_MUEDCA_VO_PARAM_0 0xC35C
2256 #define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
2258 #define R_AX_MUEDCA_EN 0xC370
2259 #define R_AX_MUEDCA_EN_C1 0xE370
2262 #define B_AX_MUEDCA_EN_0 BIT(0)
2264 #define R_AX_CCA_CONTROL 0xC390
2265 #define R_AX_CCA_CONTROL_C1 0xE390
2288 #define B_AX_CTN_CHK_CCA_P20 BIT(0)
2290 #define R_AX_CTN_DRV_TXEN 0xC398
2291 #define R_AX_CTN_DRV_TXEN_C1 0xE398
2294 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
2296 #define R_AX_SCHEDULE_ERR_IMR 0xC3E8
2297 #define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
2300 #define R_AX_SCHEDULE_ERR_ISR 0xC3EC
2301 #define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
2303 #define R_AX_SCH_DBG_SEL 0xC3F4
2304 #define R_AX_SCH_DBG_SEL_C1 0xE3F4
2307 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2309 #define R_AX_SCH_DBG 0xC3F8
2310 #define R_AX_SCH_DBG_C1 0xE3F8
2311 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2313 #define R_AX_SCH_EXT_CTRL 0xC3FC
2314 #define R_AX_SCH_EXT_CTRL_C1 0xE3FC
2317 #define R_AX_PORT_CFG_P0 0xC400
2318 #define R_AX_PORT_CFG_P1 0xC440
2319 #define R_AX_PORT_CFG_P2 0xC480
2320 #define R_AX_PORT_CFG_P3 0xC4C0
2321 #define R_AX_PORT_CFG_P4 0xC500
2337 #define B_AX_RXBCN_RPT_EN BIT(0)
2339 #define R_AX_TBTT_PROHIB_P0 0xC404
2340 #define R_AX_TBTT_PROHIB_P1 0xC444
2341 #define R_AX_TBTT_PROHIB_P2 0xC484
2342 #define R_AX_TBTT_PROHIB_P3 0xC4C4
2343 #define R_AX_TBTT_PROHIB_P4 0xC504
2345 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2347 #define R_AX_BCN_AREA_P0 0xC408
2348 #define R_AX_BCN_AREA_P1 0xC448
2349 #define R_AX_BCN_AREA_P2 0xC488
2350 #define R_AX_BCN_AREA_P3 0xC4C8
2351 #define R_AX_BCN_AREA_P4 0xC508
2353 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2355 #define R_AX_BCNERLYINT_CFG_P0 0xC40C
2356 #define R_AX_BCNERLYINT_CFG_P1 0xC44C
2357 #define R_AX_BCNERLYINT_CFG_P2 0xC48C
2358 #define R_AX_BCNERLYINT_CFG_P3 0xC4CC
2359 #define R_AX_BCNERLYINT_CFG_P4 0xC50C
2360 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2362 #define R_AX_TBTTERLYINT_CFG_P0 0xC40E
2363 #define R_AX_TBTTERLYINT_CFG_P1 0xC44E
2364 #define R_AX_TBTTERLYINT_CFG_P2 0xC48E
2365 #define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
2366 #define R_AX_TBTTERLYINT_CFG_P4 0xC50E
2367 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2369 #define R_AX_TBTT_AGG_P0 0xC412
2370 #define R_AX_TBTT_AGG_P1 0xC452
2371 #define R_AX_TBTT_AGG_P2 0xC492
2372 #define R_AX_TBTT_AGG_P3 0xC4D2
2373 #define R_AX_TBTT_AGG_P4 0xC512
2376 #define R_AX_BCN_SPACE_CFG_P0 0xC414
2377 #define R_AX_BCN_SPACE_CFG_P1 0xC454
2378 #define R_AX_BCN_SPACE_CFG_P2 0xC494
2379 #define R_AX_BCN_SPACE_CFG_P3 0xC4D4
2380 #define R_AX_BCN_SPACE_CFG_P4 0xC514
2382 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2384 #define R_AX_BCN_FORCETX_P0 0xC418
2385 #define R_AX_BCN_FORCETX_P1 0xC458
2386 #define R_AX_BCN_FORCETX_P2 0xC498
2387 #define R_AX_BCN_FORCETX_P3 0xC4D8
2388 #define R_AX_BCN_FORCETX_P4 0xC518
2390 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2391 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2393 #define R_AX_BCN_ERR_CNT_P0 0xC420
2394 #define R_AX_BCN_ERR_CNT_P1 0xC460
2395 #define R_AX_BCN_ERR_CNT_P2 0xC4A0
2396 #define R_AX_BCN_ERR_CNT_P3 0xC4E0
2397 #define R_AX_BCN_ERR_CNT_P4 0xC520
2400 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2401 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2403 #define R_AX_BCN_ERR_FLAG_P0 0xC424
2404 #define R_AX_BCN_ERR_FLAG_P1 0xC464
2405 #define R_AX_BCN_ERR_FLAG_P2 0xC4A4
2406 #define R_AX_BCN_ERR_FLAG_P3 0xC4E4
2407 #define R_AX_BCN_ERR_FLAG_P4 0xC524
2414 #define B_AX_BCN_ERR_FLAG_LOCK BIT(0)
2416 #define R_AX_DTIM_CTRL_P0 0xC426
2417 #define R_AX_DTIM_CTRL_P1 0xC466
2418 #define R_AX_DTIM_CTRL_P2 0xC4A6
2419 #define R_AX_DTIM_CTRL_P3 0xC4E6
2420 #define R_AX_DTIM_CTRL_P4 0xC526
2422 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2424 #define R_AX_TBTT_SHIFT_P0 0xC428
2425 #define R_AX_TBTT_SHIFT_P1 0xC468
2426 #define R_AX_TBTT_SHIFT_P2 0xC4A8
2427 #define R_AX_TBTT_SHIFT_P3 0xC4E8
2428 #define R_AX_TBTT_SHIFT_P4 0xC528
2429 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2431 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2433 #define R_AX_BCN_CNT_TMR_P0 0xC434
2434 #define R_AX_BCN_CNT_TMR_P1 0xC474
2435 #define R_AX_BCN_CNT_TMR_P2 0xC4B4
2436 #define R_AX_BCN_CNT_TMR_P3 0xC4F4
2437 #define R_AX_BCN_CNT_TMR_P4 0xC534
2438 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2440 #define R_AX_TSFTR_LOW_P0 0xC438
2441 #define R_AX_TSFTR_LOW_P1 0xC478
2442 #define R_AX_TSFTR_LOW_P2 0xC4B8
2443 #define R_AX_TSFTR_LOW_P3 0xC4F8
2444 #define R_AX_TSFTR_LOW_P4 0xC538
2445 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2447 #define R_AX_TSFTR_HIGH_P0 0xC43C
2448 #define R_AX_TSFTR_HIGH_P1 0xC47C
2449 #define R_AX_TSFTR_HIGH_P2 0xC4BC
2450 #define R_AX_TSFTR_HIGH_P3 0xC4FC
2451 #define R_AX_TSFTR_HIGH_P4 0xC53C
2452 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2454 #define R_AX_BCN_DROP_ALL0 0xC560
2455 #define R_AX_BCN_DROP_ALL0_C1 0xE560
2460 #define B_AX_BCN_DROP_ALL_P0 BIT(0)
2462 #define R_AX_MBSSID_CTRL 0xC568
2463 #define R_AX_MBSSID_CTRL_C1 0xE568
2482 #define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
2483 #define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
2484 #define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
2485 #define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
2487 #define R_AX_PTCL_COMMON_SETTING_0 0xC600
2488 #define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
2497 #define B_AX_CMAC_TX_MODE_0 BIT(0)
2499 #define R_AX_AMPDU_AGG_LIMIT 0xC610
2503 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2505 #define R_AX_AGG_LEN_HT_0 0xC614
2506 #define R_AX_AGG_LEN_HT_0_C1 0xE614
2509 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2511 #define R_AX_AGG_LEN_VHT_0 0xC618
2512 #define R_AX_AGG_LEN_VHT_0_C1 0xE618
2513 #define B_AX_AMPDU_MAX_LEN_VHT_MASK GENMASK(19, 0)
2516 #define R_AX_SIFS_SETTING 0xC624
2517 #define R_AX_SIFS_SETTING_C1 0xE624
2523 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2526 #define R_AX_TXRATE_CHK 0xC628
2527 #define R_AX_TXRATE_CHK_C1 0xE628
2532 #define B_AX_CHECK_CCK_EN BIT(0)
2534 #define R_AX_TXCNT 0xC62C
2535 #define R_AX_TXCNT_C1 0xE62C
2540 #define R_AX_MBSSID_DROP_0 0xC63C
2541 #define R_AX_MBSSID_DROP_0_C1 0xE63C
2545 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2547 #define R_AX_PTCLRPT_FULL_HDL 0xC660
2548 #define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
2557 #define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
2559 #define R_AX_BT_PLT 0xC67C
2560 #define R_AX_BT_PLT_C1 0xE67C
2571 #define B_AX_TX_PLT_GNT_WL BIT(0)
2573 #define R_AX_PTCL_BSS_COLOR_0 0xC6A0
2574 #define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
2578 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2580 #define R_AX_PTCL_BSS_COLOR_1 0xC6A4
2581 #define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
2582 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2584 #define R_AX_PTCL_IMR0 0xC6C0
2585 #define R_AX_PTCL_IMR0_C1 0xE6C0
2603 #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
2604 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2630 #define R_AX_PTCL_ISR0 0xC6C4
2631 #define R_AX_PTCL_ISR0_C1 0xE6C4
2633 #define S_AX_PTCL_TO_2MS 0x3F
2634 #define R_AX_PTCL_FSM_MON 0xC6E8
2635 #define R_AX_PTCL_FSM_MON_C1 0xE6E8
2637 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2639 #define R_AX_PTCL_TX_CTN_SEL 0xC6EC
2640 #define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
2643 #define R_AX_PTCL_DBG_INFO 0xC6F0
2644 #define R_AX_PTCL_DBG_INFO_C1 0xE6F0
2651 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2652 #define R_AX_PTCL_DBG 0xC6F4
2653 #define R_AX_PTCL_DBG_C1 0xE6F4
2655 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2660 #define R_AX_DLE_CTRL 0xC800
2661 #define R_AX_DLE_CTRL_C1 0xE800
2671 #define R_AX_RX_ERR_FLAG 0xC800
2672 #define R_AX_RX_ERR_FLAG_C1 0xE800
2704 #define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
2706 #define R_AX_RXDMA_CTRL_0 0xC804
2707 #define R_AX_RXDMA_CTRL_0_C1 0xE804
2723 #define B_AX_RU0_PTR_FULL_MODE BIT(0)
2728 #define R_AX_RX_CTRL0 0xC808
2729 #define R_AX_RX_CTRL0_C1 0xE808
2743 #define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
2745 #define R_AX_RX_CTRL1 0xC80C
2746 #define R_AX_RX_CTRL1_C1 0xE80C
2757 #define B_AX_DBG_SEL_MASK GENMASK(1, 0)
2759 #define R_AX_RX_CTRL2 0xC810
2760 #define R_AX_RX_CTRL2_C1 0xE810
2769 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2771 #define R_AX_RXDMA_PKT_INFO_0 0xC814
2772 #define R_AX_RXDMA_PKT_INFO_1 0xC818
2773 #define R_AX_RXDMA_PKT_INFO_2 0xC81C
2775 #define R_AX_RX_ERR_FLAG_IMR 0xC804
2776 #define R_AX_RX_ERR_FLAG_IMR_C1 0xE804
2807 #define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0)
2859 #define R_AX_TX_ERR_FLAG_IMR 0xC870
2860 #define R_AX_TX_ERR_FLAG_IMR_C1 0xE870
2900 #define R_AX_TCR0 0xCA00
2901 #define R_AX_TCR0_C1 0xEA00
2905 #define TCR_UDF_THSD 0x6
2916 #define B_AX_TCR_DISGCLK BIT(0)
2918 #define R_AX_TCR1 0xCA04
2919 #define R_AX_TCR1_C1 0xEA04
2929 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2931 #define R_AX_MD_TSFT_STMP_CTL 0xCA08
2932 #define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
2936 #define B_AX_UPD_TIMIE BIT(0)
2938 #define R_AX_PPWRBIT_SETTING 0xCA0C
2939 #define R_AX_PPWRBIT_SETTING_C1 0xEA0C
2941 #define R_AX_TXD_FIFO_CTRL 0xCA1C
2942 #define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
2946 #define TXDFIFO_HIGH_MCS_THRE 0x7
2948 #define TXDFIFO_LOW_MCS_THRE  0x7
2950 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2952 #define R_AX_MACTX_DBG_SEL_CNT 0xCA20
2953 #define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
2960 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2962 #define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
2963 #define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
2964 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2966 #define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
2967 #define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
2968 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2970 #define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
2971 #define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
2972 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2974 #define R_AX_RSP_CHK_SIG 0xCC00
2975 #define R_AX_RSP_CHK_SIG_C1 0xEC00
2985 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2987 #define R_AX_TRXPTCL_RESP_0 0xCC04
2988 #define R_AX_TRXPTCL_RESP_0_C1 0xEC04
3003 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
3004 #define WMAC_SPEC_SIFS_OFDM_52A 0x15
3005 #define WMAC_SPEC_SIFS_OFDM_52B 0x11
3006 #define WMAC_SPEC_SIFS_OFDM_52C 0x11
3007 #define WMAC_SPEC_SIFS_CCK	 0xA
3009 #define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
3010 #define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
3021 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
3023 #define R_AX_MAC_LOOPBACK 0xCC20
3024 #define R_AX_MAC_LOOPBACK_C1 0xEC20
3025 #define B_AX_MACLBK_EN BIT(0)
3027 #define R_AX_WMAC_NAV_CTL 0xCC80
3028 #define R_AX_WMAC_NAV_CTL_C1 0xEC80
3034 #define NAV_12MS 0xBC
3035 #define NAV_25MS 0xC4
3036 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
3038 #define R_AX_RXTRIG_TEST_USER_2 0xCCB0
3039 #define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
3045 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
3047 #define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
3048 #define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
3059 #define B_AX_TMAC_MACTX BIT(0)
3078 #define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
3079 #define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
3088 #define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
3090 #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
3091 #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
3092 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
3094 #define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
3095 #define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
3096 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3098 #define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
3099 #define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
3100 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3102 #define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
3103 #define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
3117 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
3127 #define R_AX_DBGSEL_TRXPTCL 0xCCF4
3128 #define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
3129 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3131 #define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8
3132 #define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8
3139 #define B_AX_PHY_TXON_TIMEOUT_EN BIT(0)
3153 #define R_AX_PHYINFO_ERR_IMR 0xCCFC
3154 #define R_AX_PHYINFO_ERR_IMR_C1 0xECFC
3167 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
3175 #define B_AX_PHYINFO_IMR_SET (B_AX_PHY_TXON_TIMEOUT_INT_EN | 0x7)
3177 #define R_AX_PHYINFO_ERR_ISR 0xCCFC
3178 #define R_AX_PHYINFO_ERR_ISR_C1 0xECFC
3180 #define R_AX_BFMER_CTRL_0 0xCD78
3181 #define R_AX_BFMER_CTRL_0_C1 0xED78
3186 #define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
3188 #define R_AX_BFMEE_RESP_OPTION 0xCD80
3189 #define R_AX_BFMEE_RESP_OPTION_C1 0xED80
3192 #define BFRP_RX_STANDBY_TIMER_KEEP 0x0
3193 #define BFRP_RX_STANDBY_TIMER_RELEASE 0x1
3196 #define BFRP_RX_STANDBY_TIMER		0x0
3197 #define NDP_RX_STANDBY_TIMER		0xFF
3200 #define B_AX_BFMEE_HT_NDPA_EN BIT(0)
3202 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
3203 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
3204 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
3205 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
3224 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
3226 #define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
3227 #define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
3228 #define CSI_RRSC_BMAP 0x29292911
3230 #define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
3231 #define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
3234 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
3235 #define CSI_INIT_RATE_HE		0x3
3236 #define CSI_INIT_RATE_VHT		0x3
3237 #define CSI_INIT_RATE_HT		0x3
3239 #define R_AX_RCR 0xCE00
3240 #define R_AX_RCR_C1 0xEE00
3243 #define B_AX_CH_EN_MASK GENMASK(3, 0)
3245 #define R_AX_DLK_PROTECT_CTL 0xCE02
3246 #define R_AX_DLK_PROTECT_CTL_C1 0xEE02
3250 #define B_AX_RX_DLK_INT_EN BIT(0)
3252 #define R_AX_PLCP_HDR_FLTR 0xCE04
3253 #define R_AX_PLCP_HDR_FLTR_C1 0xEE04
3261 #define B_AX_CCK_CRC_CHK BIT(0)
3263 #define R_AX_RX_FLTR_OPT 0xCE20
3264 #define R_AX_RX_FLTR_OPT_C1 0xEE20
3269 #define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f
3283 #define B_AX_SNIFFER_MODE BIT(0)
3291 #define R_AX_CTRL_FLTR 0xCE24
3292 #define R_AX_CTRL_FLTR_C1 0xEE24
3293 #define R_AX_MGNT_FLTR 0xCE28
3294 #define R_AX_MGNT_FLTR_C1 0xEE28
3295 #define R_AX_DATA_FLTR 0xCE2C
3296 #define R_AX_DATA_FLTR_C1 0xEE2C
3297 #define RX_FLTR_FRAME_DROP	0x00000000
3298 #define RX_FLTR_FRAME_TO_HOST	0x55555555
3299 #define RX_FLTR_FRAME_TO_WLCPU	0xAAAAAAAA
3301 #define R_AX_ADDR_CAM_CTRL 0xCE34
3302 #define R_AX_ADDR_CAM_CTRL_C1 0xEE34
3308 #define B_AX_ADDR_CAM_EN BIT(0)
3310 #define R_AX_RESPBA_CAM_CTRL 0xCE3C
3311 #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
3313 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
3316 #define R_AX_PPDU_STAT 0xCE40
3317 #define R_AX_PPDU_STAT_C1 0xEE40
3324 #define B_AX_PPDU_STAT_RPT_EN BIT(0)
3326 #define R_AX_RX_SR_CTRL 0xCE4A
3327 #define R_AX_RX_SR_CTRL_C1 0xEE4A
3328 #define B_AX_SR_EN BIT(0)
3330 #define R_AX_BSSID_SRC_CTRL 0xCE4B
3331 #define R_AX_BSSID_SRC_CTRL_C1 0xEE4B
3335 #define B_AX_PLCP_SRC_EN BIT(0)
3337 #define R_AX_CSIRPT_OPTION 0xCE64
3338 #define R_AX_CSIRPT_OPTION_C1 0xEE64
3342 #define R_AX_RX_STATE_MONITOR 0xCEF0
3343 #define R_AX_RX_STATE_MONITOR_C1 0xEEF0
3344 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3348 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3350 #define R_AX_RMAC_ERR_ISR 0xCEF4
3351 #define R_AX_RMAC_ERR_ISR_C1 0xEEF4
3368 #define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
3382 #define R_AX_RX_ERR_IMR 0xCEF8
3383 #define R_AX_RX_ERR_IMR_C1 0xEEF8
3393 #define B_AX_RX_ERR_CCA_TO_MSK BIT(0)
3415 #define R_AX_RMAC_PLCP_MON 0xCEF8
3416 #define R_AX_RMAC_PLCP_MON_C1 0xEEF8
3417 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3419 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
3421 #define R_AX_RX_DEBUG_SELECT 0xCEFC
3422 #define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
3423 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3425 #define R_AX_PWR_RATE_CTRL 0xD200
3426 #define R_AX_PWR_RATE_CTRL_C1 0xF200
3429 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3431 #define R_AX_PWR_RATE_OFST_CTRL 0xD204
3432 #define R_AX_PWR_COEXT_CTRL 0xD220
3436 #define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
3437 #define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
3438 #define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
3440 #define R_AX_PWR_UL_CTRL0 0xD240
3441 #define R_AX_PWR_UL_CTRL2 0xD248
3442 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3443 #define B_AX_PWR_UL_CTRL2_MASK 0x07700007
3445 #define R_AX_PWR_NORM_FORCE1 0xD260
3446 #define R_AX_PWR_NORM_FORCE1_C1 0xF260
3464 #define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
3466 #define R_AX_PWR_UL_TB_CTRL 0xD288
3468 #define R_AX_PWR_UL_TB_1T 0xD28C
3469 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3470 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3472 #define R_AX_PWR_UL_TB_2T 0xD290
3473 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3474 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3476 #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
3477 #define R_AX_PWR_BY_RATE_TABLE6 0xD2D8
3478 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
3482 #define R_AX_PWR_LMT_TABLE0 0xD2EC
3483 #define R_AX_PWR_LMT_TABLE9 0xD310
3484 #define R_AX_PWR_LMT_TABLE19 0xD338
3488 #define R_AX_PWR_RU_LMT_TABLE0 0xD33C
3489 #define R_AX_PWR_RU_LMT_TABLE5 0xD350
3490 #define R_AX_PWR_RU_LMT_TABLE11 0xD368
3494 #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
3495 #define R_AX_PWR_MACID_LMT_TABLE127 0xD568
3497 #define R_AX_PATH_COM0 0xD800
3498 #define AX_PATH_COM0_DFVAL 0x00000000
3499 #define AX_PATH_COM0_PATHA 0x08889880
3500 #define AX_PATH_COM0_PATHB 0x11111900
3501 #define AX_PATH_COM0_PATHAB 0x19999980
3502 #define R_AX_PATH_COM1 0xD804
3504 #define AX_PATH_COM1_DFVAL 0x00000000
3505 #define AX_PATH_COM1_PATHA 0x13111111
3506 #define AX_PATH_COM1_PATHB 0x23222222
3507 #define AX_PATH_COM1_PATHAB 0x33333333
3508 #define R_AX_PATH_COM2 0xD808
3510 #define AX_PATH_COM2_DFVAL 0x00000000
3511 #define AX_PATH_COM2_PATHA 0x01209313
3512 #define AX_PATH_COM2_PATHB 0x01209323
3513 #define AX_PATH_COM2_PATHAB 0x01209333
3514 #define R_AX_PATH_COM3 0xD80C
3515 #define AX_PATH_COM3_DFVAL 0x49249249
3516 #define R_AX_PATH_COM4 0xD810
3517 #define AX_PATH_COM4_DFVAL 0x1C9C9C49
3518 #define R_AX_PATH_COM5 0xD814
3519 #define AX_PATH_COM5_DFVAL 0x39393939
3520 #define R_AX_PATH_COM6 0xD818
3521 #define AX_PATH_COM6_DFVAL 0x39393939
3522 #define R_AX_PATH_COM7 0xD81C
3523 #define AX_PATH_COM7_DFVAL 0x39393939
3524 #define AX_PATH_COM7_PATHA 0x39393939
3525 #define AX_PATH_COM7_PATHB 0x39383939
3526 #define AX_PATH_COM7_PATHAB 0x39393939
3527 #define R_AX_PATH_COM8 0xD820
3528 #define AX_PATH_COM8_DFVAL 0x00000000
3529 #define AX_PATH_COM8_PATHA 0x00003939
3530 #define AX_PATH_COM8_PATHB 0x00003938
3531 #define AX_PATH_COM8_PATHAB 0x00003939
3532 #define R_AX_PATH_COM9 0xD824
3533 #define AX_PATH_COM9_DFVAL 0x000007C0
3534 #define R_AX_PATH_COM10 0xD828
3535 #define AX_PATH_COM10_DFVAL 0xE0000000
3536 #define R_AX_PATH_COM11 0xD82C
3537 #define AX_PATH_COM11_DFVAL 0x00000000
3538 #define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848
3540 #define R_AX_TSSI_CTRL_HEAD 0xD908
3541 #define R_AX_BANDEDGE_CFG 0xD94C
3543 #define R_AX_TSSI_CTRL_TAIL 0xD95C
3545 #define R_AX_TXPWR_IMR 0xD9E0
3546 #define R_AX_TXPWR_IMR_C1 0xF9E0
3547 #define R_AX_TXPWR_ISR 0xD9E4
3548 #define R_AX_TXPWR_ISR_C1 0xF9E4
3550 #define R_AX_BTC_CFG 0xDA00
3565 #define B_AX_WL_SRC BIT(0)
3567 #define R_AX_RTK_MODE_CFG_V1 0xDA04
3568 #define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
3575 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3577 #define R_AX_WL_PRI_MSK 0xDA10
3580 #define R_AX_BT_CNT_CFG 0xDA10
3581 #define R_AX_BT_CNT_CFG_C1 0xFA10
3583 #define B_AX_BT_CNT_EN BIT(0)
3585 #define R_BTC_BT_CNT_HIGH 0xDA14
3586 #define R_BTC_BT_CNT_LOW 0xDA18
3588 #define R_AX_BTC_FUNC_EN 0xDA20
3589 #define R_AX_BTC_FUNC_EN_C1 0xFA20
3591 #define B_AX_PTA_EDCCA_EN BIT(0)
3593 #define R_BTC_COEX_WL_REQ 0xDA24
3594 #define R_BTC_COEX_WL_REQ_BE 0xE324
3602 #define R_BTC_BREAK_TABLE 0xDA2C
3603 #define BTC_BREAK_PARAM 0xf0ffffff
3605 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
3609 #define R_AX_BT_COEX_CFG_2 0xDA34
3610 #define R_AX_BT_COEX_CFG_2_C1 0xFA34
3613 #define B_AX_TIMER_MASK GENMASK(7, 0)
3616 #define R_AX_CSR_MODE 0xDA40
3617 #define R_AX_CSR_MODE_C1 0xFA40
3620 #define MAC_AX_CSR_DELAY 0
3628 #define B_AX_ENHANCED_BT BIT(0)
3630 #define R_AX_BT_BREAK_TABLE 0xDA44
3632 #define R_AX_BT_STAST_HIGH 0xDA44
3634 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3635 #define R_AX_BT_STAST_LOW 0xDA48
3636 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3639 #define R_AX_GNT_SW_CTRL 0xDA48
3640 #define R_AX_GNT_SW_CTRL_C1 0xFA48
3662 #define B_AX_GNT_WL_BB_SWCTRL BIT(0)
3664 #define R_AX_GNT_VAL 0x0054
3670 #define R_AX_GNT_VAL_V1 0xDA4C
3676 #define R_AX_TDMA_MODE 0xDA4C
3677 #define R_AX_TDMA_MODE_C1 0xFA4C
3686 #define B_AX_RTK_BT_ENABLE BIT(0)
3688 #define R_AX_BT_COEX_CFG_5 0xDA6C
3689 #define R_AX_BT_COEX_CFG_5_C1 0xFA6C
3691 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3694 #define R_AX_LTE_CTRL 0xDAF0
3695 #define R_AX_LTE_WDATA 0xDAF4
3696 #define R_AX_LTE_RDATA 0xDAF8
3698 #define R_AX_MACID_ANT_TABLE 0xDC00
3699 #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC
3701 #define CMAC1_START_ADDR_AX 0xE000
3702 #define CMAC1_END_ADDR_AX 0xFFFF
3703 #define R_AX_CMAC_REG_END 0xFFFF
3705 #define R_AX_LTE_SW_CFG_1 0x0038
3706 #define R_AX_LTE_SW_CFG_1_C1 0x2038
3731 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3733 #define R_AX_LTE_SW_CFG_2 0x003C
3734 #define R_AX_LTE_SW_CFG_2_C1 0x203C
3743 #define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
3745 #define R_BE_SYS_ISO_CTRL 0x0000
3760 #define B_BE_ISO_WD2PP BIT(0)
3762 #define R_BE_SYS_PW_CTRL 0x0004
3789 #define R_BE_SYS_CLK_CTRL 0x0008
3797 #define B_BE_CNTD16V_EN BIT(0)
3799 #define R_BE_SYS_WL_EFUSE_CTRL 0x000A
3809 #define R_BE_SYS_PAGE_CLK_GATED 0x000C
3836 #define B_BE_DIS_CLK_REG0_GATE BIT(0)
3838 #define R_BE_ANAPAR_POW_MAC 0x0016
3842 #define B_BE_POW_POWER_CUT_POW_LDO BIT(0)
3844 #define R_BE_SYS_ADIE_PAD_PWR_CTRL 0x0018
3848 #define R_BE_RSV_CTRL 0x001C
3859 #define B_BE_WLOCK_ALL BIT(0)
3861 #define R_BE_AFE_LDO_CTRL 0x0020
3887 #define B_BE_R_SYM_WLBBOFF_PC_EN BIT(0)
3889 #define R_BE_AFE_CTRL1 0x0024
3915 #define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0)
3922 #define R_BE_EFUSE_CTRL 0x0030
3926 #define B_BE_EF_ADDR_MASK GENMASK(15, 0)
3928 #define R_BE_EFUSE_CTRL_1_V1 0x0034
3929 #define B_BE_EF_DATA_MASK GENMASK(31, 0)
3931 #define R_BE_GPIO_EXT_CTRL 0x0060
3937 #define B_BE_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
3940 #define R_BE_WL_BT_PWR_CTRL 0x0068
3961 #define B_BE_WL_HWPDN_EN BIT(0)
3963 #define R_BE_SYS_SDIO_CTRL 0x0070
3987 #define B_BE_USB_WAIT_TIME BIT(0)
3989 #define R_BE_HCI_OPT_CTRL 0x0074
4016 #define B_BE_PCI_VAUX_EN BIT(0)
4018 #define R_BE_SYS_ISO_CTRL_EXTEND 0x0080
4040 #define B_BE_R_SYM_ISO_SPDIO2PP BIT(0)
4042 #define R_BE_FEN_RST_ENABLE 0x0084
4062 #define B_BE_FEN_BBPLAT_RSTB BIT(0)
4064 #define R_BE_PLATFORM_ENABLE 0x0088
4075 #define B_BE_PLATFORM_EN BIT(0)
4077 #define R_BE_WLLPS_CTRL 0x0090
4097 #define B_BE_WL_LPS_EN BIT(0)
4099 #define R_BE_WLRESUME_CTRL 0x0094
4122 #define R_BE_EFUSE_CTRL_2_V1 0x00A4
4136 #define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
4138 #define R_BE_PMC_DBG_CTRL2 0x00CC
4149 #define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)
4151 #define R_BE_MEM_PWR_CTRL 0x00D0
4175 #define R_BE_PCIE_MIO_INTF 0x00E4
4182 #define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
4184 #define R_BE_PCIE_MIO_INTD 0x00E8
4185 #define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4187 #define R_BE_HALT_H2C_CTRL 0x0160
4188 #define B_BE_HALT_H2C_TRIGGER BIT(0)
4190 #define R_BE_HALT_C2H_CTRL 0x0164
4191 #define B_BE_HALT_C2H_TRIGGER BIT(0)
4193 #define R_BE_HALT_H2C 0x0168
4194 #define B_BE_HALT_H2C_MASK GENMASK(31, 0)
4196 #define R_BE_HALT_C2H 0x016C
4198 #define B_BE_ERROR_CODE_MASK GENMASK(15, 0)
4200 #define R_BE_SYS_CFG5 0x0170
4209 #define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184
4211 #define R_BE_FWS1IMR 0x0198
4231 #define B_BE_FS_GPIO16_INT_EN BIT(0)
4233 #define R_BE_HIMR0 0x01A0
4258 #define B_BE_GPIO0_INT_EN BIT(0)
4260 #define R_BE_HISR0 0x01A4
4285 #define B_BE_GPIO0_INT BIT(0)
4287 #define R_BE_WCPU_FW_CTRL 0x01E0
4301 #define B_BE_DLFW_PATH_RDY BIT(0)
4303 #define R_BE_BOOT_REASON 0x01E6
4304 #define B_BE_BOOT_REASON_MASK GENMASK(2, 0)
4306 #define R_BE_LDM 0x01E8
4308 #define B_BE_LDM_MASK GENMASK(30, 0)
4310 #define R_BE_UDM0 0x01F0
4320 #define B_BE_UDM0_DBG_MODE_CTRL BIT(0)
4322 #define R_BE_UDM1 0x01F4
4327 #define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
4329 #define R_BE_UDM2 0x01F8
4330 #define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4332 #define R_BE_AFE_ON_CTRL0 0x0240
4344 #define B_BE_LDO_VSEL_MASK GENMASK(1, 0)
4346 #define R_BE_AFE_ON_CTRL1 0x0244
4361 #define B_BE_REG_LPF_R3_4_MASK GENMASK(1, 0)
4363 #define R_BE_AFE_ON_CTRL3 0x024C
4383 #define B_BE_REG_CK640M_EN BIT(0)
4385 #define R_BE_GPIO8_15_FUNC_SEL 0x02D4
4388 #define R_BE_WLAN_XTAL_SI_CTRL 0x0270
4394 #define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
4396 #define R_BE_IC_PWR_STATE 0x03F0
4398 #define MAC_AX_SYS_ACT 0x220
4403 #define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
4405 #define R_BE_WLCPU_PORT_PC 0x03FC
4407 #define R_BE_DBG_WOW 0x0504
4409 #define R_BE_DCPU_PLATFORM_ENABLE 0x0888
4416 #define B_BE_DCPU_PLATFORM_EN BIT(0)
4418 #define R_BE_PL_AXIDMA_IDCT_MSK 0x0910
4425 #define B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK BIT(0)
4437 #define R_BE_PL_AXIDMA_IDCT 0x0914
4444 #define B_BE_PL_AXIDMA_TXBD_TX_STUCK BIT(0)
4446 #define R_BE_FILTER_MODEL_ADDR 0x0C04
4448 #define R_BE_WLAN_WDT 0x3050
4452 #define B_BE_WLAN_WDT_ENABLE BIT(0)
4454 #define R_BE_AXIDMA_WDT 0x305C
4458 #define B_BE_AXIDMA_WDT_ENABLE BIT(0)
4460 #define R_BE_AON_WDT 0x3068
4464 #define B_BE_AON_WDT_ENABLE BIT(0)
4466 #define R_BE_AON_WDT_TMR 0x306C
4467 #define R_BE_MDIO_WDT_TMR 0x3090
4468 #define R_BE_LA_MODE_WDT_TMR 0x309C
4469 #define R_BE_WDT_AR_TMR 0x3144
4470 #define R_BE_WDT_AW_TMR 0x3150
4471 #define R_BE_WLAN_WDT_TMR 0x3054
4472 #define R_BE_WDT_W_TMR 0x315C
4473 #define R_BE_AXIDMA_WDT_TMR 0x3060
4474 #define R_BE_WDT_B_TMR 0x3164
4475 #define R_BE_WDT_R_TMR 0x316C
4476 #define R_BE_LOCAL_WDT_TMR 0x3084
4478 #define R_BE_LOCAL_WDT 0x3080
4482 #define B_BE_LOCAL_WDT_ENABLE BIT(0)
4484 #define R_BE_MDIO_WDT 0x308C
4488 #define B_BE_MDIO_WDT_ENABLE BIT(0)
4490 #define R_BE_LA_MODE_WDT 0x3098
4494 #define B_BE_LA_MODE_WDT_ENABLE BIT(0)
4496 #define R_BE_WDT_AR 0x3140
4500 #define B_BE_WDT_AR_ENABLE BIT(0)
4502 #define R_BE_WDT_AW 0x314C
4506 #define B_BE_WDT_AW_ENABLE BIT(0)
4508 #define R_BE_WDT_W 0x3158
4512 #define B_BE_WDT_W_ENABLE BIT(0)
4514 #define R_BE_WDT_B 0x3160
4518 #define B_BE_WDT_B_ENABLE BIT(0)
4520 #define R_BE_WDT_R 0x3168
4524 #define B_BE_WDT_R_ENABLE BIT(0)
4526 #define R_BE_LTR_DECISION_CTRL_V1 0x3610
4541 #define B_BE_LTR_SPACE_IDX_MASK GENMASK(1, 0)
4543 #define R_BE_LTR_LATENCY_IDX0_V1 0x3614
4544 #define R_BE_LTR_LATENCY_IDX1_V1 0x3618
4545 #define R_BE_LTR_LATENCY_IDX2_V1 0x361C
4546 #define R_BE_LTR_LATENCY_IDX3_V1 0x3620
4548 #define R_BE_H2CREG_DATA0 0x7140
4549 #define R_BE_H2CREG_DATA1 0x7144
4550 #define R_BE_H2CREG_DATA2 0x7148
4551 #define R_BE_H2CREG_DATA3 0x714C
4552 #define R_BE_C2HREG_DATA0 0x7150
4553 #define R_BE_C2HREG_DATA1 0x7154
4554 #define R_BE_C2HREG_DATA2 0x7158
4555 #define R_BE_C2HREG_DATA3 0x715C
4556 #define R_BE_H2CREG_CTRL 0x7160
4557 #define B_BE_H2CREG_TRIGGER BIT(0)
4558 #define R_BE_C2HREG_CTRL 0x7164
4559 #define B_BE_C2HREG_TRIGGER BIT(0)
4561 #define R_BE_HCI_FUNC_EN 0x7880
4565 #define B_BE_HCI_TXDMA_EN BIT(0)
4567 #define R_BE_DBG_WOW_READY 0x815E
4568 #define B_BE_DBG_WOW_READY GENMASK(7, 0)
4570 #define R_BE_DMAC_FUNC_EN 0x8400
4595 #define R_BE_DMAC_CLK_EN 0x8404
4617 #define R_BE_LTR_CTRL_0 0x8410
4622 #define B_BE_LTR_HW_EN BIT(0)
4624 #define R_BE_LTR_CFG_0 0x8414
4632 #define B_BE_EN_LTR_HAXIDMA_RX_IDLE_CHK BIT(0)
4634 #define R_BE_LTR_CFG_1 0x8418
4636 #define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0)
4638 #define R_BE_DMAC_TABLE_CTRL 0x8420
4643 #define B_BE_DMAC_CTRL_INFO_OFFSET_MASK GENMASK(10, 0)
4645 #define R_BE_SER_DBG_INFO 0x8424
4649 #define B_BE_SER_L0_COUNTER_MASK GENMASK(8, 0)
4651 #define R_BE_DMAC_SYS_CR32B 0x842C
4653 #define B_BE_DMAC_BB_PHY0_MASK GENMASK(15, 0)
4685 #define B_BE_DMAC_BB_CTRL_8 BIT(0)
4687 #define R_BE_DLE_EMPTY0 0x8430
4715 #define B_BE_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
4717 #define R_BE_DLE_EMPTY1 0x8434
4729 #define B_BE_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
4731 #define R_BE_SER_L1_DBG_CNT_0 0x8440
4735 #define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0)
4737 #define R_BE_SER_L1_DBG_CNT_1 0x8444
4741 #define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0)
4743 #define R_BE_SER_L1_DBG_CNT_2 0x8448
4747 #define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0)
4749 #define R_BE_SER_L1_DBG_CNT_3 0x844C
4753 #define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0)
4755 #define R_BE_SER_L1_DBG_CNT_4 0x8450
4759 #define R_BE_SER_L1_DBG_CNT_5 0x8454
4760 #define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)
4762 #define R_BE_SER_L1_DBG_CNT_6 0x8458
4763 #define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)
4765 #define R_BE_SER_L1_DBG_CNT_7 0x845C
4766 #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)
4768 #define R_BE_DMAC_ERR_IMR 0x8520
4789 #define B_BE_WDRLS_ERR_INT_EN BIT(0)
4791 #define R_BE_DMAC_ERR_ISR 0x8524
4810 #define B_BE_WDRLS_ERR_FLAG BIT(0)
4812 #define R_BE_DISP_ERROR_ISR0 0x8804
4842 #define B_BE_WDE_FLOW_CTRL_ERR BIT(0)
4844 #define R_BE_DISP_ERROR_ISR1 0x8808
4873 #define B_BE_HT_EP_CH_DIFF_ERR BIT(0)
4875 #define R_BE_DISP_ERROR_ISR2 0x880C
4902 #define B_BE_CT_EP_CH_DIFF_ERR BIT(0)
4904 #define R_BE_DISP_OTHER_IMR 0x8870
4934 #define B_BE_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
4972 #define R_BE_DISP_HOST_IMR 0x8874
5001 #define B_BE_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5049 #define R_BE_DISP_CPU_IMR 0x8878
5078 #define B_BE_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5123 #define R_BE_RX_STOP 0x8914
5127 #define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0)
5129 #define R_BE_DISP_FWD_WLAN_0 0x8938
5145 #define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0)
5147 #define R_BE_WDE_PKTBUF_CFG 0x8C08
5150 #define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)
5152 #define R_BE_WDE_BUFMGN_CTL 0x8C10
5155 #define B_BE_WDE_BUFMGN_FRZTMR_MODE BIT(0)
5157 #define R_BE_WDE_ERR_IMR 0x8C38
5185 #define B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5243 #define R_BE_WDE_QTA0_CFG 0x8C40
5245 #define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5247 #define R_BE_WDE_QTA1_CFG 0x8C44
5249 #define B_BE_WDE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5251 #define R_BE_WDE_QTA2_CFG 0x8C48
5253 #define B_BE_WDE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5255 #define R_BE_WDE_QTA3_CFG 0x8C4C
5257 #define B_BE_WDE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5259 #define R_BE_WDE_QTA4_CFG 0x8C50
5261 #define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5263 #define R_BE_WDE_ERR1_IMR 0x8CC0
5268 #define R_BE_PLE_PKTBUF_CFG 0x9008
5271 #define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)
5273 #define R_BE_PLE_BUFMGN_CTL 0x9010
5276 #define B_BE_PLE_BUFMGN_FRZTMR_MODE BIT(0)
5278 #define R_BE_PLE_ERR_IMR 0x9038
5306 #define B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5364 #define R_BE_PLE_QTA0_CFG 0x9040
5366 #define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5368 #define R_BE_PLE_QTA1_CFG 0x9044
5370 #define B_BE_PLE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5372 #define R_BE_PLE_QTA2_CFG 0x9048
5374 #define B_BE_PLE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5376 #define R_BE_PLE_QTA3_CFG 0x904C
5378 #define B_BE_PLE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5380 #define R_BE_PLE_QTA4_CFG 0x9050
5382 #define B_BE_PLE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5384 #define R_BE_PLE_QTA5_CFG 0x9054
5386 #define B_BE_PLE_Q5_MIN_SIZE_MASK GENMASK(11, 0)
5388 #define R_BE_PLE_QTA6_CFG 0x9058
5390 #define B_BE_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
5392 #define R_BE_PLE_QTA7_CFG 0x905C
5394 #define B_BE_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
5396 #define R_BE_PLE_QTA8_CFG 0x9060
5398 #define B_BE_PLE_Q8_MIN_SIZE_MASK GENMASK(11, 0)
5400 #define R_BE_PLE_QTA9_CFG 0x9064
5402 #define B_BE_PLE_Q9_MIN_SIZE_MASK GENMASK(11, 0)
5404 #define R_BE_PLE_QTA10_CFG 0x9068
5406 #define B_BE_PLE_Q10_MIN_SIZE_MASK GENMASK(11, 0)
5408 #define R_BE_PLE_QTA11_CFG 0x906C
5410 #define B_BE_PLE_Q11_MIN_SIZE_MASK GENMASK(11, 0)
5412 #define R_BE_PLE_QTA12_CFG 0x9070
5414 #define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)
5416 #define R_BE_PLE_ERRFLAG1_IMR 0x90C0
5427 #define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110
5430 #define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0)
5432 #define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114
5433 #define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
5435 #define R_BE_WDRLS_CFG 0x9408
5439 #define B_BE_WDRLS_MODE_MASK GENMASK(1, 0)
5441 #define R_BE_WDRLS_ERR_IMR 0x9430
5454 #define B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
5473 #define R_BE_RLSRPT0_CFG1 0x9444
5480 #define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
5482 #define R_BE_BBRPT_COM_ERR_IMR 0x9608
5484 #define B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN BIT(0)
5489 #define R_BE_BBRPT_CHINFO_ERR_IMR 0x9628
5491 #define B_BE_ERR_GEN_FRZTO_INT_EN BIT(0)
5497 #define R_BE_BBRPT_DFS_ERR_IMR 0x9638
5498 #define B_BE_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
5502 #define R_BE_LA_ERRFLAG_IMR 0x9668
5503 #define B_BE_LA_IMR_DATA_LOSS BIT(0)
5507 #define R_BE_LA_ERRFLAG_ISR 0x966C
5508 #define B_BE_LA_ISR_DATA_LOSS BIT(0)
5510 #define R_BE_CH_INFO_DBGFLAG_IMR 0x9688
5521 #define B_BE_CHIF_RPT_WTOUT_ISR_EN BIT(0)
5530 #define B_BE_CH_INFO_DBGFLAG_IMR_SET 0
5532 #define R_BE_WD_BUF_REQ 0x9800
5535 #define B_BE_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
5537 #define R_BE_WD_BUF_STATUS 0x9804
5539 #define B_BE_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5541 #define R_BE_WD_CPUQ_OP_0 0x9810
5544 #define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5546 #define R_BE_WD_CPUQ_OP_1 0x9814
5549 #define B_BE_WD_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5551 #define R_BE_WD_CPUQ_OP_2 0x9818
5554 #define B_BE_WD_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5556 #define R_BE_WD_CPUQ_OP_3 0x981C
5558 #define B_BE_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5560 #define R_BE_WD_CPUQ_OP_STATUS 0x9820
5563 #define B_BE_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5565 #define R_BE_PL_BUF_REQ 0x9840
5568 #define B_BE_PL_BUF_REQ_LEN_MASK GENMASK(15, 0)
5570 #define R_BE_PL_BUF_STATUS 0x9844
5572 #define B_BE_PL_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5574 #define R_BE_PL_CPUQ_OP_0 0x9850
5577 #define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5579 #define R_BE_PL_CPUQ_OP_1 0x9854
5582 #define B_BE_PL_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5584 #define R_BE_PL_CPUQ_OP_2 0x9858
5587 #define B_BE_PL_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5589 #define R_BE_PL_CPUQ_OP_3 0x985C
5591 #define B_BE_PL_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5593 #define R_BE_PL_CPUQ_OP_STATUS 0x9860
5596 #define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5598 #define R_BE_CPUIO_ERR_IMR 0x9888
5602 #define B_BE_WDEBUF_OP_ERR_INT_EN BIT(0)
5612 #define R_BE_PKTIN_ERR_IMR 0x9A20
5614 #define B_BE_GET_NULL_PKTID_ERR_INT_EN BIT(0)
5620 #define R_BE_HDR_SHCUT_SETTING 0x9B00
5625 #define B_BE_TX_HW_SEQ_EN BIT(0)
5627 #define R_BE_MPDU_TX_ERR_IMR 0x9BF4
5628 #define B_BE_TX_TIMEOUT_ERR_EN BIT(0)
5630 #define B_BE_MPDU_TX_ERR_IMR_SET 0
5632 #define R_BE_MPDU_PROC 0x9C00
5642 #define B_BE_APPEND_FCS BIT(0)
5644 #define R_BE_FWD_ERR 0x9C10
5645 #define R_BE_FWD_ACTN0 0x9C14
5646 #define R_BE_FWD_ACTN1 0x9C18
5647 #define R_BE_FWD_ACTN2 0x9C1C
5648 #define R_BE_FWD_TF0 0x9C20
5649 #define R_BE_FWD_TF1 0x9C24
5651 #define R_BE_HW_PPDU_STATUS 0x9C30
5657 #define B_BE_FWD_PPDU_STAT_MASK GENMASK(7, 0)
5659 #define R_BE_CUT_AMSDU_CTRL 0x9C94
5665 #define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0)
5667 #define R_BE_WOW_CTRL 0x9CB8
5671 #define B_BE_WOW_FORCE_WAKEUP BIT(0)
5673 #define R_BE_RX_HDRTRNS 0x9CC0
5679 #define B_BE_RX_HDR_CNV_EN BIT(0)
5680 #define TRXCFG_MPDU_PROC_RX_HDR_CONV	0x00000000
5682 #define R_BE_MPDU_RX_ERR_IMR 0x9CF4
5686 #define B_BE_MPDU_RX_ERR_IMR_SET 0
5688 #define R_BE_SEC_ENG_CTRL 0x9D00
5711 #define B_BE_SEC_TX_ENC BIT(0)
5713 #define R_BE_SEC_MPDU_PROC 0x9D04
5722 #define B_BE_APPEND_MIC BIT(0)
5724 #define R_BE_SEC_CAM_ACCESS 0x9D10
5729 #define B_BE_SEC_CAM_OFFSET_MASK GENMASK(10, 0)
5731 #define R_BE_SEC_CAM_RDATA 0x9D14
5732 #define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)
5734 #define R_BE_SEC_DEBUG2 0x9D28
5735 #define B_BE_DBG_READ_MASK GENMASK(31, 0)
5737 #define R_BE_SEC_ERROR_IMR 0x9D2C
5742 #define B_BE_TX_HANG_IMR BIT(0)
5754 #define R_BE_SEC_ERROR_FLAG 0x9D30
5760 #define B_BE_TX_HANG_ERROR BIT(0)
5762 #define R_BE_TXPKTCTL_MPDUINFO_CFG 0x9F10
5765 #define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0)
5768 #define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48
5772 #define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5774 #define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
5776 #define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5778 #define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
5788 #define B_BE_B0_IMR_ERR_USRCTL_REINIT BIT(0)
5808 #define R_BE_TXPKTCTL_B1_PRELD_CFG0 0x9F88
5812 #define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5814 #define R_BE_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
5816 #define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5818 #define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
5828 #define B_BE_B1_IMR_ERR_USRCTL_REINIT BIT(0)
5848 #define R_BE_MLO_INIT_CTL 0xA114
5854 #define R_BE_MLO_ERR_IDCT_IMR 0xA128
5866 #define R_BE_MLO_ERR_IDCT_ISR 0xA12C
5872 #define R_BE_PLRLS_ERR_IMR 0xA218
5873 #define B_BE_PLRLS_CTL_FRZTO_IMR BIT(0)
5877 #define R_BE_PLRLS_ERR_ISR 0xA21C
5881 #define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0)
5883 #define R_BE_SS_CTRL 0xA310
5905 #define B_BE_SS_EN BIT(0)
5907 #define R_BE_INTERRUPT_MASK_REG 0xA3F0
5910 #define B_BE_SEARCH_TIMEOUT_IMR BIT(0)
5918 #define R_BE_INTERRUPT_STS_REG 0xA3F4
5921 #define B_BE_SEARCH_TIMEOUT_ISR BIT(0)
5923 #define R_BE_HAXI_INIT_CFG1 0xB000
5934 #define S_BE_DMA_MOD_PCIE_NO_DATA_CPU 0x0
5935 #define S_BE_DMA_MOD_PCIE_DATA_CPU 0x1
5936 #define S_BE_DMA_MOD_USB 0x4
5937 #define S_BE_DMA_MOD_SDIO 0x6
5943 #define B_BE_MAX_TXDMA_MASK GENMASK(1, 0)
5945 #define R_BE_HAXI_DMA_STOP1 0xB010
5961 #define B_BE_STOP_CH0 BIT(0)
5963 #define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C
5964 #define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)
5966 #define R_BE_HAXI_IDCT_MSK 0xB0B8
5974 #define B_BE_TXMDA_STUCK_IDCT_MSK BIT(0)
5990 #define R_BE_HAXI_IDCT 0xB0BC
5998 #define B_BE_TXMDA_STUCK_IDCT BIT(0)
6000 #define R_BE_HCI_FC_CTRL 0xB700
6010 #define B_BE_HCI_FC_EN BIT(0)
6012 #define R_BE_CH_PAGE_CTRL 0xB704
6014 #define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)
6016 #define R_BE_CH0_PAGE_CTRL 0xB718
6019 #define B_BE_CH0_MIN_PG_MASK GENMASK(12, 0)
6021 #define R_BE_CH0_PAGE_INFO 0xB750
6023 #define B_BE_CH0_USE_PG_MASK GENMASK(12, 0)
6025 #define R_BE_PUB_PAGE_INFO3 0xB78C
6027 #define B_BE_G0_AVAL_PG_MASK GENMASK(12, 0)
6029 #define R_BE_PUB_PAGE_CTRL1 0xB790
6031 #define B_BE_PUBPG_G0_MASK GENMASK(12, 0)
6033 #define R_BE_PUB_PAGE_CTRL2 0xB794
6034 #define B_BE_PUBPG_ALL_MASK GENMASK(12, 0)
6036 #define R_BE_PUB_PAGE_INFO1 0xB79C
6038 #define B_BE_G0_USE_PG_MASK GENMASK(12, 0)
6040 #define R_BE_PUB_PAGE_INFO2 0xB7A0
6041 #define B_BE_PUB_AVAL_PG_MASK GENMASK(12, 0)
6043 #define R_BE_WP_PAGE_CTRL1 0xB7A4
6045 #define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
6047 #define R_BE_WP_PAGE_CTRL2 0xB7A8
6048 #define B_BE_WP_THRD_MASK GENMASK(12, 0)
6050 #define R_BE_WP_PAGE_INFO1 0xB7AC
6053 #define R_BE_LTPC_T0_PATH0 0xBA28
6054 #define R_BE_LTPC_T0_PATH1 0xBB28
6056 #define R_BE_CMAC_SHARE_FUNC_EN 0x0E000
6064 #define B_BE_BTCOEX_EN BIT(0)
6066 #define R_BE_CMAC_SHARE_ACQCHK_CFG_0 0x0E010
6071 #define B_BE_R_MACID_ACQ_CHK_EN BIT(0)
6073 #define R_BE_BT_BREAK_TABLE 0x0E344
6075 #define R_BE_GNT_SW_CTRL 0x0E348
6101 #define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0)
6103 #define R_BE_PWR_MACID_PATH_BASE 0x0E500
6104 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00
6106 #define R_BE_CMAC_FUNC_EN 0x10000
6107 #define R_BE_CMAC_FUNC_EN_C1 0x14000
6131 #define B_BE_RMAC_EN BIT(0)
6138 #define R_BE_CK_EN 0x10004
6139 #define R_BE_CK_EN_C1 0x14004
6151 #define B_BE_RMAC_CKEN BIT(0)
6157 #define R_BE_WMAC_RFMOD 0x10010
6158 #define R_BE_WMAC_RFMOD_C1 0x14010
6160 #define B_BE_WMAC_RFMOD_MASK GENMASK(2, 0)
6161 #define BE_WMAC_RFMOD_20M 0
6167 #define R_BE_TX_SUB_BAND_VALUE 0x10088
6168 #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088
6172 #define S_BE_TXSB_160M_0 0
6175 #define S_BE_TXSB_80M_0 0
6179 #define S_BE_TXSB_40M_0 0
6182 #define B_BE_TXSB_20M_MASK GENMASK(3, 0)
6187 #define R_BE_PTCL_RRSR0 0x1008C
6188 #define R_BE_PTCL_RRSR0_C1 0x1408C
6192 #define B_BE_RRSR_OFDM_MASK GENMASK(7, 0)
6194 #define R_BE_PTCL_RRSR1 0x10090
6195 #define R_BE_PTCL_RRSR1_C1 0x14090
6199 #define B_BE_RRSR_CCK_MASK GENMASK(3, 0)
6201 #define R_BE_CMAC_ERR_IMR 0x10160
6202 #define R_BE_CMAC_ERR_IMR_C1 0x14160
6213 #define B_BE_SCHEDULE_TOP_ERR_IND_EN BIT(0)
6215 #define R_BE_CMAC_ERR_ISR 0x10164
6216 #define R_BE_CMAC_ERR_ISR_C1 0x14164
6227 #define B_BE_SCHEDULE_TOP_ERR_IND BIT(0)
6229 #define R_BE_SER_L0_DBG_CNT 0x10170
6230 #define R_BE_SER_L0_DBG_CNT_C1 0x14170
6234 #define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0)
6236 #define R_BE_SER_L0_DBG_CNT1 0x10174
6237 #define R_BE_SER_L0_DBG_CNT1_C1 0x14174
6240 #define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0)
6242 #define R_BE_SER_L0_DBG_CNT2 0x10178
6243 #define R_BE_SER_L0_DBG_CNT2_C1 0x14178
6245 #define R_BE_SER_L0_DBG_CNT3 0x1017C
6246 #define R_BE_SER_L0_DBG_CNT3_C1 0x1417C
6278 #define B_BE_SER_L0_SUBMODULE_BIT0_CNT BIT(0)
6280 #define R_BE_PORT_0_TSF_SYNC 0x102A0
6281 #define R_BE_PORT_0_TSF_SYNC_C1 0x142A0
6286 #define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)
6288 #define R_BE_EDCA_BCNQ_PARAM 0x10324
6289 #define R_BE_EDCA_BCNQ_PARAM_C1 0x14324
6292 #define BCN_IFS_25US 0x19
6294 #define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0)
6296 #define R_BE_PREBKF_CFG_0 0x10338
6297 #define R_BE_PREBKF_CFG_0_C1 0x14338
6301 #define B_BE_PREBKF_TIME_MASK GENMASK(4, 0)
6303 #define R_BE_PREBKF_CFG_1 0x1033C
6304 #define R_BE_PREBKF_CFG_1_C1 0x1433C
6308 #define B_BE_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
6310 #define R_BE_CCA_CFG_0 0x10340
6311 #define R_BE_CCA_CFG_0_C1 0x14340
6332 #define B_BE_CCA_EN BIT(0)
6334 #define R_BE_CTN_CFG_0 0x1034C
6335 #define R_BE_CTN_CFG_0_C1 0x1434C
6342 #define B_BE_NAV_BLK_HGQ BIT(0)
6344 #define R_BE_MUEDCA_BE_PARAM_0 0x10350
6345 #define R_BE_MUEDCA_BK_PARAM_0 0x10354
6346 #define R_BE_MUEDCA_VI_PARAM_0 0x10358
6347 #define R_BE_MUEDCA_VO_PARAM_0 0x1035C
6349 #define R_BE_MUEDCA_EN 0x10370
6350 #define R_BE_MUEDCA_EN_C1 0x14370
6356 #define B_BE_MUEDCA_EN_MASK GENMASK(1, 0)
6357 #define B_BE_MUEDCA_EN_0 BIT(0)
6359 #define R_BE_CTN_DRV_TXEN 0x10398
6360 #define R_BE_CTN_DRV_TXEN_C1 0x14398
6378 #define B_BE_CTN_TXEN_BE_0 BIT(0)
6379 #define B_BE_CTN_TXEN_ALL_MASK GENMASK(17, 0)
6381 #define R_BE_TB_CHK_CCA_NAV 0x103AC
6382 #define R_BE_TB_CHK_CCA_NAV_C1 0x143AC
6398 #define B_BE_TB_CHK_CCA_P20 BIT(0)
6400 #define R_BE_HE_SIFS_CHK_CCA_NAV 0x103B4
6401 #define R_BE_HE_SIFS_CHK_CCA_NAV_C1 0x143B4
6417 #define B_BE_HE_SIFS_CHK_CCA_P20 BIT(0)
6419 #define R_BE_HE_CTN_CHK_CCA_NAV 0x103C4
6420 #define R_BE_HE_CTN_CHK_CCA_NAV_C1 0x143C4
6436 #define B_BE_HE_CTN_CHK_CCA_P20 BIT(0)
6438 #define R_BE_SCHEDULE_ERR_IMR 0x103E8
6439 #define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8
6440 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6444 #define R_BE_SCHEDULE_ERR_ISR 0x103EC
6445 #define R_BE_SCHEDULE_ERR_ISR_C1 0x143EC
6447 #define B_BE_FSM_TIMEOUT_ERR_INT BIT(0)
6449 #define R_BE_PORT_CFG_P0 0x10400
6450 #define R_BE_PORT_CFG_P0_C1 0x14400
6468 #define B_BE_RXBCN_RPT_EN_P0 BIT(0)
6470 #define R_BE_TBTT_PROHIB_P0 0x10404
6471 #define R_BE_TBTT_PROHIB_P0_C1 0x14404
6473 #define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0)
6475 #define R_BE_BCN_AREA_P0 0x10408
6476 #define R_BE_BCN_AREA_P0_C1 0x14408
6477 #define B_BE_BCN_MSK_AREA_P0_MSK 0xfff
6478 #define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0)
6480 #define R_BE_BCNERLYINT_CFG_P0 0x1040C
6481 #define R_BE_BCNERLYINT_CFG_P0_C1 0x1440C
6482 #define B_BE_BCNERLY_P0_MASK GENMASK(11, 0)
6484 #define R_BE_TBTTERLYINT_CFG_P0 0x1040E
6485 #define R_BE_TBTTERLYINT_CFG_P0_C1 0x1440E
6486 #define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0)
6488 #define R_BE_TBTT_AGG_P0 0x10412
6489 #define R_BE_TBTT_AGG_P0_C1 0x14412
6492 #define R_BE_BCN_SPACE_CFG_P0 0x10414
6493 #define R_BE_BCN_SPACE_CFG_P0_C1 0x14414
6495 #define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0)
6497 #define R_BE_BCN_FORCETX_P0 0x10418
6498 #define R_BE_BCN_FORCETX_P0_C1 0x14418
6500 #define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0)
6502 #define R_BE_BCN_ERR_CNT_P0 0x10420
6503 #define R_BE_BCN_ERR_CNT_P0_C1 0x14420
6507 #define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0)
6509 #define R_BE_BCN_ERR_FLAG_P0 0x10424
6510 #define R_BE_BCN_ERR_FLAG_P0_C1 0x14424
6514 #define B_BE_BCN_ERR_FLAG_LOCK_P0 BIT(0)
6516 #define R_BE_DTIM_CTRL_P0 0x10426
6517 #define R_BE_DTIM_CTRL_P0_C1 0x14426
6519 #define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0)
6521 #define R_BE_TBTT_SHIFT_P0 0x10428
6522 #define R_BE_TBTT_SHIFT_P0_C1 0x14428
6523 #define B_BE_TBTT_SHIFT_OFST_P0_SH 0
6524 #define B_BE_TBTT_SHIFT_OFST_P0_MSK 0xfff
6526 #define R_BE_BCN_CNT_TMR_P0 0x10434
6527 #define R_BE_BCN_CNT_TMR_P0_C1 0x14434
6528 #define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)
6530 #define R_BE_TSFTR_LOW_P0 0x10438
6531 #define R_BE_TSFTR_LOW_P0_C1 0x14438
6532 #define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)
6534 #define R_BE_TSFTR_HIGH_P0 0x1043C
6535 #define R_BE_TSFTR_HIGH_P0_C1 0x1443C
6536 #define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)
6538 #define R_BE_BCN_DROP_ALL0 0x10560
6540 #define R_BE_MBSSID_CTRL 0x10568
6541 #define R_BE_MBSSID_CTRL_C1 0x14568
6560 #define R_BE_P0MB_HGQ_WINDOW_CFG_0 0x10590
6561 #define R_BE_P0MB_HGQ_WINDOW_CFG_0_C1 0x14590
6562 #define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0
6563 #define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0
6565 #define R_BE_PTCL_COMMON_SETTING_0 0x10800
6566 #define R_BE_PTCL_COMMON_SETTING_0_C1 0x14800
6576 #define B_BE_CMAC_TX_MODE_0 BIT(0)
6578 #define R_BE_TB_PPDU_CTRL 0x1080C
6579 #define R_BE_TB_PPDU_CTRL_C1 0x1480C
6586 #define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0)
6588 #define R_BE_AMPDU_AGG_LIMIT 0x10810
6589 #define R_BE_AMPDU_AGG_LIMIT_C1 0x14810
6591 #define AMPDU_MAX_TIME 0x9E
6594 #define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)
6596 #define R_BE_AGG_LEN_HT_0 0x10814
6597 #define R_BE_AGG_LEN_HT_0_C1 0x14814
6600 #define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)
6602 #define R_BE_SIFS_SETTING 0x10824
6603 #define R_BE_SIFS_SETTING_C1 0x14824
6608 #define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
6610 #define R_BE_TXRATE_CHK 0x10828
6611 #define R_BE_TXRATE_CHK_C1 0x14828
6619 #define B_BE_CHECK_CCK_EN BIT(0)
6621 #define R_BE_MBSSID_DROP_0 0x1083C
6622 #define R_BE_MBSSID_DROP_0_C1 0x1483C
6626 #define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
6628 #define R_BE_BT_PLT 0x1087C
6629 #define R_BE_BT_PLT_C1 0x1487C
6640 #define B_BE_TX_PLT_GNT_WL BIT(0)
6642 #define R_BE_PTCL_BSS_COLOR_0 0x108A0
6643 #define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0
6647 #define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0)
6649 #define R_BE_PTCL_BSS_COLOR_1 0x108A4
6650 #define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4
6651 #define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0)
6653 #define R_BE_PTCL_IMR_2 0x108B8
6654 #define R_BE_PTCL_IMR_2_C1 0x148B8
6656 #define B_BE_TX_IDLE_TIMEOUT_IMR BIT(0)
6658 #define B_BE_PTCL_IMR_2_SET 0
6660 #define R_BE_PTCL_IMR0 0x108C0
6661 #define R_BE_PTCL_IMR0_C1 0x148C0
6664 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6672 #define R_BE_PTCL_ISR0 0x108C4
6673 #define R_BE_PTCL_ISR0_C1 0x148C4
6676 #define B_BE_FSM_TIMEOUT_ERR BIT(0)
6678 #define R_BE_PTCL_IMR1 0x108C8
6679 #define R_BE_PTCL_IMR1_C1 0x148C8
6714 #define R_BE_PTCL_ISR1 0x108CC
6715 #define R_BE_PTCL_ISR1_C1 0x148CC
6733 #define R_BE_PTCL_FSM_MON 0x108E8
6734 #define R_BE_PTCL_FSM_MON_C1 0x148E8
6742 #define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
6744 #define R_BE_PTCL_TX_CTN_SEL 0x108EC
6745 #define R_BE_PTCL_TX_CTN_SEL_C1 0x148EC
6749 #define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0)
6751 #define R_BE_PTCL_DBG_INFO 0x108F0
6753 #define R_BE_PTCL_DBG 0x108F4
6755 #define R_BE_RX_ERROR_FLAG 0x10C00
6756 #define R_BE_RX_ERROR_FLAG_C1 0x14C00
6788 #define B_BE_RX_CSI_PKT_NUM_ERROR BIT(0)
6790 #define R_BE_RX_ERROR_FLAG_IMR 0x10C04
6791 #define R_BE_RX_ERROR_FLAG_IMR_C1 0x14C04
6823 #define B_BE_RX_CSI_PKT_NUM_ERROR_IMR BIT(0)
6869 #define R_BE_RX_CTRL_1 0x10C0C
6870 #define R_BE_RX_CTRL_1_C1 0x14C0C
6875 #define B_BE_DBG_SEL_MASK GENMASK(1, 0)
6876 #define WLCPU_RXCH2_QID 0xA
6878 #define R_BE_TX_ERROR_FLAG 0x10C6C
6879 #define R_BE_TX_ERROR_FLAG_C1 0x14C6C
6899 #define R_BE_TX_ERROR_FLAG_IMR 0x10C70
6900 #define R_BE_TX_ERROR_FLAG_IMR_C1 0x14C70
6956 #define R_BE_RX_ERROR_FLAG_1 0x10C84
6957 #define R_BE_RX_ERROR_FLAG_1_C1 0x14C84
6975 #define R_BE_RX_ERROR_FLAG_IMR_1 0x10C88
6976 #define R_BE_RX_ERROR_FLAG_IMR_1_C1 0x14C88
7026 #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08
7027 #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08
7031 #define B_BE_UPD_TIMIE BIT(0)
7033 #define R_BE_WMTX_POWER_BE_BIT_CTL 0x10E0C
7034 #define R_BE_WMTX_POWER_BE_BIT_CTL_C1 0x14E0C
7036 #define R_BE_WMTX_TCR_BE_4 0x10E2C
7037 #define R_BE_WMTX_TCR_BE_4_C1 0x14E2C
7043 #define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0)
7045 #define R_BE_RSP_CHK_SIG 0x11000
7046 #define R_BE_RSP_CHK_SIG_C1 0x15000
7057 #define B_BE_ACKTO_MASK GENMASK(8, 0)
7059 #define R_BE_TRXPTCL_RESP_0 0x11004
7060 #define R_BE_TRXPTCL_RESP_0_C1 0x15004
7074 #define WMAC_SPEC_SIFS_OFDM_1115E 0x11
7075 #define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
7077 #define R_BE_TRXPTCL_RESP_1 0x11008
7078 #define R_BE_TRXPTCL_RESP_1_C1 0x15008
7086 #define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0)
7088 #define R_BE_MAC_LOOPBACK 0x11020
7089 #define R_BE_MAC_LOOPBACK_C1 0x15020
7094 #define S_BE_MACLBK_PLCP_DLY_DEF 0x28
7096 #define B_BE_MACLBK_EN BIT(0)
7098 #define R_BE_WMAC_NAV_CTL 0x11080
7099 #define R_BE_WMAC_NAV_CTL_C1 0x15080
7105 #define NAV_25MS 0xC4
7106 #define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
7108 #define R_BE_RXTRIG_TEST_USER_2 0x110B0
7109 #define R_BE_RXTRIG_TEST_USER_2_C1 0x150B0
7115 #define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
7117 #define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC
7118 #define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC
7132 #define B_BE_TMAC_MACTX BIT(0)
7154 #define R_BE_TRXPTCL_ERROR_INDICA 0x110C0
7155 #define R_BE_TRXPTCL_ERROR_INDICA_C1 0x150C0
7165 #define B_BE_MACTX_ERROR_FLAG_CLR BIT(0)
7167 #define R_BE_DBGSEL_TRXPTCL 0x110F4
7168 #define R_BE_DBGSEL_TRXPTCL_C1 0x150F4
7171 #define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
7173 #define R_BE_PHYINFO_ERR_IMR_V1 0x110F8
7174 #define R_BE_PHYINFO_ERR_IMR_V1_C1 0x150F8
7185 #define B_BE_PHY_TXON_TIMEOUT_EN BIT(0)
7192 #define B_BE_PHYINFO_ERR_IMR_V1_SET 0
7194 #define R_BE_PHYINFO_ERR_ISR 0x110FC
7195 #define R_BE_PHYINFO_ERR_ISR_C1 0x150FC
7201 #define B_BE_PHY_TXON_TIMEOUT_ERR BIT(0)
7203 #define R_BE_BFMEE_RESP_OPTION 0x11180
7204 #define R_BE_BFMEE_RESP_OPTION_C1 0x15180
7206 #define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf
7208 #define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3
7217 #define B_BE_BFMEE_HT_NDPA_EN BIT(0)
7219 #define R_BE_TRXPTCL_RESP_CSI_CTRL_0 0x11188
7220 #define R_BE_TRXPTCL_RESP_CSI_CTRL_0_C1 0x15188
7239 #define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
7240 #define CSI_RX_BW_CFG 0x1
7241 #define R_BE_TRXPTCL_RESP_CSI_CTRL_1 0x11194
7242 #define R_BE_TRXPTCL_RESP_CSI_CTRL_1_C1 0x15194
7244 #define CSI_RRSC_BITMAP_CFG 0x2A
7246 #define R_BE_TRXPTCL_RESP_CSI_RRSC 0x1118C
7247 #define R_BE_TRXPTCL_RESP_CSI_RRSC_C1 0x1518C
7248 #define CSI_RRSC_BMAP_BE 0x2A2AFF
7250 #define R_BE_TRXPTCL_RESP_CSI_RATE 0x11190
7251 #define R_BE_TRXPTCL_RESP_CSI_RATE_C1 0x15190
7255 #define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0)
7256 #define CSI_INIT_RATE_EHT 0x3
7258 #define R_BE_WMAC_ACK_BA_RESP_LEGACY 0x11200
7259 #define R_BE_WMAC_ACK_BA_RESP_LEGACY_C1 0x15200
7276 #define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0)
7278 #define R_BE_WMAC_ACK_BA_RESP_HE 0x11204
7279 #define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204
7296 #define B_BE_ACK_BA_RESP_HE_CHK_CCA BIT(0)
7298 #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC 0x11208
7299 #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC_C1 0x15208
7316 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0)
7318 #define R_BE_RCR 0x11400
7319 #define R_BE_RCR_C1 0x15400
7329 #define B_BE_CH_EN BIT(0)
7331 #define R_BE_DLK_PROTECT_CTL 0x11402
7332 #define R_BE_DLK_PROTECT_CTL_C1 0x15402
7340 #define B_BE_RX_DLK_INT_EN BIT(0)
7342 #define R_BE_PLCP_HDR_FLTR 0x11404
7343 #define R_BE_PLCP_HDR_FLTR_C1 0x15404
7353 #define B_BE_CCK_CRC_CHK BIT(0)
7355 #define R_BE_RX_FLTR_OPT 0x11420
7356 #define R_BE_RX_FLTR_OPT_C1 0x15420
7372 #define B_BE_SNIFFER_MODE BIT(0)
7374 #define R_BE_CTRL_FLTR 0x11424
7375 #define R_BE_CTRL_FLTR_C1 0x15424
7376 #define B_BE_CTRL_STYPE_MASK GENMASK(15, 0)
7377 #define RX_FLTR_FRAME_DROP_BE 0x0000
7378 #define RX_FLTR_FRAME_ACCEPT_BE 0xFFFF
7380 #define R_BE_MGNT_FLTR 0x11428
7381 #define R_BE_MGNT_FLTR_C1 0x15428
7382 #define B_BE_MGNT_STYPE_MASK GENMASK(15, 0)
7384 #define R_BE_DATA_FLTR 0x1142C
7385 #define R_BE_DATA_FLTR_C1 0x1542C
7386 #define B_BE_DATA_STYPE_MASK GENMASK(15, 0)
7388 #define R_BE_ADDR_CAM_CTRL 0x11434
7389 #define R_BE_ADDR_CAM_CTRL_C1 0x15434
7391 #define ADDR_CAM_SERCH_RANGE  0x7f
7398 #define B_BE_ADDR_CAM_EN BIT(0)
7400 #define R_BE_RESPBA_CAM_CTRL 0x1143C
7401 #define R_BE_RESPBA_CAM_CTRL_C1 0x1543C
7411 #define B_BE_BACAM_RST_MASK GENMASK(1, 0)
7412 #define S_BE_BACAM_RST_DONE 0
7416 #define R_BE_PPDU_STAT 0x11440
7417 #define R_BE_PPDU_STAT_C1 0x15440
7428 #define B_BE_PPDU_STAT_RPT_EN BIT(0)
7430 #define R_BE_RX_SR_CTRL 0x1144A
7431 #define R_BE_RX_SR_CTRL_C1 0x1544A
7435 #define B_BE_SR_EN BIT(0)
7437 #define R_BE_BSSID_SRC_CTRL 0x1144B
7438 #define R_BE_BSSID_SRC_CTRL_C1 0x1544B
7442 #define B_BE_PLCP_SRC_EN BIT(0)
7444 #define R_BE_CSIRPT_OPTION 0x11464
7445 #define R_BE_CSIRPT_OPTION_C1 0x15464
7450 #define R_BE_RX_ERR_ISR 0x114F4
7451 #define R_BE_RX_ERR_ISR_C1 0x154F4
7461 #define B_BE_RX_ERR_CCA_TO BIT(0)
7463 #define R_BE_RX_ERR_IMR 0x114F8
7464 #define R_BE_RX_ERR_IMR_C1 0x154F8
7474 #define B_BE_RX_ERR_CCA_TO_MSK BIT(0)
7489 #define R_BE_RX_PLCP_EXT_OPTION_1 0x11514
7490 #define R_BE_RX_PLCP_EXT_OPTION_1_C1 0x15514
7505 #define B_BE_PLCP_PPDU_TYPE_SRC BIT(0)
7507 #define R_BE_RESP_CSI_RESERVED_PAGE 0x11810
7508 #define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810
7510 #define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0)
7512 #define R_BE_RESP_IMR 0x11884
7513 #define R_BE_RESP_IMR_C1 0x15884
7530 #define B_BE_RESP_DMAC_PROC_ERR_ISR_EN BIT(0)
7557 #define R_BE_PWR_MODULE 0x11900
7558 #define R_BE_PWR_MODULE_C1 0x15900
7559 #define R_BE_PWR_LISTEN_PATH 0x11988
7562 #define R_BE_PWR_REF_CTRL 0x11A20
7566 #define R_BE_PWR_OFST_LMTBF 0x11A24
7567 #define B_BE_PWR_OFST_LMTBF_DB GENMASK(8, 0)
7568 #define R_BE_PWR_FORCE_LMT 0x11A28
7571 #define R_BE_PWR_RATE_CTRL 0x11A2C
7572 #define B_BE_PWR_OFST_BYRATE_DB GENMASK(8, 0)
7576 #define R_BE_PWR_RATE_OFST_CTRL 0x11A30
7577 #define R_BE_PWR_RATE_OFST_END 0x11A38
7578 #define R_BE_PWR_RULMT_START 0x12048
7579 #define R_BE_PWR_RULMT_END 0x120e4
7581 #define R_BE_PWR_BOOST 0x11A40
7584 #define R_BE_PWR_OFST_RULMT 0x11A44
7588 #define R_BE_PWR_FORCE_MACID 0x11A48
7591 #define R_BE_PWR_REG_CTRL 0x11A50
7594 #define R_BE_PWR_COEX_CTRL 0x11A54
7595 #define B_BE_PWR_BT_VAL GENMASK(8, 0)
7598 #define R_BE_PWR_TH 0x11A78
7599 #define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
7601 #define R_BE_PWR_OFST_SW 0x11AE8
7604 #define R_BE_PWR_FTM 0x11B00
7605 #define R_BE_PWR_FTM_SS 0x11B04
7607 #define R_BE_PWR_BY_RATE 0x11E00
7608 #define R_BE_PWR_BY_RATE_MAX 0x11FA8
7609 #define R_BE_PWR_LMT 0x11FAC
7610 #define R_BE_PWR_LMT_MAX 0x12040
7611 #define R_BE_PWR_BY_RATE_END 0x12044
7612 #define R_BE_PWR_RU_LMT 0x12048
7613 #define R_BE_PWR_RU_LMT_MAX 0x120E4
7615 #define R_BE_C0_TXPWR_IMR 0x128E0
7616 #define R_BE_C0_TXPWR_IMR_C1 0x168E0
7617 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
7621 #define R_BE_TXPWR_ERR_FLAG 0x128E4
7622 #define R_BE_TXPWR_ERR_IMR 0x128E0
7623 #define R_BE_TXPWR_ERR_FLAG_C1 0x158E4
7624 #define R_BE_TXPWR_ERR_IMR_C1 0x158E0
7626 #define CMAC1_START_ADDR_BE 0x14000
7627 #define CMAC1_END_ADDR_BE 0x17FFF
7629 #define RR_MOD 0x00
7630 #define RR_MOD_V1 0x10000
7637 #define RR_MOD_V_DOWN 0x0
7638 #define RR_MOD_V_STANDBY 0x1
7639 #define RR_TXAGC 0x10001
7640 #define RR_MOD_V_TX 0x2
7641 #define RR_MOD_V_RX 0x3
7642 #define RR_MOD_V_TXIQK 0x4
7643 #define RR_MOD_V_DPK 0x5
7644 #define RR_MOD_V_RXK1 0x6
7645 #define RR_MOD_V_RXK2 0x7
7650 #define RR_MODOPT 0x01
7652 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
7653 #define RR_WLSEL 0x02
7655 #define RR_RSV1 0x05
7656 #define RR_RSV1_RST BIT(0)
7657 #define RR_BBDC 0x10005
7658 #define RR_BBDC_SEL BIT(0)
7659 #define RR_DTXLOK 0x08
7660 #define RR_RSV2 0x09
7661 #define RR_LOKVB 0x0a
7664 #define RR_TXIG 0x11
7667 #define RR_TXIG_GR0 GENMASK(1, 0)
7668 #define RR_CHTR 0x17
7670 #define RR_CHTR_TXRX GENMASK(9, 0)
7671 #define RR_CFGCH 0x18
7672 #define RR_CFGCH_V1 0x10018
7674 #define CFGCH_BAND1_2G 0
7682 #define CFGCH_BAND0_2G 0
7684 #define CFGCH_BAND0_6G 0
7686 #define CFGCH_BW_V2_20M 0
7692 #define RR_CFGCH_CH GENMASK(7, 0)
7696 #define CFGCH_BW_160M 0
7697 #define RR_APK 0x19
7699 #define RR_BTC 0x1a
7702 #define RR_RCKC 0x1b
7704 #define RR_RCKS 0x1c
7705 #define RR_RCKO 0x1d
7707 #define RR_RXKPLL 0x1e
7708 #define RR_RXKPLL_OFF GENMASK(5, 0)
7710 #define RR_RSV4 0x1f
7712 #define RR_RSV4_PLLCH GENMASK(9, 0)
7713 #define RR_RXK 0x20
7717 #define RR_LUTWA 0x33
7718 #define RR_LUTWA_MASK GENMASK(9, 0)
7719 #define RR_LUTWA_M1 GENMASK(7, 0)
7720 #define RR_LUTWA_M2 GENMASK(4, 0)
7721 #define RR_LUTWD1 0x3e
7722 #define RR_LUTWD0 0x3f
7724 #define RR_LUTWD0_LB GENMASK(5, 0)
7725 #define RR_TM 0x42
7727 #define RR_TM_VAL_V1 GENMASK(7, 0)
7729 #define RR_TM2 0x43
7731 #define RR_TXG1 0x51
7734 #define RR_TXG2 0x52
7736 #define RR_BSPAD 0x54
7737 #define RR_TXGA 0x55
7739 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
7740 #define RR_TXGA_LOK_EN BIT(0)
7741 #define RR_TXGA_V1 0x10055
7743 #define RR_GAINTX 0x56
7744 #define RR_GAINTX_ALL GENMASK(15, 0)
7746 #define RR_GAINTX_BB GENMASK(4, 0)
7747 #define RR_TXMO 0x58
7752 #define RR_TXA 0x5d
7754 #define RR_TXRSV 0x5c
7756 #define RR_BIAS 0x5e
7758 #define RR_TXAC 0x5f
7759 #define RR_TXAC_IQG GENMASK(3, 0)
7760 #define RR_BIASA 0x60
7766 #define RR_BIASA_TXG_V1 GENMASK(3, 0)
7767 #define RR_BIASA_A GENMASK(2, 0)
7768 #define RR_BIASA2 0x63
7770 #define RR_TXATANK 0x64
7773 #define RR_TXA2 0x65
7775 #define RR_TRXIQ 0x66
7776 #define RR_RSV6 0x6d
7777 #define RR_TXVBUF 0x7c
7779 #define RR_TXPOW 0x7f
7783 #define RR_RXPOW 0x80
7785 #define RR_RXBB 0x83
7790 #define RR_RXBB_FATT GENMASK(7, 0)
7792 #define RR_RXBB_ATTC GENMASK(2, 0)
7793 #define RR_RXG 0x84
7795 #define RR_XGLNA2 0x85
7796 #define RR_XGLNA2_SW GENMASK(1, 0)
7797 #define RR_RXAE 0x89
7798 #define RR_RXAE_IQKMOD GENMASK(3, 0)
7799 #define RR_RXA 0x8a
7801 #define RR_RXA_LNA 0x8b
7802 #define RR_RXA2 0x8c
7809 #define RR_RXA2_HATT GENMASK(6, 0)
7810 #define RR_RXA2_ATT GENMASK(3, 0)
7811 #define RR_RXIQGEN 0x8d
7814 #define RR_RXBB2 0x8f
7820 #define RR_XALNA2 0x90
7822 #define RR_XALNA2_SW GENMASK(1, 0)
7823 #define RR_DCK 0x92
7828 #define RR_DCK_LV BIT(0)
7829 #define RR_DCK1 0x93
7833 #define RR_DCK1_CLR GENMASK(3, 0)
7835 #define RR_DCK2 0x94
7837 #define RR_DCKC 0x95
7839 #define RR_IQGEN 0x97
7841 #define RR_TXIQK 0x98
7843 #define RR_TXIQK_ATT1 GENMASK(6, 0)
7844 #define RR_TIA 0x9e
7846 #define RR_MIXER 0x9f
7848 #define RR_POW 0xa0
7850 #define RR_POW_SYN_V1 GENMASK(3, 0)
7851 #define RR_LOGEN 0xa3
7853 #define RR_SX 0xaf
7854 #define RR_IBD 0xc9
7855 #define RR_IBD_VAL GENMASK(4, 0)
7856 #define RR_LDO 0xb1
7858 #define RR_VCO 0xb2
7860 #define RR_VCI 0xb3
7862 #define RR_LPF 0xb7
7864 #define RR_XTALX2 0xb8
7865 #define RR_MALSEL 0xbe
7866 #define RR_SYNFB 0xc5
7868 #define RR_AACK 0xca
7869 #define RR_LCKST 0xcf
7870 #define RR_LCKST_BIN BIT(0)
7871 #define RR_LCK_TRG 0xd3
7874 #define RR_MMD 0xd5
7877 #define RR_SMD 0xd6
7879 #define RR_IQKPLL 0xdc
7881 #define RR_SYNLUT 0xdd
7883 #define RR_RCKD 0xde
7886 #define RR_TXADBG 0xde
7887 #define RR_LUTDBG 0xdf
7890 #define RR_LUTPLL 0xec
7892 #define RR_LUTWE2 0xee
7895 #define RR_LUTWE 0xef
7897 #define RR_RFC 0xf0
7901 #define R_UPD_P0 0x0000
7902 #define R_BBCLK 0x0000
7904 #define R_RSTB_WATCH_DOG 0x000C
7905 #define B_P0_RSTB_WATCH_DOG BIT(0)
7908 #define R_EMLSR 0x0044
7910 #define R_CHK_LPS_STAT 0x0058
7911 #define B_CHK_LPS_STAT BIT(0)
7912 #define R_SPOOF_CG 0x00B4
7914 #define R_CHINFO_SEG 0x00B4
7915 #define B_CHINFO_SEG_LEN GENMASK(2, 0)
7917 #define R_DFS_FFT_CG 0x00B8
7919 #define B_DFS_FFT_EN BIT(0)
7920 #define R_CHINFO_DATA 0x00C0
7921 #define B_CHINFO_DATA_BITMAP GENMASK(22, 0)
7922 #define R_ANAPAR_PW15 0x030C
7926 #define R_ANAPAR 0x032C
7933 #define B_ANAPAR_14 GENMASK(15, 0)
7934 #define R_RFE_E_A2 0x0334
7935 #define R_RFE_O_SEL_A2 0x0338
7936 #define R_RFE_SEL0_A2 0x033C
7937 #define B_RFE_SEL0_MASK GENMASK(1, 0)
7938 #define R_RFE_SEL32_A2 0x0340
7939 #define R_CIRST 0x035c
7941 #define R_SWSI_DATA_V1 0x0370
7942 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
7946 #define R_SWSI_BIT_MASK_V1 0x0374
7947 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
7948 #define R_SWSI_READ_ADDR_V1 0x0378
7949 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
7951 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
7952 #define R_BRK_R 0x0418
7955 #define R_BRK_EHT 0x0474
7957 #define R_BRK_RXEHT 0x0478
7960 #define R_EN_SND_WO_NDP 0x047c
7961 #define R_EN_SND_WO_NDP_C1 0x147c
7963 #define R_BRK_HE 0x0480
7967 #define R_RXCCA_BE1 0x0520
7968 #define B_RXCCA_BE1_DIS BIT(0)
7969 #define R_UPD_CLK_ADC 0x0700
7974 #define R_RSTB_ASYNC 0x0704
7977 #define R_P0_ANT_SW 0x0728
7979 #define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
7980 #define R_MAC_PIN_SEL 0x0734
7982 #define R_PLCP_HISTOGRAM 0x0738
7988 #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C
7989 #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f
7990 #define R_PHY_STS_BITMAP_R2T 0x0740
7991 #define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744
7992 #define R_PHY_STS_BITMAP_OFDM_BRK 0x0748
7993 #define R_PHY_STS_BITMAP_CCK_BRK 0x074C
7994 #define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750
7995 #define R_PHY_STS_BITMAP_HE_MU 0x0754
7996 #define R_PHY_STS_BITMAP_VHT_MU 0x0758
7997 #define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C
7998 #define R_PHY_STS_BITMAP_TRIGBASE 0x0760
7999 #define R_PHY_STS_BITMAP_CCK 0x0764
8000 #define R_PHY_STS_BITMAP_LEGACY 0x0768
8001 #define R_PHY_STS_BITMAP_HT 0x076C
8002 #define R_PHY_STS_BITMAP_VHT 0x0770
8003 #define R_PHY_STS_BITMAP_HE 0x0774
8004 #define R_EDCCA_RPTREG_SEL_BE 0x078C
8006 #define R_PMAC_GNT 0x0980
8007 #define B_PMAC_GNT_TXEN BIT(0)
8011 #define R_PMAC_RX_CFG1 0x0988
8012 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
8013 #define R_PMAC_RXMOD 0x0994
8015 #define R_MAC_SEL 0x09A4
8021 #define R_PMAC_TX_CTRL 0x09C0
8022 #define B_PMAC_TXEN_DIS BIT(0)
8023 #define R_PMAC_TX_PRD 0x09C4
8025 #define B_PMAC_CTX_EN BIT(0)
8027 #define R_PMAC_TX_CNT 0x09C8
8028 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
8029 #define R_P80_AT_HIGH_FREQ 0x09D8
8031 #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
8032 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
8033 #define R_CCX 0x0C00
8038 #define B_CCX_EN_MSK BIT(0)
8039 #define R_FAHM 0x0C1C
8041 #define R_IFS_COUNTER 0x0C28
8046 #define R_IFS_T1 0x0C2C
8049 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
8050 #define R_IFS_T2 0x0C30
8053 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
8054 #define R_IFS_T3 0x0C34
8057 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
8058 #define R_IFS_T4 0x0C38
8061 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
8062 #define R_PD_CTRL 0x0C3C
8064 #define R_IOQ_IQK_DPK 0x0C60
8065 #define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0)
8067 #define R_GNT_BT_WGT_EN 0x0C6C
8069 #define R_IQK_DPK_RST 0x0C6C
8070 #define R_IQK_DPK_RST_C1 0x1C6C
8071 #define B_IQK_DPK_RST BIT(0)
8072 #define R_TX_COLLISION_T2R_ST 0x0C70
8074 #define B_TXRX_FORCE_VAL GENMASK(9, 0)
8075 #define R_TXGATING 0x0C74
8077 #define R_TXRFC 0x0C7C
8078 #define R_TXRFC_C1 0x1C7C
8080 #define R_PD_ARBITER_OFF 0x0C80
8082 #define R_SNDCCA_A1 0x0C9C
8084 #define R_SNDCCA_A2 0x0CA0
8086 #define R_UDP_COEEF 0x0CBC
8088 #define R_TX_COLLISION_T2R_ST_BE 0x0CC8
8090 #define R_RXHT_MCS_LIMIT 0x0D18
8092 #define R_RXVHT_MCS_LIMIT 0x0D18
8094 #define R_P0_EN_SOUND_WO_NDP 0x0D7C
8096 #define R_RXHE 0x0D80
8100 #define R_SPOOF_ASYNC_RST 0x0D84
8102 #define R_NDP_BRK0 0xDA0
8103 #define R_NDP_BRK1 0xDA4
8104 #define B_NDP_RU_BRK BIT(0)
8105 #define R_BRK_ASYNC_RST_EN_1 0x0DC0
8106 #define R_BRK_ASYNC_RST_EN_2 0x0DC4
8107 #define R_BRK_ASYNC_RST_EN_3 0x0DC8
8108 #define R_CTLTOP 0x1008
8111 #define R_CLK_GCK 0x1008
8112 #define B_CLK_GCK GENMASK(24, 0)
8113 #define R_EDCCA_RPT_SEL_BE 0x10CC
8114 #define R_ADC_FIFO_V1 0x10FC
8116 #define R_S0_HW_SI_DIS 0x1200
8118 #define R_P0_RXCK 0x12A0
8126 #define R_P0_RFMODE 0x12AC
8129 #define R_P0_RFMODE_ORI_RX 0x12AC
8131 #define R_P0_RFMODE_FTM_RX 0x12B0
8132 #define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
8133 #define R_P0_NRBW 0x12B8
8136 #define R_S0_RXDC 0x12D4
8139 #define R_S0_RXDC2 0x12D8
8143 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
8144 #define R_CFO_COMP_SEG0_L 0x1384
8145 #define R_CFO_COMP_SEG0_H 0x1388
8146 #define R_CFO_COMP_SEG0_CTRL 0x138C
8147 #define R_DBG32_D 0x1730
8148 #define R_EDCCA_RPT_A 0x1738
8149 #define R_EDCCA_RPT_B 0x173c
8156 #define R_SWSI_V1 0x174C
8160 #define R_TX_COUNTER 0x1A40
8161 #define R_IFS_CLM_TX_CNT 0x1ACC
8162 #define R_IFS_CLM_TX_CNT_V1 0x0ECC
8164 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
8165 #define R_IFS_CLM_CCA 0x1AD0
8166 #define R_IFS_CLM_CCA_V1 0x0ED0
8168 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
8169 #define R_IFS_CLM_FA 0x1AD4
8170 #define R_IFS_CLM_FA_V1 0x0ED4
8172 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
8173 #define R_IFS_HIS 0x1AD8
8174 #define R_IFS_HIS_V1 0x0ED8
8178 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
8179 #define R_IFS_AVG_L 0x1ADC
8180 #define R_IFS_AVG_L_V1 0x0EDC
8182 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
8183 #define R_IFS_AVG_H 0x1AE0
8184 #define R_IFS_AVG_H_V1 0x0EE0
8186 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
8187 #define R_IFS_CCA_L 0x1AE4
8188 #define R_IFS_CCA_L_V1 0x0EE4
8190 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
8191 #define R_IFS_CCA_H 0x1AE8
8192 #define R_IFS_CCA_H_V1 0x0EE8
8194 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
8195 #define R_IFSCNT 0x1AEC
8196 #define R_IFSCNT_V1 0x0EEC
8198 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
8199 #define R_TXAGC_TP 0x1C04
8200 #define B_TXAGC_TP GENMASK(2, 0)
8201 #define R_TSSI_THER 0x1C10
8203 #define R_TSSI_CWRPT 0x1C18
8205 #define B_TSSI_CWRPT GENMASK(8, 0)
8206 #define R_TXAGC_BTP 0x1CA0
8208 #define R_TXAGC_BB 0x1C60
8211 #define B_TXAGC_RF GENMASK(5, 0)
8212 #define R_PATH0_TXPWR 0x1C78
8213 #define B_PATH0_TXPWR GENMASK(8, 0)
8214 #define R_S0_ADDCK 0x1E00
8215 #define B_S0_ADDCK_I GENMASK(9, 0)
8217 #define R_TXCKEN_FORCE 0x2008
8218 #define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
8219 #define R_EDCCA_RPT_SEL 0x20CC
8220 #define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)
8221 #define R_ADC_FIFO 0x20fc
8228 #define R_TXFIR0 0x2300
8229 #define B_TXFIR_C01 GENMASK(23, 0)
8230 #define R_TXFIR2 0x2304
8231 #define B_TXFIR_C23 GENMASK(23, 0)
8232 #define R_TXFIR4 0x2308
8233 #define B_TXFIR_C45 GENMASK(23, 0)
8234 #define R_TXFIR6 0x230c
8235 #define B_TXFIR_C67 GENMASK(23, 0)
8236 #define R_TXFIR8 0x2310
8237 #define B_TXFIR_C89 GENMASK(23, 0)
8238 #define R_TXFIRA 0x2314
8239 #define B_TXFIR_CAB GENMASK(23, 0)
8240 #define R_TXFIRC 0x2318
8241 #define B_TXFIR_CCD GENMASK(23, 0)
8242 #define R_TXFIRE 0x231c
8243 #define B_TXFIR_CEF GENMASK(23, 0)
8244 #define R_11B_RX_V1 0x2320
8245 #define B_11B_RXCCA_DIS_V1 BIT(0)
8246 #define R_RPL_OFST 0x2340
8248 #define R_RXCCA 0x2344
8250 #define R_RXCCA_V1 0x2320
8251 #define B_RXCCA_DIS_V1 BIT(0)
8252 #define R_RXSC 0x237C
8253 #define B_RXSC_EN BIT(0)
8254 #define R_RX_RPL_OFST 0x23AC
8255 #define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
8256 #define R_RXSCOBC 0x23B0
8257 #define B_RXSCOBC_TH GENMASK(18, 0)
8258 #define R_RXSCOCCK 0x23B4
8259 #define B_RXSCOCCK_TH GENMASK(18, 0)
8260 #define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
8263 #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
8264 #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
8265 #define R_AFEDAC0 0x2A5C
8267 #define R_AFEDAC1 0x2A60
8268 #define B_AFEDAC1 GENMASK(2, 0)
8269 #define R_IQKDPK_HC 0x2AB8
8271 #define R_HWSI_ADD0 0x2ADC
8272 #define R_HWSI_ADD1 0x2BDC
8274 #define B_HWSI_ADD_CTL_MASK GENMASK(2, 0)
8276 #define B_HWSI_ADD_POLL_MASK GENMASK(1, 0)
8278 #define B_HWSI_ADD_BUSY BIT(0)
8279 #define R_HWSI_DATA 0x2AE0
8281 #define B_HWSI_DATA_ADDR GENMASK(7, 0)
8282 #define R_HWSI_VAL0 0x2C24
8283 #define R_HWSI_VAL1 0x2D24
8286 #define R_P1_EN_SOUND_WO_NDP 0x2D7C
8288 #define R_EDCCA_RPT_A_BE 0x2E38
8289 #define R_EDCCA_RPT_B_BE 0x2E3C
8290 #define R_S1_HW_SI_DIS 0x3200
8292 #define R_P1_RXCK 0x32A0
8297 #define R_P1_RFMODE 0x32AC
8300 #define R_P1_RFMODE_ORI_RX 0x32AC
8302 #define R_P1_RFMODE_FTM_RX 0x32B0
8303 #define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
8304 #define R_P1_DBGMOD 0x32B8
8306 #define R_S1_RXDC 0x32D4
8309 #define R_S1_RXDC2 0x32D8
8312 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
8313 #define R_TXAGC_BB_S1 0x3C60
8316 #define R_PATH1_TXPWR 0x3C78
8317 #define B_PATH1_TXPWR GENMASK(8, 0)
8318 #define R_S1_ADDCK 0x3E00
8319 #define B_S1_ADDCK_I GENMASK(9, 0)
8321 #define R_OP1DB_A 0x40B0
8323 #define R_OP1DB1_A 0x40BC
8324 #define B_TIA10_A GENMASK(15, 0)
8326 #define B_TIA0_A GENMASK(7, 0)
8327 #define R_BKOFF_A 0x40E0
8329 #define R_BACKOFF_A 0x40E4
8333 #define R_RXBY_WBADC_A 0x40F4
8335 #define R_MUIC 0x40F8
8336 #define B_MUIC_EN BIT(0)
8337 #define R_BT_RXBY_WBADC_A 0x4160
8339 #define R_BT_SHARE_A 0x4164
8340 #define B_BT_SHARE_A BIT(0)
8343 #define R_FORCE_FIR_A 0x418C
8344 #define B_FORCE_FIR_A GENMASK(1, 0)
8345 #define R_DCFO 0x4264
8346 #define B_DCFO GENMASK(7, 0)
8347 #define R_SEG0CSI 0x42AC
8348 #define R_SEG0CSI_V1 0x42B0
8349 #define B_SEG0CSI_IDX GENMASK(10, 0)
8350 #define R_SEG0CSI_EN 0x42C4
8351 #define R_SEG0CSI_EN_V1 0x42C8
8353 #define R_BSS_CLR_MAP 0x43ac
8354 #define R_BSS_CLR_MAP_V1 0x43B0
8355 #define R_BSS_CLR_MAP_V2 0x4EB0
8359 #define R_CFO_TRK0 0x4404
8360 #define R_CFO_TRK1 0x440C
8362 #define R_T2F_GI_COMB 0x4424
8364 #define R_BT_DYN_DC_EST_EN 0x441C
8365 #define R_BT_DYN_DC_EST_EN_V1 0x4420
8367 #define R_ASSIGN_SBD_OPT_V1 0x4440
8369 #define R_ASSIGN_SBD_OPT 0x4450
8371 #define R_DCFO_COMP_S0 0x448C
8372 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
8373 #define R_DCFO_WEIGHT 0x4490
8376 #define R_DCFO_OPT 0x4494
8379 #define R_BANDEDGE 0x4498
8381 #define R_DPD_BF 0x44a0
8383 #define B_DPD_BF_SCA GENMASK(6, 0)
8384 #define R_LNA_OP 0x44B0
8386 #define R_LNA_TIA 0x44BC
8387 #define B_TIA10_B GENMASK(15, 0)
8389 #define B_TIA0_B GENMASK(7, 0)
8390 #define R_BKOFF_B 0x44E0
8392 #define R_BACKOFF_B 0x44E4
8396 #define R_RXBY_WBADC_B 0x44F4
8398 #define R_BT_RXBY_WBADC_B 0x4560
8400 #define R_BT_SHARE_B 0x4564
8401 #define B_BT_SHARE_B BIT(0)
8404 #define R_TXPATH_SEL 0x458C
8406 #define R_FORCE_FIR_B 0x458C
8407 #define B_FORCE_FIR_B GENMASK(1, 0)
8408 #define R_TXPWR 0x4594
8410 #define R_TXNSS_MAP 0x45B4
8412 #define R_PCOEFF0_V1 0x45BC
8413 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
8414 #define R_PCOEFF2_V1 0x45CC
8415 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
8416 #define R_PCOEFF4_V1 0x45D0
8417 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
8418 #define R_PCOEFF6_V1 0x45D4
8419 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
8420 #define R_PCOEFF8_V1 0x45D8
8421 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
8422 #define R_PCOEFFA_V1 0x45C0
8423 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
8424 #define R_PCOEFFC_V1 0x45C4
8425 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
8426 #define R_PCOEFFE_V1 0x45C8
8427 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
8428 #define R_PATH0_IB_PKPW 0x4628
8430 #define R_PATH0_LNA_ERR1 0x462C
8434 #define R_PATH0_LNA_ERR2 0x4630
8437 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
8438 #define R_PATH0_LNA_ERR3 0x4634
8442 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
8443 #define R_PATH0_LNA_ERR4 0x4638
8447 #define R_PATH0_LNA_ERR5 0x463C
8448 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
8449 #define R_PATH0_TIA_ERR_G0 0x4640
8452 #define R_PATH0_TIA_ERR_G1 0x4644
8455 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
8456 #define R_PATH0_IB_PBK 0x4650
8458 #define R_PATH0_RXB_INIT 0x4658
8460 #define R_PATH0_LNA_INIT 0x4668
8461 #define R_PATH0_LNA_INIT_V1 0x472C
8463 #define R_PATH0_BTG 0x466C
8465 #define R_PATH0_TIA_INIT 0x4674
8467 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
8468 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
8469 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
8470 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8
8472 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
8473 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
8474 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
8475 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC
8477 #define R_PATH0_RXB_INIT_V1 0x46A8
8479 #define R_PATH0_G_LNA6_OP1DB_V1 0x4688
8481 #define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
8482 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8483 #define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694
8486 #define R_CDD_EVM_CHK_EN 0x46C0
8487 #define B_CDD_EVM_CHK_EN BIT(0)
8488 #define R_PATH0_BAND_SEL_V1 0x4738
8491 #define R_PATH0_BT_SHARE_V1 0x4738
8493 #define R_PATH0_BTG_PATH_V1 0x4738
8495 #define R_P0_NBIIDX 0x469C
8496 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
8498 #define R_P0_BACKOFF_IBADC_V1 0x469C
8501 #define R_P1_MODE 0x4718
8503 #define R_P0_AGC_CTL 0x4730
8505 #define R_PATH1_LNA_INIT 0x473C
8506 #define R_PATH1_LNA_INIT_V1 0x4A80
8508 #define R_PATH0_TIA_INIT_V1 0x473C
8510 #define R_PATH1_TIA_INIT 0x4748
8512 #define R_PATH1_BTG 0x4740
8514 #define R_PATH1_RXB_INIT 0x472C
8516 #define R_PATH1_G_LNA6_OP1DB_V1 0x476C
8518 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
8519 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
8520 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
8521 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8
8523 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
8524 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
8525 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
8526 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC
8528 #define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
8529 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8530 #define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778
8532 #define R_PATH1_BAND_SEL_V1 0x4AA4
8535 #define R_PATH1_BT_SHARE_V1 0x4AA4
8537 #define R_PATH1_BTG_PATH_V1 0x4AA4
8539 #define R_P1_NBIIDX 0x4770
8540 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
8542 #define R_PKT_CTRL 0x47D4
8544 #define R_SEG0R_PD 0x481C
8545 #define R_SEG0R_PD_V1 0x4860
8546 #define R_SEG0R_PD_V2 0x6A74
8547 #define R_SEG0R_EDCCA_LVL 0x4840
8548 #define R_SEG0R_EDCCA_LVL_V1 0x4884
8551 #define B_EDCCA_LVL_MSK0 GENMASK(7, 0)
8555 #define R_PWOFST 0x488C
8557 #define R_2P4G_BAND 0x4970
8559 #define R_FC0_BW 0x4974
8560 #define R_FC0_BW_V1 0x49C0
8565 #define B_FC0_BW_INV GENMASK(6, 0)
8566 #define R_Q_MATRIX_00 0x497C
8567 #define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0)
8569 #define R_CHBW_MOD 0x4978
8570 #define R_CHBW_MOD_V1 0x49C4
8574 #define B_ANT_RX_SEG0 GENMASK(3, 0)
8575 #define R_Q_MATRIX_11 0x4988
8576 #define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0)
8578 #define R_CUSTOMIZE_Q_MATRIX 0x498C
8579 #define B_CUSTOMIZE_Q_MATRIX_EN BIT(0)
8580 #define R_P0_RPL1 0x49B0
8586 #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
8587 #define R_P0_RPL2 0x49B4
8591 #define B_P0_RTL2_42_MASK GENMASK(7, 0)
8592 #define R_P0_RPL3 0x49B8
8596 #define B_P0_RTL3_82_MASK GENMASK(7, 0)
8597 #define R_PD_BOOST_EN 0x49E8
8599 #define R_P1_BACKOFF_IBADC_V1 0x49F0
8601 #define R_P1_RPL1 0x4A00
8602 #define R_P1_RPL2 0x4A04
8603 #define R_P1_RPL3 0x4A08
8604 #define R_BK_FC0_INV_V1 0x4A1C
8605 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
8606 #define R_CCK_FC0_INV_V1 0x4A20
8607 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
8608 #define R_PATH1_RXB_INIT_V1 0x4A5C
8610 #define R_P1_AGC_CTL 0x4A9C
8612 #define R_PATH1_TIA_INIT_V1 0x4AA8
8614 #define R_P0_AGC_RSVD 0x4ACC
8615 #define R_PATH0_RXBB_V1 0x4AD4
8616 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
8617 #define R_P1_AGC_RSVD 0x4AD8
8618 #define R_PATH1_RXBB_V1 0x4AE0
8619 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
8620 #define R_PATH0_BT_BACKOFF_V1 0x4AE4
8621 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
8622 #define R_PATH1_BT_BACKOFF_V1 0x4AEC
8623 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
8624 #define R_DCFO_COMP_S0_V2 0x4B20
8625 #define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
8626 #define R_PATH0_TX_CFR 0x4B30
8628 #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
8629 #define R_PATH0_TX_POLAR_CLIPPING 0x4B3C
8632 #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
8633 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8634 #define R_PATH0_NOTCH 0x4C14
8636 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
8637 #define R_PATH0_NOTCH2 0x4C20
8639 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
8640 #define R_PATH0_5MDET 0x4C4C
8641 #define R_PATH0_5MDET_V1 0x46F8
8645 #define B_PATH0_5MDET_TH GENMASK(5, 0)
8646 #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
8647 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8648 #define R_PATH1_NOTCH 0x4CD8
8650 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
8651 #define R_PATH1_NOTCH2 0x4CE4
8653 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
8654 #define R_PATH1_5MDET 0x4D10
8655 #define R_PATH1_5MDET_V1 0x47B8
8659 #define B_PATH1_5MDET_TH GENMASK(5, 0)
8660 #define R_S0S1_CSI_WGT 0x4D34
8661 #define B_S0S1_CSI_WGT_EN BIT(0)
8663 #define R_CHINFO_ELM_SRC 0x4D84
8664 #define B_CHINFO_ELM_BITMAP GENMASK(22, 0)
8666 #define R_CHINFO_TYPE_SCAL 0x4D88
8669 #define R_RPL_BIAS_COMP 0x4DF0
8670 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
8671 #define R_RPL_PATHAB 0x4E0C
8674 #define R_RSSI_M_PATHAB 0x4E2C
8676 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
8677 #define R_FC0_V1 0x4E30
8678 #define B_FC0_MSK_V1 GENMASK(12, 0)
8679 #define R_RX_BW40_2XFFT_EN_V1 0x4E30
8681 #define R_DCFO_COMP_S0_V1 0x4A40
8682 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
8683 #define R_BMODE_PDTH_V1 0x4B64
8684 #define R_BMODE_PDTH_V2 0x6708
8686 #define R_BMODE_PDTH_EN_V1 0x4B74
8687 #define R_BMODE_PDTH_EN_V2 0x6718
8689 #define R_BSS_CLR_VLD_V2 0x4EBC
8691 #define R_CFO_COMP_SEG1_L 0x5384
8692 #define R_CFO_COMP_SEG1_H 0x5388
8693 #define R_CFO_COMP_SEG1_CTRL 0x538C
8696 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
8697 #define R_TSSI_PA_K1 0x5600
8698 #define R_TSSI_PA_K2 0x5604
8699 #define R_P0_TSSI_ALIM1 0x5630
8700 #define B_P0_TSSI_ALIM1 GENMASK(29, 0)
8703 #define B_P0_TSSI_ALIM13 GENMASK(9, 0)
8704 #define R_P0_TSSI_ALIM3 0x5634
8705 #define B_P0_TSSI_ALIM31 GENMASK(9, 0)
8706 #define R_TSSI_PA_K5 0x5638
8707 #define R_P0_TSSI_ALIM2 0x563c
8708 #define B_P0_TSSI_ALIM2 GENMASK(29, 0)
8709 #define R_P0_TSSI_ALIM4 0x5640
8710 #define R_TSSI_PA_K8 0x5644
8711 #define R_P0_TSSI_ADC_CLK 0x566c
8713 #define R_UPD_CLK 0x5670
8719 #define R_TXPWRB 0x56CC
8722 #define R_DPD_OFT_EN 0x5800
8726 #define B_DPD_REF GENMASK(8, 0)
8727 #define R_P0_TSSIC 0x5814
8729 #define R_DPD_OFT_ADDR 0x5804
8731 #define R_TXPWRB_H 0x580c
8733 #define R_P0_TMETER 0x5810
8737 #define R_P0_ADCFF_EN 0x58C8
8739 #define R_P1_TSSIC 0x7814
8741 #define R_P0_TSSI_TRK 0x5818
8745 #define B_P0_TSSI_OFT GENMASK(7, 0)
8746 #define R_P0_TSSI_AVG 0x5820
8749 #define R_P0_RFCTM 0x5864
8755 #define R_P0_TRSW 0x5868
8760 #define B_P0_TRSW_B BIT(0)
8761 #define B_P0_ANT_TRAIN_EN BIT(0)
8763 #define R_P0_ANTSEL 0x586C
8772 #define R_RFSW_CTRL_ANT0_BASE 0x5870
8773 #define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
8774 #define R_RFE_SEL0_BASE 0x5880
8775 #define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
8776 #define R_RFE_SEL32_BASE 0x5884
8778 #define R_RFE_INV0 0x5890
8779 #define R_P0_RFM 0x5894
8783 #define B_P0_RFM_OUT GENMASK(4, 0)
8784 #define R_P0_PATH_RST 0x58AC
8786 #define R_P0_TXDPD 0x58D4
8788 #define R_P0_TXPW_RSTB 0x58DC
8791 #define R_P0_TSSI_MV_AVG 0x58E4
8796 #define R_TXGAIN_SCALE 0x58F0
8799 #define R_P0_DAC_COMP_POST_DPD_EN 0x58F8
8801 #define R_P0_TSSI_BASE 0x5C00
8802 #define R_S0_DACKI 0x5E00
8805 #define R_S0_DACKI2 0x5E30
8807 #define R_S0_DACKI7 0x5E44
8809 #define R_S0_DACKI8 0x5E48
8811 #define R_S0_DACKQ 0x5E50
8814 #define R_S0_DACKQ2 0x5E80
8816 #define R_S0_DACKQ7 0x5E94
8818 #define R_S0_DACKQ8 0x5E98
8820 #define R_DCFO_WEIGHT_V1 0x6244
8822 #define R_DAC_CLK 0x625C
8824 #define R_DCFO_OPT_V1 0x6260
8826 #define R_TXFCTR 0x627C
8828 #define R_TXSCALE 0x6284
8830 #define R_PCOEFF01 0x6684
8831 #define B_PCOEFF01 GENMASK(23, 0)
8832 #define R_PCOEFF23 0x6688
8833 #define B_PCOEFF23 GENMASK(23, 0)
8834 #define R_PCOEFF45 0x668c
8835 #define B_PCOEFF45 GENMASK(23, 0)
8836 #define R_PCOEFF67 0x6690
8837 #define B_PCOEFF67 GENMASK(23, 0)
8838 #define R_PCOEFF89 0x6694
8839 #define B_PCOEFF89 GENMASK(23, 0)
8840 #define R_PCOEFFAB 0x6698
8841 #define B_PCOEFFAB GENMASK(23, 0)
8842 #define R_PCOEFFCD 0x669c
8843 #define B_PCOEFFCD GENMASK(23, 0)
8844 #define R_PCOEFFEF 0x66a0
8845 #define B_PCOEFFEF GENMASK(23, 0)
8846 #define R_MGAIN_BIAS 0x672c
8847 #define B_MGAIN_BIAS_BW20 GENMASK(3, 0)
8849 #define R_CCK_RPL_OFST 0x6750
8850 #define B_CCK_RPL_OFST GENMASK(7, 0)
8851 #define R_BK_FC0INV 0x6758
8852 #define B_BK_FC0INV GENMASK(18, 0)
8853 #define R_CCK_FC0INV 0x675c
8854 #define B_CCK_FC0INV GENMASK(18, 0)
8855 #define R_SEG0R_EDCCA_LVL_BE 0x69EC
8856 #define R_SEG0R_PPDU_LVL_BE 0x69F0
8857 #define R_SEGSND 0x6A14
8859 #define R_DBCC 0x6B48
8860 #define B_DBCC_EN BIT(0)
8861 #define R_FC0 0x6B4C
8863 #define B_FC0 GENMASK(12, 0)
8864 #define R_FC0INV_SBW 0x6B50
8868 #define B_FC0_INV GENMASK(6, 0)
8869 #define R_ANT_CHBW 0x6B54
8873 #define B_ANT_RX_SG0 GENMASK(3, 0)
8874 #define R_SLOPE 0x6B6C
8877 #define B_SLOPE_A GENMASK(13, 0)
8878 #define R_SC_CORNER 0x6B70
8879 #define B_SC_CORNER GENMASK(10, 0)
8880 #define R_MAG_A 0x6BF4
8882 #define R_MAG_AB 0x6BF8
8884 #define B_MAG_AB GENMASK(23, 0)
8885 #define R_BEDGE 0x6BFC
8888 #define R_BEDGE2 0x6C00
8890 #define B_HT_VHT_TH GENMASK(11, 0)
8891 #define R_BEDGE3 0x6C04
8896 #define B_BEDGE_CFG GENMASK(1, 0)
8897 #define R_SU_PUNC 0x6C08
8899 #define R_BEDGE5 0x6C10
8902 #define R_RPL_BIAS_COMP1 0x6DF0
8903 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
8904 #define R_DBCC_FA 0x703C
8906 #define R_P1_TSSI_ALIM1 0x7630
8907 #define B_P1_TSSI_ALIM1 GENMASK(29, 0)
8910 #define B_P1_TSSI_ALIM13 GENMASK(9, 0)
8911 #define R_P1_TSSI_ALIM3 0x7634
8912 #define B_P1_TSSI_ALIM31 GENMASK(9, 0)
8913 #define R_P1_TSSI_ALIM2 0x763c
8914 #define B_P1_TSSI_ALIM2 GENMASK(29, 0)
8915 #define R_P1_TSSI_ADC_CLK 0x766c
8917 #define R_P1_TXAGC_TH 0x7800
8918 #define B_P1_TXAGC_MAXMIN GENMASK(15, 0)
8919 #define R_P1_TXPW_FORCE 0x780C
8921 #define R_P1_TSSIC 0x7814
8923 #define R_P1_TMETER 0x7810
8927 #define R_P1_TSSI_TRK 0x7818
8931 #define B_P1_TSSI_OFT GENMASK(7, 0)
8932 #define R_P1_TSSI_AVG 0x7820
8935 #define R_P1_RFCTM 0x7864
8941 #define R_P1_PATH_RST 0x78AC
8943 #define R_P1_ADCFF_EN 0x78C8
8945 #define R_P1_TXPW_RSTB 0x78DC
8948 #define R_P1_TSSI_MV_AVG 0x78E4
8953 #define R_P1_DAC_COMP_POST_DPD_EN 0x78F8
8955 #define R_TSSI_THOF 0x7C00
8956 #define R_S1_DACKI 0x7E00
8959 #define R_S1_DACKI2 0x7E30
8961 #define R_S1_DACKI7 0x7E44
8963 #define R_S1_DACKI8 0x7E48
8965 #define R_S1_DACKQ 0x7E50
8968 #define R_S1_DACKQ2 0x7E80
8970 #define R_S1_DACKQ7 0x7E94
8972 #define R_S1_DACKQ8 0x7E98
8974 #define R_NCTL_CFG 0x8000
8976 #define R_NCTL_RPT 0x8008
8978 #define R_NCTL_N1 0x8010
8979 #define B_NCTL_N1_CIP GENMASK(7, 0)
8980 #define R_NCTL_N2 0x8014
8981 #define R_IQK_COM 0x8018
8982 #define R_IQK_DIF 0x801C
8983 #define B_IQK_DIF_TRX GENMASK(1, 0)
8984 #define R_IQK_DIF1 0x8020
8985 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
8986 #define R_IQK_DIF2 0x8024
8987 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
8988 #define R_IQK_DIF4 0x802C
8990 #define B_IQK_DIF4_TXT GENMASK(11, 0)
8991 #define IQK_DF4_TXT_8_25MHZ 0x021
8992 #define R_IQK_CFG 0x8034
8994 #define R_IQK_RXA 0x8044
8996 #define R_TPG_SEL 0x8068
8997 #define R_TPG_MOD 0x806C
8999 #define R_MDPK_SYNC 0x8070
9003 #define R_MDPK_RX_DCK 0x8074
9005 #define R_KIP_MOD 0x8078
9006 #define B_KIP_MOD GENMASK(19, 0)
9007 #define R_NCTL_RW 0x8080
9008 #define R_KIP_SYSCFG 0x8088
9009 #define R_KIP_CLK 0x808C
9010 #define R_DPK_IDL 0x809C
9013 #define R_LDL_NORM 0x80A0
9016 #define B_LDL_NORM_OP GENMASK(1, 0)
9017 #define R_DPK_CTL 0x80B0
9019 #define R_DPK_CFG 0x80B8
9021 #define R_DPK_CFG2 0x80BC
9023 #define R_DPK_CFG3 0x80C0
9024 #define R_KPATH_CFG 0x80D0
9026 #define R_KIP_RPT1 0x80D4
9029 #define R_SRAM_IQRX 0x80D8
9030 #define R_IDL_MPA 0x80DC
9033 #define B_IDL_MD500 BIT(0)
9034 #define R_GAPK 0x80E0
9035 #define B_GAPK_ADR BIT(0)
9036 #define R_SRAM_IQRX2 0x80E8
9037 #define R_DPK_MPA 0x80EC
9041 #define R_DPK_WR 0x80F4
9043 #define R_DPK_TRK 0x80f0
9045 #define R_RPT_COM 0x80FC
9049 #define B_RPT_COM_RDY GENMASK(15, 0)
9050 #define B_PRT_COM_DCQ GENMASK(11, 0)
9053 #define B_PRT_COM_CORI GENMASK(7, 0)
9054 #define B_PRT_COM_RXBB GENMASK(5, 0)
9055 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
9056 #define B_PRT_COM_DONE BIT(0)
9057 #define R_COEF_SEL 0x8104
9058 #define R_COEF_SEL_C1 0x8204
9059 #define B_COEF_SEL_IQC BIT(0)
9060 #define B_COEF_SEL_IQC_V1 GENMASK(1, 0)
9064 #define R_CFIR_SYS 0x8120
9065 #define R_IQK_RES 0x8124
9068 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
9069 #define R_TXIQC 0x8138
9070 #define R_RXIQC 0x813c
9071 #define B_RXIQC_BYPASS BIT(0)
9075 #define R_KIP 0x8140
9076 #define B_KIP_DBCC BIT(0)
9078 #define R_RFGAIN 0x8144
9079 #define B_RFGAIN_PAD GENMASK(4, 0)
9081 #define R_RFGAIN_BND 0x8148
9082 #define B_RFGAIN_BND GENMASK(4, 0)
9083 #define R_CFIR_MAP 0x8150
9084 #define R_CFIR_LUT 0x8154
9085 #define R_CFIR_LUT_C1 0x8254
9091 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
9092 #define B_CFIR_LUT_GP GENMASK(1, 0)
9093 #define R_DPK_GN 0x819C
9095 #define B_DPK_GN_AG GENMASK(9, 0)
9096 #define R_DPD_V1 0x81a0
9098 #define R_DPD_CH0 0x81AC
9099 #define R_DPD_BND 0x81B4
9101 #define B_DPD_BND_0 GENMASK(8, 0)
9102 #define R_DPD_CH0A 0x81BC
9106 #define B_DPD_CFG GENMASK(22, 0)
9108 #define R_TXAGC_RFK 0x81C4
9109 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
9110 #define R_DPD_COM 0x81C8
9112 #define R_KIP_IQP 0x81CC
9114 #define B_KIP_IQP_IQSW GENMASK(5, 0)
9115 #define R_KIP_RPT 0x81D4
9117 #define R_W_COEF 0x81D8
9118 #define R_LOAD_COEF 0x81DC
9120 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
9122 #define B_LOAD_COEF_AUTO BIT(0)
9123 #define R_DPK_GL 0x81F0
9125 #define B_DPK_GL_A1 GENMASK(17, 0)
9126 #define R_RPT_PER 0x81FC
9130 #define B_RPT_PER_TH GENMASK(5, 0)
9131 #define R_IQRSN 0x8220
9134 #define R_DPD_CH0B 0x82BC
9135 #define R_RXCFIR_P0C0 0x8D40
9136 #define R_RXCFIR_P0C1 0x8D84
9137 #define R_RXCFIR_P0C2 0x8DC8
9138 #define R_RXCFIR_P0C3 0x8E0C
9139 #define R_TXCFIR_P0C0 0x8F50
9140 #define R_TXCFIR_P0C1 0x8F84
9141 #define R_TXCFIR_P0C2 0x8FB8
9142 #define R_TXCFIR_P0C3 0x8FEC
9143 #define R_RXCFIR_P1C0 0x9140
9144 #define R_RXCFIR_P1C1 0x9184
9145 #define R_RXCFIR_P1C2 0x91C8
9146 #define R_RXCFIR_P1C3 0x920C
9147 #define R_TXCFIR_P1C0 0x9350
9148 #define R_TXCFIR_P1C1 0x9384
9149 #define R_TXCFIR_P1C2 0x93B8
9150 #define R_TXCFIR_P1C3 0x93EC
9151 #define R_IQKINF 0x9FE0
9155 #define B_IQKINF_FAIL GENMASK(3, 0)
9159 #define B_IQKINF_FCOR BIT(0)
9160 #define R_IQKCH 0x9FE4
9163 #define B_IQKCH_BAND GENMASK(3, 0)
9164 #define R_IQKINF2 0x9FE8
9167 #define B_IQKINF2_NCTLV GENMASK(7, 0)
9168 #define R_RFK_ST 0xBFF8
9169 #define R_DCOF0 0xC000
9172 #define R_DCOF1 0xC004
9175 #define B_DCOF1_S BIT(0)
9176 #define R_DCOF8 0xC020
9178 #define R_DCOF9 0xC024
9181 #define R_DACK_S0P0 0xC040
9183 #define R_DACK_BIAS00 0xc048
9185 #define R_DACK_S0P2 0xC05C
9188 #define R_DACK_DADCK00 0xC060
9190 #define R_DACK_S0P1 0xC064
9192 #define R_DACK_BIAS01 0xC06C
9194 #define R_DACK_S0P3 0xC080
9197 #define R_DACK_DADCK01 0xC084
9199 #define R_DRCK_FH 0xC094
9201 #define R_DRCK 0xC0C4
9205 #define B_DRCK_VAL GENMASK(4, 0)
9206 #define R_DRCK_RES 0xC0C8
9209 #define R_DRCK_V1 0xC0CC
9212 #define B_DRCK_V1_CV GENMASK(4, 0)
9213 #define R_DRCK_RS 0xC0D0
9216 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
9218 #define R_P0_CFCH_BW0 0xC0D4
9222 #define R_P0_CFCH_BW1 0xC0D8
9225 #define R_WDADC 0xC0E4
9227 #define R_ADCMOD 0xC0E8
9229 #define R_DCIM 0xC0EC
9232 #define R_ADDCK0D 0xC0F0
9236 #define R_ADDCK0 0xC0F4
9242 #define B_ADDCK0_VAL GENMASK(3, 0)
9244 #define R_ADDCK0_RL 0xC0F8
9248 #define R_ADDCKR0 0xC0FC
9251 #define B_ADDCKR0_A1 GENMASK(9, 0)
9252 #define R_DACK10 0xC100
9255 #define R_DACK1_K 0xc104
9258 #define B_DACK1_EN BIT(0)
9259 #define R_DACK11 0xC120
9261 #define R_DACK2_K 0xC124
9264 #define B_DACK2_EN BIT(0)
9265 #define R_DACK_S1P0 0xC140
9267 #define R_DACK_BIAS10 0xC148
9269 #define R_DACK10S 0xC15C
9271 #define R_DACK_S1P2 0xC15C
9273 #define R_DACK_DADCK10 0xC160
9275 #define R_DACK_S1P1 0xC164
9277 #define R_DACK_BIAS11 0xC16C
9279 #define R_DACK11S 0xC180
9281 #define R_DACK_S1P3 0xC180
9283 #define R_DACK_DADCK11 0xC184
9285 #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
9287 #define R_PATH0_BW_SEL_V1 0xC0D8
9289 #define R_PATH1_BW_SEL_V1 0xC1D8
9292 #define R_ADDCK1D 0xC1F0
9295 #define R_ADDCK1 0xC1F4
9301 #define R_ADDCK1_RL 0xC1F8
9305 #define R_ADDCKR1 0xC1fC
9307 #define B_ADDCKR1_A1 GENMASK(9, 0)
9308 #define R_DACKN0_CTL 0xC210
9309 #define B_DACKN0_EN BIT(0)
9311 #define R_DACKN1_CTL 0xC224
9313 #define B_DACKN1_ON BIT(0)
9314 #define R_DACKN2_CTL 0xC238
9315 #define B_DACKN2_ON BIT(0)
9316 #define R_DACKN3_CTL 0xC24C
9317 #define B_DACKN3_ON BIT(0)
9318 #define R_GAIN_MAP0 0xE44C
9319 #define B_GAIN_MAP0_EN BIT(0)
9320 #define R_GAIN_MAP1 0xE54C
9321 #define B_GAIN_MAP1_EN BIT(0)
9322 #define R_GOTX_IQKDPK_C0 0xE464
9323 #define R_GOTX_IQKDPK_C1 0xE564
9325 #define R_IQK_DPK_PRST 0xE4AC
9326 #define R_IQK_DPK_PRST_C1 0xE5AC
9328 #define R_TXPWR_RSTA 0xE60C
9330 #define R_TSSI_PWR_P0 0xE610
9331 #define R_TSSI_PWR_P1 0xE710
9333 #define R_TSSI_MAP_OFST_P0 0xE620
9334 #define R_TSSI_MAP_OFST_P1 0xE720
9337 #define R_TXAGC_REF0_P0 0xE628
9338 #define R_TXAGC_REF0_P1 0xE728
9339 #define B_TXAGC_REF0_OFDM_DBM GENMASK(8, 0)
9342 #define R_TXAGC_REF1_P0 0xE62C
9343 #define R_TXAGC_REF1_P1 0xE72C
9344 #define B_TXAGC_REF1_CCK_CW GENMASK(8, 0)
9345 #define R_TXPWR_RSTB 0xE70C
9349 #define R_AX_WDT_CTRL 0x0040
9356 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
9357 #define WDT_CTRL_ALL_DIS 0
9359 #define R_AX_WDT_STATUS 0x0044
9361 #define B_AX_FS_WDT_INT_MSK BIT(0)