Lines Matching refs:rtw89_write32_set
52 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RST_BDRAM); in rtw89_pci_rst_bdram_ax()
260 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask); in rtw89_pci_ctrl_txdma_ch_ax()
262 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask); in rtw89_pci_ctrl_txdma_ch_ax()
274 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); in rtw89_pci_ctrl_txdma_fw_ch_ax()
1888 rtw89_write32_set(rtwdev, info->init_cfg_reg, in rtw89_pci_ctrl_dma_trx()
1903 rtw89_write32_set(rtwdev, reg->addr, reg->mask); in rtw89_pci_ctrl_dma_io()
2458 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); in rtw89_pci_rxdma_prefth()
2506 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, in rtw89_pci_hci_ldo()
2528 rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); in rtw89_pci_power_wake_ax()
2538 rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); in rtw89_pci_autoload_hang()
2547 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT); in rtw89_pci_l12_vmain()
2555 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, in rtw89_pci_gen2_force_ib()
2557 rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3); in rtw89_pci_gen2_force_ib()
2575 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN); in rtw89_pci_wd_exit_l1()
2603 rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc); in rtw89_pci_set_lbc()
2621 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); in rtw89_pci_set_io_rcy()
2622 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); in rtw89_pci_set_io_rcy()
2623 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); in rtw89_pci_set_io_rcy()
2638 rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, in rtw89_pci_set_dbg()
2646 rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, in rtw89_pci_set_dbg()
2655 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, in rtw89_pci_set_keep_reg()
2673 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); in rtw89_pci_clr_idx_all_ax()
2675 rtw89_write32_set(rtwdev, txbd_rwptr_clr2, in rtw89_pci_clr_idx_all_ax()
2677 rtw89_write32_set(rtwdev, rxbd_rwptr_clr, in rtw89_pci_clr_idx_all_ax()
2762 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); in rtw89_pci_mode_op()
2770 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); in rtw89_pci_mode_op()
2779 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); in rtw89_pci_mode_op()
2822 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, in rtw89_pci_mode_op()
2828 rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); in rtw89_pci_mode_op()
2842 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); in rtw89_pci_ops_deinit()
2894 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA); in rtw89_pci_ops_mac_pre_init_ax()
2954 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN | in rtw89_pci_ltr_set()
3002 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, in rtw89_pci_ltr_set_v1()
3029 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); in rtw89_pci_ops_mac_post_init_ax()
3033 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, in rtw89_pci_ops_mac_post_init_ax()
3919 rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL, in rtw89_pci_clkreq_set_ax()
3922 rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL, in rtw89_pci_clkreq_set_ax()
3969 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, in rtw89_pci_aspm_set_ax()
4079 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, in rtw89_pci_l1ss_set_ax()
4290 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); in rtw89_pci_suspend()
4291 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); in rtw89_pci_suspend()
4296 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, in rtw89_pci_suspend()
4336 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); in rtw89_pci_resume()
4340 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, in rtw89_pci_resume()
4345 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, in rtw89_pci_resume()