1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
67 	    test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags))  in rtw89_mac_check_mac_en_be()
70 	    test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags))  in rtw89_mac_check_mac_en_be()
73 	    test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags))  in rtw89_mac_check_mac_en_be()
76 	return -EFAULT;  in rtw89_mac_check_mac_en_be()
81 	return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;  in is_qta_poh()
86 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_get_mix_info_be()
87 	struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;  in hfc_get_mix_info_be()
88 	struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;  in hfc_get_mix_info_be()
89 	struct rtw89_hfc_pub_info *info = &param->pub_info;  in hfc_get_mix_info_be()
93 	info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK);  in hfc_get_mix_info_be()
94 	info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK);  in hfc_get_mix_info_be()
97 	info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK);  in hfc_get_mix_info_be()
98 	info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK);  in hfc_get_mix_info_be()
99 	info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2),  in hfc_get_mix_info_be()
101 	info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1),  in hfc_get_mix_info_be()
105 	param->en = !!(val & B_BE_HCI_FC_EN);  in hfc_get_mix_info_be()
106 	param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN);  in hfc_get_mix_info_be()
107 	param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK);  in hfc_get_mix_info_be()
108 	prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK);  in hfc_get_mix_info_be()
109 	prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK);  in hfc_get_mix_info_be()
110 	prec_cfg->wp_ch07_full_cond =  in hfc_get_mix_info_be()
112 	prec_cfg->wp_ch811_full_cond =  in hfc_get_mix_info_be()
116 	prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);  in hfc_get_mix_info_be()
117 	prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);  in hfc_get_mix_info_be()
120 	pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);  in hfc_get_mix_info_be()
123 	prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);  in hfc_get_mix_info_be()
124 	prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);  in hfc_get_mix_info_be()
127 	pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);  in hfc_get_mix_info_be()
130 	pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK);  in hfc_get_mix_info_be()
131 	pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK);  in hfc_get_mix_info_be()
136 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_h2c_cfg_be()
137 	const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;  in hfc_h2c_cfg_be()
140 	val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);  in hfc_h2c_cfg_be()
146 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_mix_cfg_be()
147 	const struct rtw89_hfc_prec_cfg *prec_cfg = &param->prec_cfg;  in hfc_mix_cfg_be()
148 	const struct rtw89_hfc_pub_cfg *pub_cfg = &param->pub_cfg;  in hfc_mix_cfg_be()
151 	val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |  in hfc_mix_cfg_be()
152 	      u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);  in hfc_mix_cfg_be()
155 	val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);  in hfc_mix_cfg_be()
158 	val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |  in hfc_mix_cfg_be()
159 	      u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);  in hfc_mix_cfg_be()
163 			       param->mode, B_BE_HCI_FC_MODE_MASK);  in hfc_mix_cfg_be()
164 	val = u32_replace_bits(val, prec_cfg->ch011_full_cond,  in hfc_mix_cfg_be()
166 	val = u32_replace_bits(val, prec_cfg->h2c_full_cond,  in hfc_mix_cfg_be()
168 	val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,  in hfc_mix_cfg_be()
170 	val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,  in hfc_mix_cfg_be()
177 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_func_en_be()
181 	param->en = en;  in hfc_func_en_be()
182 	param->h2c_en = h2c_en;  in hfc_func_en_be()
215 	wde_size_cfg = cfg->wde_size;  in dle_mix_cfg_be()
216 	ple_size_cfg = cfg->ple_size;  in dle_mix_cfg_be()
220 	switch (wde_size_cfg->pge_size) {  in dle_mix_cfg_be()
232 		return -EINVAL;  in dle_mix_cfg_be()
235 	bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT;  in dle_mix_cfg_be()
237 	val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num,  in dle_mix_cfg_be()
243 	switch (ple_size_cfg->pge_size) {  in dle_mix_cfg_be()
247 		return -EINVAL;  in dle_mix_cfg_be()
258 	bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT;  in dle_mix_cfg_be()
260 	val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num,  in dle_mix_cfg_be()
294 	SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
302 			  ext_wde_min_qt_wcpu : min_cfg->wcpu;  in wde_quota_cfg_be()
303 	u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu);  in wde_quota_cfg_be()
346 	switch (rtwdev->hci.type) {  in rtw89_mac_dmac_func_pre_en_be()
392 		rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",  in rtw89_mac_write_xtal_si_be()
417 		rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);  in rtw89_mac_read_xtal_si_be()
430 	clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);  in rtw89_mac_disable_cpu_be()
587 		return -EINVAL;  in cmac_func_en_be()
603 		set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);  in cmac_func_en_be()
615 		clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);  in cmac_func_en_be()
770 	ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);  in dmac_init_be()
776 	ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode);  in dmac_init_be()
913 		return -EINVAL;  in rtw89_mac_typ_fltr_opt_be()
928 		return -EINVAL;  in rtw89_mac_typ_fltr_opt_be()
949 	u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK);  in rx_fltr_init_be()
1016 	const struct rtw89_chip_info *chip = rtwdev->chip;  in trxptcl_init_be()
1017 	const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;  in trxptcl_init_be()
1018 	struct rtw89_hal *hal = &rtwdev->hal;  in trxptcl_init_be()
1059 	rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);  in trxptcl_init_be()
1072 	if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) {  in trxptcl_init_be()
1126 		rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta;  in rmac_init_be()
1128 		rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta;  in rmac_init_be()
1130 	rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size;  in rmac_init_be()
1394 		return -ENOENT;  in dle_buf_req_be()
1406 	cmd_type = ctrl_para->cmd_type;  in set_cpuio_be()
1409 	val_op3 = u32_replace_bits(0, ctrl_para->start_pktid,  in set_cpuio_be()
1411 	val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid,  in set_cpuio_be()
1416 	val_op1 = u32_replace_bits(0, ctrl_para->src_pid,  in set_cpuio_be()
1418 	val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid,  in set_cpuio_be()
1420 	val_op1 = u32_replace_bits(val_op1, ctrl_para->macid,  in set_cpuio_be()
1425 	val_op2 = u32_replace_bits(0, ctrl_para->dst_pid,  in set_cpuio_be()
1427 	val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid,  in set_cpuio_be()
1429 	val_op2 = u32_replace_bits(val_op2, ctrl_para->macid,  in set_cpuio_be()
1436 	val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num,  in set_cpuio_be()
1454 		ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK);  in set_cpuio_be()
1484 	return -EINVAL;  in dle_upd_qta_aval_page_be()
1568 	const struct rtw89_chip_info *chip = rtwdev->chip;  in enable_imr_be()
1576 		table = chip->imr_dmac_table;  in enable_imr_be()
1578 		table = chip->imr_cmac_table;  in enable_imr_be()
1580 		return -EINVAL;  in enable_imr_be()
1582 	for (i = 0; i < table->n_regs; i++) {  in enable_imr_be()
1583 		reg = &table->regs[i];  in enable_imr_be()
1584 		addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx);  in enable_imr_be()
1587 		val &= ~reg->clr;  in enable_imr_be()
1588 		val |= reg->set;  in enable_imr_be()
1606 	if (rtwdev->dbcc_en)  in err_imr_ctrl_be()
1620 	ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);  in band1_enable_be()
1626 	ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode);  in band1_enable_be()
1675 	ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false);  in band1_disable_be()
1695 		if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {  in dbcc_enable_be()
1704 		if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {  in dbcc_enable_be()
1754 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in trx_init_be()
1755 	enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;  in trx_init_be()
1810 	if (gnt_cfg->band[0].gnt_bt)  in rtw89_mac_cfg_gnt_v2()
1814 	if (gnt_cfg->band[0].gnt_bt_sw_en)  in rtw89_mac_cfg_gnt_v2()
1818 	if (gnt_cfg->band[0].gnt_wl)  in rtw89_mac_cfg_gnt_v2()
1822 	if (gnt_cfg->band[0].gnt_wl_sw_en)  in rtw89_mac_cfg_gnt_v2()
1826 	if (gnt_cfg->band[1].gnt_bt)  in rtw89_mac_cfg_gnt_v2()
1830 	if (gnt_cfg->band[1].gnt_bt_sw_en)  in rtw89_mac_cfg_gnt_v2()
1834 	if (gnt_cfg->band[1].gnt_wl)  in rtw89_mac_cfg_gnt_v2()
1838 	if (gnt_cfg->band[1].gnt_wl_sw_en)  in rtw89_mac_cfg_gnt_v2()
1842 	if (gnt_cfg->bt[0].wlan_act_en)  in rtw89_mac_cfg_gnt_v2()
1844 	if (gnt_cfg->bt[0].wlan_act)  in rtw89_mac_cfg_gnt_v2()
1846 	if (gnt_cfg->bt[1].wlan_act_en)  in rtw89_mac_cfg_gnt_v2()
1848 	if (gnt_cfg->bt[1].wlan_act)  in rtw89_mac_cfg_gnt_v2()
1859 	struct rtw89_btc *btc = &rtwdev->btc;  in rtw89_mac_cfg_ctrl_path_v2()
1860 	struct rtw89_btc_dm *dm = &btc->dm;  in rtw89_mac_cfg_ctrl_path_v2()
1861 	struct rtw89_mac_ax_gnt *g = dm->gnt.band;  in rtw89_mac_cfg_ctrl_path_v2()
1862 	struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt;  in rtw89_mac_cfg_ctrl_path_v2()
1877 	return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);  in rtw89_mac_cfg_ctrl_path_v2()
1888 	ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);  in rtw89_mac_cfg_plt_be()
1892 	reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band);  in rtw89_mac_cfg_plt_be()
1893 	val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) |  in rtw89_mac_cfg_plt_be()
1894 	      (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) |  in rtw89_mac_cfg_plt_be()
1895 	      (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) |  in rtw89_mac_cfg_plt_be()
1896 	      (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) |  in rtw89_mac_cfg_plt_be()
1897 	      (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) |  in rtw89_mac_cfg_plt_be()
1898 	      (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) |  in rtw89_mac_cfg_plt_be()
1899 	      (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) |  in rtw89_mac_cfg_plt_be()
1900 	      (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) |  in rtw89_mac_cfg_plt_be()
2018 	enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;  in rtw89_mac_get_txpwr_cr_be()
2024 		if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))  in rtw89_mac_get_txpwr_cr_be()
2097 	u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;  in rtw89_mac_set_csi_para_reg_be()  local
2099 	u8 mac_idx = rtwvif_link->mac_idx;  in rtw89_mac_set_csi_para_reg_be()
2100 	u8 port_sel = rtwvif_link->port;  in rtw89_mac_set_csi_para_reg_be()
2114 	phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;  in rtw89_mac_set_csi_para_reg_be()
2125 	if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||  in rtw89_mac_set_csi_para_reg_be()
2126 	    (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {  in rtw89_mac_set_csi_para_reg_be()
2127 		ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);  in rtw89_mac_set_csi_para_reg_be()
2128 		stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);  in rtw89_mac_set_csi_para_reg_be()
2129 		t = u32_get_bits(link_sta->vht_cap.cap,  in rtw89_mac_set_csi_para_reg_be()
2134 	nc = min(nc, sound_dim);  in rtw89_mac_set_csi_para_reg_be()
2142 	val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) |  in rtw89_mac_set_csi_para_reg_be()
2168 	u8 mac_idx = rtwvif_link->mac_idx;  in rtw89_mac_csi_rrsc_be()
2180 	if (link_sta->he_cap.has_he) {  in rtw89_mac_csi_rrsc_be()
2185 	if (link_sta->vht_cap.vht_supported) {  in rtw89_mac_csi_rrsc_be()
2190 	if (link_sta->ht_cap.ht_supported) {  in rtw89_mac_csi_rrsc_be()
2225 		rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx);  in rtw89_mac_bf_assoc_be()
2459 	rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);  in rtw89_mac_dump_err_status_be()
2497 	rtwdev->hci.ops->dump_err_status(rtwdev);  in rtw89_mac_dump_err_status_be()
2502 	rtw89_info(rtwdev, "<---\n");  in rtw89_mac_dump_err_status_be()
2513 	grpnum = rtwdev->chip->wde_qempty_acq_grpnum;  in mac_is_txq_empty_be()
2533 	qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;  in mac_is_txq_empty_be()