Lines Matching +full:0 +full:x18800000
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
19 RTW89_DMAC_SEL = 0,
26 RTW89_FWD_DONT_CARE = 0,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
58 RTW89_MAC_LBC_TMR_8US = 0,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
83 WDE_DLE_PORT_ID_DISPATCH = 0,
93 WDE_DLE_QUEID_TXOK = 0,
101 PLE_DLE_PORT_ID_DISPATCH = 0,
113 PLE_DLE_QUEID_NO_REPORT = 0x0
117 RTW89_MGNT = 0,
123 DLE_DFI_TYPE_FREEPG = 0,
134 WDE_QTAID_HOST_IF = 0,
142 PLE_QTAID_B0_TXPL = 0,
156 DLE_CTRL_TYPE_WDE = 0,
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
173 WOWLAN_NOT_READY = 0x00,
174 WOWLAN_SLEEP_READY = 0x01,
175 WOWLAN_RESUME_READY = 0x02,
181 /* CMAC 0 related */
182 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
284 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
285 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
287 #define AXIDMA_BASE_ADDR 0x18006000
288 #define STA_SCHED_BASE_ADDR 0x18808000
289 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
290 #define SECURITY_CAM_BASE_ADDR 0x18814000
291 #define WOW_CAM_BASE_ADDR 0x18815000
292 #define CMAC_TBL_BASE_ADDR 0x18840000
293 #define ADDR_CAM_BASE_ADDR 0x18850000
294 #define BSSID_CAM_BASE_ADDR 0x18853000
295 #define BA_CAM_BASE_ADDR 0x18854000
296 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
297 #define SHARED_BUF_BASE_ADDR 0x18700000
298 #define DMAC_TBL_BASE_ADDR 0x18800000
299 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
300 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
301 #define TXD_FIFO_0_BASE_ADDR 0x18856200
302 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
303 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
304 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
305 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
306 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
307 #define CPU_LOCAL_BASE_ADDR 0x18003000
309 #define WD_PAGE_BASE_ADDR_BE 0x0
310 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
311 #define AXIDMA_BASE_ADDR_BE 0x18006000
312 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
313 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
314 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
315 #define STA_SCHED_BASE_ADDR_BE 0x18818000
316 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
317 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
318 #define SEC_CAM_BASE_ADDR_BE 0x18824000
319 #define WOW_CAM_BASE_ADDR_BE 0x18828000
320 #define MLD_TBL_BASE_ADDR_BE 0x18829000
321 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
322 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
323 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
324 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
325 #define BA_CAM_BASE_ADDR_BE 0x18859000
326 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
327 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
328 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
329 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
330 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
331 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
332 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
365 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
392 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
393 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
394 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
395 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
408 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
417 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
430 RTW89_MAC_C2H_CLASS_INFO = 0x0,
431 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
432 RTW89_MAC_C2H_CLASS_TWT = 0x2,
433 RTW89_MAC_C2H_CLASS_WOW = 0x3,
434 RTW89_MAC_C2H_CLASS_MCC = 0x4,
435 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
436 RTW89_MAC_C2H_CLASS_MRC = 0xe,
441 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
466 RTW89_MAC_MRC_START_SCH_OK = 0,
482 #define RTW89_MAC_AX_COEX_RTK_MODE 0
485 #define RTW89_MAC_AX_COEX_INNER 0
492 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
502 RTW89_MAC_BF_RRSC_6M = 0,
537 #define RTW89_R32_EA 0xEAEAEAEA
538 #define RTW89_R32_DEAD 0xDEADBEEF
543 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
544 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
558 #define S_AX_WDE_PAGE_SEL_64 0
566 #define S_AX_PLE_PAGE_SEL_64 0
582 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
584 #define SDIO_LOCAL_BASE_ADDR 0x80000000
586 #define PWR_CMD_WRITE 0
591 #define PWR_INTF_MSK_SDIO BIT(0)
594 #define PWR_INTF_MSK_ALL 0x7
596 #define PWR_BASE_MAC 0
601 #define PWR_CV_MSK_A BIT(0)
609 #define PWR_CV_MSK_ALL 0xFF
611 #define PWR_DELAY_US 0
616 #define SS_TX_LEN_MSK 0x1FFFFF
622 #define TMAC_DBG_SEL_C0 0xA5
623 #define RMAC_DBG_SEL_C0 0xA6
624 #define TRXPTCL_DBG_SEL_C0 0xA7
625 #define TMAC_DBG_SEL_C1 0xB5
626 #define RMAC_DBG_SEL_C1 0xB6
627 #define TRXPTCL_DBG_SEL_C1 0xB7
628 #define FW_PROG_CNTR_DBG_SEL 0xF2
629 #define PCIE_TXDMA_DBG_SEL 0x30
630 #define PCIE_RXDMA_DBG_SEL 0x31
631 #define PCIE_CVT_DBG_SEL 0x32
632 #define PCIE_CXPL_DBG_SEL 0x33
633 #define PCIE_IO_DBG_SEL 0x37
634 #define PCIE_MISC_DBG_SEL 0x38
635 #define PCIE_MISC2_DBG_SEL 0x00
640 #define TRXPTRL_DBG_SEL_TMAC 0
667 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
668 #define QLNKTBL_ADDR_INFO_SEL_0 0
671 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
722 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
723 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
724 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
725 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
728 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
729 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
730 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
731 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
732 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
733 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
737 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
738 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
739 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
740 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
741 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
742 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
743 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
744 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
747 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
748 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
749 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
750 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
751 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
752 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
753 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
754 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
757 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
758 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
759 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
760 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
761 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
762 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
763 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
764 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
765 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
766 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
767 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
768 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
769 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
770 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
771 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
772 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
773 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
774 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
775 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
776 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
777 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
846 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
847 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
848 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
849 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
850 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
851 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
852 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
853 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
854 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
855 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
856 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
857 MAC_AX_ERR_ASSERTION = 0x4000,
858 MAC_AX_ERR_RXI300 = 0x5000,
860 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
863 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
864 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
865 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
866 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
867 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
868 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
869 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
870 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
871 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
1030 return band == 0 ? reg_base : (reg_base + mac->band1_offset); in rtw89_mac_reg_by_idx()
1036 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); in rtw89_mac_reg_by_port()
1191 return 0; in rtw89_chip_reset_bb_rf()
1200 return 0; in rtw89_chip_reset_bb_rf()
1238 return 0; in rtw89_mac_cfg_ppdu_status_bands()
1329 return 0; in rtw89_mac_txpwr_read32()
1343 return 0; in rtw89_mac_txpwr_write32()
1357 return 0; in rtw89_mac_txpwr_write32_mask()
1420 XTAL0 = 0x0,
1421 XTAL3 = 0x3,
1422 XTAL_SI_XTAL_SC_XI = 0x04,
1423 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1424 XTAL_SI_XTAL_SC_XO = 0x05,
1425 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1426 XTAL_SI_XREF_MODE = 0x0B,
1427 XTAL_SI_PWR_CUT = 0x10,
1428 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1430 XTAL_SI_XTAL_DRV = 0x15,
1432 XTAL_SI_XTAL_PLL = 0x16,
1433 XTAL_SI_XTAL_XMD_2 = 0x24,
1435 XTAL_SI_XTAL_XMD_4 = 0x26,
1436 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1437 XTAL_SI_XREF_RF1 = 0x2D,
1438 XTAL_SI_XREF_RF2 = 0x2E,
1439 XTAL_SI_CV = 0x41,
1440 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1441 XTAL_SI_LOW_ADDR = 0x62,
1442 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1443 XTAL_SI_CTRL = 0x63,
1446 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1447 XTAL_SI_READ_VAL = 0x7A,
1448 XTAL_SI_WL_RFC_S0 = 0x80,
1449 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1450 #define XTAL_SI_RF00 BIT(0)
1451 XTAL_SI_WL_RFC_S1 = 0x81,
1452 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1453 #define XTAL_SI_RF10 BIT(0)
1454 XTAL_SI_ANAPAR_WL = 0x90,
1462 #define XTAL_SI_PON_WEI BIT(0)
1463 XTAL_SI_SRAM_CTRL = 0xA1,
1465 #define FULL_BIT_MASK GENMASK(7, 0)
1466 XTAL_SI_APBT = 0xD1,
1467 XTAL_SI_PLL = 0xE0,
1468 XTAL_SI_PLL_1 = 0xE1,