Lines Matching +full:0 +full:x1a20
11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
65 u8 res1[0x09];
70 u8 channel_plan; /* 0xb8 */
74 u8 res3[5]; /* 0xbc */
83 u8 rf_antenna_option; /* 0xc9 */
87 u8 path_a_thermal; /* 0xd0 */
100 u8 res11[0x42];
146 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
148 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
150 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
152 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
154 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
158 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
160 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
162 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
164 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
166 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
168 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
170 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
172 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
174 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
176 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
178 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
180 #define RTW8822C_EDCCA_MAX 0x7f
181 #define REG_ANAPARLDO_POW_MAC 0x0029
182 #define BIT_LDOE25_PON BIT(0)
183 #define XCAP_MASK GENMASK(6, 0)
188 #define REG_TXDFIR0 0x808
189 #define REG_DFIRBW 0x810
190 #define REG_ANTMAP0 0x820
191 #define BIT_ANT_PATH GENMASK(1, 0)
192 #define REG_ANTMAP 0x824
193 #define REG_EDCCA_DECISION 0x844
195 #define REG_DYMPRITH 0x86c
196 #define REG_DYMENTH0 0x870
197 #define REG_DYMENTH 0x874
198 #define REG_SBD 0x88c
200 #define REG_DYMTHMIN 0x8a4
202 #define REG_TXBWCTL 0x9b0
203 #define REG_TXCLK 0x9b4
205 #define REG_SCOTRK 0xc30
206 #define REG_MRCM 0xc38
207 #define REG_AGCSWSH 0xc44
208 #define REG_ANTWTPD 0xc54
209 #define REG_PT_CHSMO 0xcbc
212 #define REG_ORITXCODE 0x1800
214 #define REG_3WIRE 0x180c
216 #define BIT_3WIRE_TX_EN BIT(0)
218 #define BIT_3WIRE_EN GENMASK(1, 0)
220 #define REG_ANAPAR_A 0x1830
222 #define REG_RFTXEN_GCK_A 0x1864
224 #define REG_DIS_SHARE_RX_A 0x186c
226 #define REG_RXAGCCTL0 0x18ac
229 #define REG_DCKA_I_0 0x18bc
230 #define REG_DCKA_I_1 0x18c0
231 #define REG_DCKA_Q_0 0x18d8
232 #define REG_DCKA_Q_1 0x18dc
234 #define REG_CCKSB 0x1a00
236 #define REG_RXCCKSEL 0x1a04
237 #define REG_BGCTRL 0x1a14
239 #define REG_TXF0 0x1a20
240 #define REG_TXF1 0x1a24
241 #define REG_TXF2 0x1a28
242 #define REG_CCANRX 0x1a2c
245 #define REG_CCK_FACNT 0x1a5c
246 #define REG_CCKTXONLY 0x1a80
248 #define REG_TXF3 0x1a98
249 #define REG_TXF4 0x1a9c
250 #define REG_TXF5 0x1aa0
251 #define REG_TXF6 0x1aac
252 #define REG_TXF7 0x1ab0
253 #define REG_CCK_SOURCE 0x1abc
256 #define REG_NCTL0 0x1b00
258 #define BIT_SUBPAGE GENMASK(3, 0)
259 #define REG_DPD_CTL0_S0 0x1b04
260 #define BIT_GS_PWSF GENMASK(27, 0)
261 #define REG_DPD_CTL1_S0 0x1b08
264 #define REG_IQKSTAT 0x1b10
265 #define REG_IQK_CTL1 0x1b20
270 #define REG_TX_TONE_IDX 0x1b2c
271 #define REG_DPD_LUT0 0x1b44
273 #define REG_DPD_CTL0_S1 0x1b5c
274 #define REG_DPD_CTL1_S1 0x1b60
275 #define REG_DPD_AGC 0x1b67
276 #define REG_TABLE_SEL 0x1b98
280 #define BIT_Q_GAIN GENMASK(11, 0)
281 #define REG_TX_GAIN_SET 0x1b9c
283 #define REG_DPD_CTL0 0x1bb4
284 #define REG_SINGLE_TONE_SW 0x1bb8
286 #define REG_R_CONFIG 0x1bcc
288 #define BIT_IQ_SWITCH GENMASK(5, 0)
289 #define BIT_2G_SWING 0x2d
290 #define BIT_5G_SWING 0x36
291 #define REG_RXSRAM_CTL 0x1bd4
295 #define REG_DPD_CTL11 0x1be4
296 #define REG_DPD_CTL12 0x1be8
297 #define REG_DPD_CTL15 0x1bf4
298 #define REG_DPD_CTL16 0x1bf8
299 #define REG_STAT_RPT 0x1bfc
301 #define BIT_GAPK_RPT0 GENMASK(3, 0)
310 #define REG_TXANT 0x1c28
311 #define REG_IQK_CTRL 0x1c38
312 #define REG_ENCCK 0x1c3c
314 #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
315 #define REG_CCAMSK 0x1c80
316 #define REG_RSTB 0x1c90
318 #define REG_CH_DELAY_EXTR2 0x1cd0
324 #define REG_RX_BREAK 0x1d2c
326 #define REG_RXFNCTL 0x1d30
327 #define REG_CCA_OFF 0x1d58
329 #define REG_RXIGI 0x1d70
331 #define REG_ENFN 0x1e24
333 #define REG_TXANTSEG 0x1e28
334 #define BIT_ANTSEG GENMASK(3, 0)
335 #define REG_TXLGMAP 0x1e2c
336 #define REG_CCKPATH 0x1e5c
337 #define REG_TX_FIFO 0x1e70
338 #define BIT_STOP_TX GENMASK(3, 0)
339 #define REG_CNT_CTRL 0x1eb4
342 #define REG_OFDM_FACNT 0x2d00
343 #define REG_OFDM_FACNT1 0x2d04
344 #define REG_OFDM_FACNT2 0x2d08
345 #define REG_OFDM_FACNT3 0x2d0c
346 #define REG_OFDM_FACNT4 0x2d10
347 #define REG_OFDM_FACNT5 0x2d20
348 #define REG_RPT_CIP 0x2d9c
349 #define BIT_RPT_CIP_STATUS GENMASK(7, 0)
350 #define REG_OFDM_TXCNT 0x2de0
352 #define REG_ORITXCODE2 0x4100
353 #define REG_3WIRE2 0x410c
354 #define REG_ANAPAR_B 0x4130
355 #define REG_RFTXEN_GCK_B 0x4164
356 #define REG_DIS_SHARE_RX_B 0x416c
358 #define REG_RXAGCCTL 0x41ac
359 #define REG_DCKB_I_0 0x41bc
360 #define REG_DCKB_I_1 0x41c0
361 #define REG_DCKB_Q_0 0x41d8
362 #define REG_DCKB_Q_1 0x41dc
364 #define RF_MODE_TRXAGC 0x00
367 #define BIT_TXAGC GENMASK(4, 0)
368 #define RF_RXAGC_OFFSET 0x19
369 #define RF_BW_TRXBB 0x1a
374 #define RF_TX_GAIN_OFFSET 0x55
377 #define RF_TX_GAIN 0x56
378 #define BIT_GAIN_TXBB GENMASK(4, 0)
379 #define RF_IDAC 0x58
381 #define RF_TX_RESULT 0x5f
384 #define RF_PA 0x60
387 #define RF_TXA_LB_SW 0x63
391 #define RF_RXG_GAIN 0x87
393 #define RF_RXA_MIX_GAIN 0x8a
395 #define RF_EXT_TIA_BW 0x8f
397 #define RF_DIS_BYPASS_TXBB 0x9e
400 #define RF_DEBUG 0xde
405 #define PPG_THERMAL_B 0x1b0
407 #define PPG_2GH_TXAB 0x1d2
408 #define PPG_2G_A_MASK GENMASK(3, 0)
410 #define PPG_2GL_TXAB 0x1d4
411 #define PPG_PABIAS_2GB 0x1d5
412 #define PPG_PABIAS_2GA 0x1d6
413 #define PPG_PABIAS_MASK GENMASK(3, 0)
414 #define PPG_PABIAS_5GB 0x1d7
415 #define PPG_PABIAS_5GA 0x1d8
416 #define PPG_5G_MASK GENMASK(4, 0)
417 #define PPG_5GH1_TXB 0x1db
418 #define PPG_5GH1_TXA 0x1dc
419 #define PPG_5GM2_TXB 0x1df
420 #define PPG_5GM2_TXA 0x1e0
421 #define PPG_5GM1_TXB 0x1e3
422 #define PPG_5GM1_TXA 0x1e4
423 #define PPG_5GL2_TXB 0x1e7
424 #define PPG_5GL2_TXA 0x1e8
425 #define PPG_5GL1_TXB 0x1eb
426 #define PPG_5GL1_TXA 0x1ec
427 #define PPG_2GM_TXAB 0x1ee
428 #define PPG_THERMAL_A 0x1ef