Lines Matching +full:0 +full:x133
11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
64 u8 res1[0x09];
69 u8 channel_plan; /* 0xb8 */
73 u8 res3[5]; /* 0xbc */
82 u8 rf_antenna_option; /* 0xc9 */
86 u8 path_a_thermal; /* 0xd0 */
99 u8 res11[0x42];
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
153 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
165 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
167 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
169 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
171 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
173 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
175 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
177 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
179 #define RTW8822C_EDCCA_MAX 0x7f
180 #define REG_ANAPARLDO_POW_MAC 0x0029
181 #define BIT_LDOE25_PON BIT(0)
182 #define XCAP_MASK GENMASK(6, 0)
187 #define REG_TXDFIR0 0x808
188 #define REG_DFIRBW 0x810
189 #define REG_ANTMAP0 0x820
190 #define BIT_ANT_PATH GENMASK(1, 0)
191 #define REG_ANTMAP 0x824
192 #define REG_EDCCA_DECISION 0x844
194 #define REG_DYMPRITH 0x86c
195 #define REG_DYMENTH0 0x870
196 #define REG_DYMENTH 0x874
197 #define REG_SBD 0x88c
199 #define REG_DYMTHMIN 0x8a4
201 #define REG_TXBWCTL 0x9b0
202 #define REG_TXCLK 0x9b4
204 #define REG_SCOTRK 0xc30
205 #define REG_MRCM 0xc38
206 #define REG_AGCSWSH 0xc44
207 #define REG_ANTWTPD 0xc54
208 #define REG_PT_CHSMO 0xcbc
211 #define REG_ORITXCODE 0x1800
213 #define REG_3WIRE 0x180c
215 #define BIT_3WIRE_TX_EN BIT(0)
217 #define BIT_3WIRE_EN GENMASK(1, 0)
219 #define REG_ANAPAR_A 0x1830
221 #define REG_RFTXEN_GCK_A 0x1864
223 #define REG_DIS_SHARE_RX_A 0x186c
225 #define REG_RXAGCCTL0 0x18ac
228 #define REG_DCKA_I_0 0x18bc
229 #define REG_DCKA_I_1 0x18c0
230 #define REG_DCKA_Q_0 0x18d8
231 #define REG_DCKA_Q_1 0x18dc
233 #define REG_CCKSB 0x1a00
235 #define REG_RXCCKSEL 0x1a04
236 #define REG_BGCTRL 0x1a14
238 #define REG_TXF0 0x1a20
239 #define REG_TXF1 0x1a24
240 #define REG_TXF2 0x1a28
241 #define REG_CCANRX 0x1a2c
244 #define REG_CCK_FACNT 0x1a5c
245 #define REG_CCKTXONLY 0x1a80
247 #define REG_TXF3 0x1a98
248 #define REG_TXF4 0x1a9c
249 #define REG_TXF5 0x1aa0
250 #define REG_TXF6 0x1aac
251 #define REG_TXF7 0x1ab0
252 #define REG_CCK_SOURCE 0x1abc
255 #define REG_NCTL0 0x1b00
257 #define BIT_SUBPAGE GENMASK(3, 0)
258 #define REG_DPD_CTL0_S0 0x1b04
259 #define BIT_GS_PWSF GENMASK(27, 0)
260 #define REG_DPD_CTL1_S0 0x1b08
263 #define REG_IQKSTAT 0x1b10
264 #define REG_IQK_CTL1 0x1b20
269 #define REG_TX_TONE_IDX 0x1b2c
270 #define REG_DPD_LUT0 0x1b44
272 #define REG_DPD_CTL0_S1 0x1b5c
273 #define REG_DPD_CTL1_S1 0x1b60
274 #define REG_DPD_AGC 0x1b67
275 #define REG_TABLE_SEL 0x1b98
279 #define BIT_Q_GAIN GENMASK(11, 0)
280 #define REG_TX_GAIN_SET 0x1b9c
282 #define REG_DPD_CTL0 0x1bb4
283 #define REG_SINGLE_TONE_SW 0x1bb8
285 #define REG_R_CONFIG 0x1bcc
287 #define BIT_IQ_SWITCH GENMASK(5, 0)
288 #define BIT_2G_SWING 0x2d
289 #define BIT_5G_SWING 0x36
290 #define REG_RXSRAM_CTL 0x1bd4
294 #define REG_DPD_CTL11 0x1be4
295 #define REG_DPD_CTL12 0x1be8
296 #define REG_DPD_CTL15 0x1bf4
297 #define REG_DPD_CTL16 0x1bf8
298 #define REG_STAT_RPT 0x1bfc
300 #define BIT_GAPK_RPT0 GENMASK(3, 0)
309 #define REG_TXANT 0x1c28
310 #define REG_IQK_CTRL 0x1c38
311 #define REG_ENCCK 0x1c3c
313 #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
314 #define REG_CCAMSK 0x1c80
315 #define REG_RSTB 0x1c90
317 #define REG_CH_DELAY_EXTR2 0x1cd0
323 #define REG_RX_BREAK 0x1d2c
325 #define REG_RXFNCTL 0x1d30
326 #define REG_CCA_OFF 0x1d58
328 #define REG_RXIGI 0x1d70
330 #define REG_ENFN 0x1e24
332 #define REG_TXANTSEG 0x1e28
333 #define BIT_ANTSEG GENMASK(3, 0)
334 #define REG_TXLGMAP 0x1e2c
335 #define REG_CCKPATH 0x1e5c
336 #define REG_TX_FIFO 0x1e70
337 #define BIT_STOP_TX GENMASK(3, 0)
338 #define REG_CNT_CTRL 0x1eb4
341 #define REG_OFDM_FACNT 0x2d00
342 #define REG_OFDM_FACNT1 0x2d04
343 #define REG_OFDM_FACNT2 0x2d08
344 #define REG_OFDM_FACNT3 0x2d0c
345 #define REG_OFDM_FACNT4 0x2d10
346 #define REG_OFDM_FACNT5 0x2d20
347 #define REG_RPT_CIP 0x2d9c
348 #define BIT_RPT_CIP_STATUS GENMASK(7, 0)
349 #define REG_OFDM_TXCNT 0x2de0
351 #define REG_ORITXCODE2 0x4100
352 #define REG_3WIRE2 0x410c
353 #define REG_ANAPAR_B 0x4130
354 #define REG_RFTXEN_GCK_B 0x4164
355 #define REG_DIS_SHARE_RX_B 0x416c
357 #define REG_RXAGCCTL 0x41ac
358 #define REG_DCKB_I_0 0x41bc
359 #define REG_DCKB_I_1 0x41c0
360 #define REG_DCKB_Q_0 0x41d8
361 #define REG_DCKB_Q_1 0x41dc
363 #define RF_MODE_TRXAGC 0x00
366 #define BIT_TXAGC GENMASK(4, 0)
367 #define RF_RXAGC_OFFSET 0x19
368 #define RF_BW_TRXBB 0x1a
373 #define RF_TX_GAIN_OFFSET 0x55
376 #define RF_TX_GAIN 0x56
377 #define BIT_GAIN_TXBB GENMASK(4, 0)
378 #define RF_IDAC 0x58
380 #define RF_TX_RESULT 0x5f
383 #define RF_PA 0x60
386 #define RF_TXA_LB_SW 0x63
390 #define RF_RXG_GAIN 0x87
392 #define RF_RXA_MIX_GAIN 0x8a
394 #define RF_EXT_TIA_BW 0x8f
396 #define RF_DIS_BYPASS_TXBB 0x9e
399 #define RF_DEBUG 0xde
404 #define PPG_THERMAL_B 0x1b0
406 #define PPG_2GH_TXAB 0x1d2
407 #define PPG_2G_A_MASK GENMASK(3, 0)
409 #define PPG_2GL_TXAB 0x1d4
410 #define PPG_PABIAS_2GB 0x1d5
411 #define PPG_PABIAS_2GA 0x1d6
412 #define PPG_PABIAS_MASK GENMASK(3, 0)
413 #define PPG_PABIAS_5GB 0x1d7
414 #define PPG_PABIAS_5GA 0x1d8
415 #define PPG_5G_MASK GENMASK(4, 0)
416 #define PPG_5GH1_TXB 0x1db
417 #define PPG_5GH1_TXA 0x1dc
418 #define PPG_5GM2_TXB 0x1df
419 #define PPG_5GM2_TXA 0x1e0
420 #define PPG_5GM1_TXB 0x1e3
421 #define PPG_5GM1_TXA 0x1e4
422 #define PPG_5GL2_TXB 0x1e7
423 #define PPG_5GL2_TXA 0x1e8
424 #define PPG_5GL1_TXB 0x1eb
425 #define PPG_5GL1_TXA 0x1ec
426 #define PPG_2GM_TXAB 0x1ee
427 #define PPG_THERMAL_A 0x1ef