Lines Matching +full:0 +full:x000003ff
28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
75 u8 channel_plan; /* 0xb8 */
79 u8 pa_type; /* 0xbc */
80 u8 lna_type_2g[2]; /* 0xbd */
90 u8 rf_antenna_option; /* 0xc9 */
166 #define IQK_TX_X_ERR 0x142
167 #define IQK_TX_Y_ERR 0x42
168 #define IQK_RX_X_ERR 0x132
169 #define IQK_RX_Y_ERR 0x36
170 #define IQK_RX_X_UPPER 0x11a
171 #define IQK_RX_X_LOWER 0xe6
172 #define IQK_RX_Y_LMT 0x1a
173 #define IQK_TX_OK BIT(0)
176 #define WLAN_TXQ_RPT_EN 0x1F
178 #define SPUR_THRES 0x16
179 #define DIS_3WIRE 0xccf000c0
180 #define EN_3WIRE 0xccc000c0
181 #define START_PSD 0x400000
182 #define FREQ_CH5 0xfccd
183 #define FREQ_CH6 0xfc4d
184 #define FREQ_CH7 0xffcd
185 #define FREQ_CH8 0xff4d
186 #define FREQ_CH13 0xfccd
187 #define FREQ_CH14 0xff9a
188 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
192 #define BIT_MASK_RFMOD BIT(0)
195 #define REG_GPIO_INTM 0x0048
196 #define REG_BTG_SEL 0x0067
198 #define REG_LTECOEX_PATH_CONTROL 0x0070
199 #define REG_LTECOEX_CTRL 0x07c0
200 #define REG_LTECOEX_WRITE_DATA 0x07c4
201 #define REG_LTECOEX_READ_DATA 0x07c8
202 #define REG_PSDFN 0x0808
203 #define REG_BB_PWR_SAV1_11N 0x0874
204 #define REG_ANA_PARAM1 0x0880
205 #define REG_ANALOG_P4 0x088c
206 #define REG_PSDRPT 0x08b4
207 #define REG_FPGA1_RFMOD 0x0900
208 #define REG_BB_SEL_BTG 0x0948
209 #define REG_BBRX_DFIR 0x0954
212 #define REG_CCK0_SYS 0x0a00
214 #define REG_CCK_ANT_SEL_11N 0x0a04
215 #define REG_PWRTH 0x0a08
216 #define REG_CCK_FA_RST_11N 0x0a2c
223 #define REG_CCK_FA_LSB_11N 0x0a5c
224 #define REG_CCK_FA_MSB_11N 0x0a58
225 #define REG_CCK_CCA_CNT_11N 0x0a60
226 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
228 #define REG_PWRTH2 0x0aa8
229 #define REG_CSRATIO 0x0aaa
230 #define REG_OFDM_FA_HOLDC_11N 0x0c00
232 #define REG_BB_RX_PATH_11N 0x0c04
233 #define REG_TRMUX_11N 0x0c08
234 #define REG_OFDM_FA_RSTC_11N 0x0c0c
236 #define REG_A_RXIQI 0x0c14
237 #define BIT_MASK_RXIQ_S1_X 0x000003FF
238 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
239 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)
240 #define REG_OFDM0_RXDSP 0x0c40
243 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c
250 #define REG_OFDM0_XAAGC1 0x0c50
251 #define REG_OFDM0_XBAGC1 0x0c58
252 #define REG_AGCRSSI 0x0c78
253 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80
254 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE 0x0c88
255 #define BIT_MASK_TXIQ_ELM_A 0x03ff
256 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \
257 ((a) & 0x03ff))
259 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)
261 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94
262 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)
263 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0
264 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
265 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)
266 #define REG_TXIQ_AB_S0 0x0cd0
267 #define BIT_MASK_TXIQ_A_S0 0x000007FE
268 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)
269 #define BIT_MASK_TXIQ_B_S0 0x0007E000
270 #define REG_TXIQ_CD_S0 0x0cd4
271 #define BIT_MASK_TXIQ_C_S0 0x000007FE
272 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)
275 #define REG_RXIQ_AB_S0 0x0cd8
276 #define BIT_MASK_RXIQ_X_S0 0x000003FF
277 #define BIT_MASK_RXIQ_Y_S0 0x003FF000
278 #define REG_OFDM_FA_TYPE1_11N 0x0cf0
279 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
281 #define REG_OFDM_FA_RSTD_11N 0x0d00
284 #define REG_CTX 0x0d03
286 #define REG_OFDM1_CFOTRK 0x0d2c
288 #define REG_OFDM1_CSI1 0x0d40
289 #define REG_OFDM1_CSI2 0x0d44
290 #define REG_OFDM1_CSI3 0x0d48
291 #define REG_OFDM1_CSI4 0x0d4c
292 #define REG_OFDM_FA_TYPE2_11N 0x0da0
293 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
295 #define REG_OFDM_FA_TYPE3_11N 0x0da4
296 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
298 #define REG_OFDM_FA_TYPE4_11N 0x0da8
299 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
300 #define REG_FPGA0_IQK_11N 0x0e28
301 #define BIT_MASK_IQK_MOD 0xffffff00
302 #define EN_IQK 0x808000
303 #define RST_IQK 0x000000
304 #define REG_TXIQK_TONE_A_11N 0x0e30
305 #define REG_RXIQK_TONE_A_11N 0x0e34
306 #define REG_TXIQK_PI_A_11N 0x0e38
307 #define REG_RXIQK_PI_A_11N 0x0e3c
308 #define REG_TXIQK_11N 0x0e40
309 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
310 #define REG_RXIQK_11N 0x0e44
311 #define REG_IQK_AGC_PTS_11N 0x0e48
312 #define REG_IQK_AGC_RSP_11N 0x0e4c
313 #define REG_TX_IQK_TONE_B 0x0e50
314 #define REG_RX_IQK_TONE_B 0x0e54
315 #define REG_TXIQK_PI_B 0x0e58
316 #define REG_RXIQK_PI_B 0x0e5c
317 #define REG_IQK_RES_TX 0x0e94
319 #define REG_IQK_RES_TY 0x0e9c
321 #define REG_IQK_RES_RX 0x0ea4
323 #define REG_IQK_RES_RY 0x0eac
328 #define REG_PAGE_F_RST_11N 0x0f14
330 #define REG_IGI_C_11N 0x0f84
331 #define REG_IGI_D_11N 0x0f88
332 #define REG_HT_CRC32_CNT_11N 0x0f90
333 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
335 #define REG_OFDM_CRC32_CNT_11N 0x0f94
336 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
338 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8
340 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)
358 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ in iqk_mult()
460 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", in rtw8723x_iqk_backup_path_ctrl()
466 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723x_iqk_config_path_ctrl()
467 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", in rtw8723x_iqk_config_path_ctrl()
476 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", in rtw8723x_iqk_restore_path_ctrl()
485 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); in rtw8723x_iqk_backup_lte_path_gnt()
488 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", in rtw8723x_iqk_backup_lte_path_gnt()
497 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); in rtw8723x_iqk_config_lte_path_gnt()
499 BIT_LTE_MUX_CTRL_PATH, 0x1); in rtw8723x_iqk_config_lte_path_gnt()
507 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); in rtw8723x_iqk_restore_lte_path_gnt()
514 for (int i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) in rtw8723x_iqk_path_adda_on()