17 #define WLAN_RL_VAL 0x3030
19 #define WLAN_BAR_VAL 0x0201ffff
20 #define WLAN_PIFS_VAL 0
21 #define WLAN_RX_PKT_LIMIT 0x18
22 #define WLAN_SLOT_TIME 0x09
23 #define WLAN_SPEC_SIFS 0x100a
24 #define WLAN_MAX_AGG_NR 0x1f
25 #define WLAN_AMPDU_MAX_TIME 0x70
28 #define TBTT_PROHIBIT_SETUP_TIME 0x04
29 #define TBTT_PROHIBIT_HOLD_TIME 0x80
30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64
33 	0xFFFF,				\
36 	0,				\
37 	RTW_PWR_CMD_END, 0, 0
45 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} };
51 	{0, 0, false, 7},  /* for normal */
52 	{0, 10, false, 7}, /* for WL-CPT */
53 	{1, 0, true, 4},
60 	{0, 0, false, 7},  /* for normal */
61 	{0, 10, false, 7}, /* for WL-CPT */
62 	{1, 0, true, 5},
69 	0x0b40002d, /* 0,  -15.0dB */
70 	0x0c000030, /* 1,  -14.5dB */
71 	0x0cc00033, /* 2,  -14.0dB */
72 	0x0d800036, /* 3,  -13.5dB */
73 	0x0e400039, /* 4,  -13.0dB */
74 	0x0f00003c, /* 5,  -12.5dB */
75 	0x10000040, /* 6,  -12.0dB */
76 	0x11000044, /* 7,  -11.5dB */
77 	0x12000048, /* 8,  -11.0dB */
78 	0x1300004c, /* 9,  -10.5dB */
79 	0x14400051, /* 10, -10.0dB */
80 	0x15800056, /* 11, -9.5dB */
81 	0x16c0005b, /* 12, -9.0dB */
82 	0x18000060, /* 13, -8.5dB */
83 	0x19800066, /* 14, -8.0dB */
84 	0x1b00006c, /* 15, -7.5dB */
85 	0x1c800072, /* 16, -7.0dB */
86 	0x1e400079, /* 17, -6.5dB */
87 	0x20000080, /* 18, -6.0dB */
88 	0x22000088, /* 19, -5.5dB */
89 	0x24000090, /* 20, -5.0dB */
90 	0x26000098, /* 21, -4.5dB */
91 	0x288000a2, /* 22, -4.0dB */
92 	0x2ac000ab, /* 23, -3.5dB */
93 	0x2d4000b5, /* 24, -3.0dB */
94 	0x300000c0, /* 25, -2.5dB */
95 	0x32c000cb, /* 26, -2.0dB */
96 	0x35c000d7, /* 27, -1.5dB */
97 	0x390000e4, /* 28, -1.0dB */
98 	0x3c8000f2, /* 29, -0.5dB */
99 	0x40000100, /* 30, +0dB */
100 	0x43c0010f, /* 31, +0.5dB */
101 	0x47c0011f, /* 32, +1.0dB */
102 	0x4c000130, /* 33, +1.5dB */
103 	0x50800142, /* 34, +2.0dB */
104 	0x55400155, /* 35, +2.5dB */
105 	0x5a400169, /* 36, +3.0dB */
106 	0x5fc0017f, /* 37, +3.5dB */
107 	0x65400195, /* 38, +4.0dB */
108 	0x6b8001ae, /* 39, +4.5dB */
109 	0x71c001c7, /* 40, +5.0dB */
110 	0x788001e2, /* 41, +5.5dB */
111 	0x7f8001fe /* 42, +6.0dB */
115 	0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29,
116 	0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3,
120 	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
121 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
122 	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
123 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
124 	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
125 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
126 	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
127 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
128 	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
129 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
130 	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
131 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
132 	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
133 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
134 	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
135 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
136 	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
137 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
138 	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
139 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
140 	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
141 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
142 	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
143 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
144 	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
145 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
146 	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
147 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
148 	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
149 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
150 	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
151 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
152 	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
153 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
154 	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
155 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
156 	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
157 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
158 	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
159 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
160 	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
161 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
175 	{0x0069,
185 	 RTW_PWR_CMD_WRITE, 0xff, 0},
190 	{0x0005,
194 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
199 	{0x0023,
204 	{0x0007,
208 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
209 	{0x0006,
213 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
214 	{0x0005,
223 	{0x0020,
227 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
228 	{0x0067,
232 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
233 	{0x0001,
238 	{0x0000,
242 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
243 	{0x0005,
247 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
248 	{0x0075,
252 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
253 	{0x0004,
258 	{0x0004,
262 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
264 	{0x0006,
269 	{0x0075,
273 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
274 	{0x0006,
278 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
279 	{0x0005,
283 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
284 	{0x0005,
288 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
289 	{0x0005,
293 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
294 	{0x0005,
298 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
299 	{0x0010,
304 	{0x0049,
309 	{0x0063,
314 	{0x0062,
318 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
319 	{0x0058,
323 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
324 	{0x005A,
329 	{0x0068,
334 	{0x0069,
343 	{0x001f,
347 	 RTW_PWR_CMD_WRITE, 0xff, 0},
348 	{0x0049,
352 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
353 	{0x0006,
357 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
358 	{0x0005,
363 	{0x0005,
367 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
368 	{0x0010,
372 	 RTW_PWR_CMD_WRITE, BIT(6), 0},
373 	{0x0000,
378 	{0x0020,
382 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
391 	 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0},
397 	 RTW_PWR_CMD_WRITE, 0xff, 0},
403 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
408 	 RTW_PWR_CMD_WRITE, BIT(0), 1},
413 	{0x0301,
417 	 RTW_PWR_CMD_WRITE, 0xff, 0xff},
418 	{0x0522,
422 	 RTW_PWR_CMD_WRITE, 0xff, 0xff},
423 	{0x05f8,
427 	 RTW_PWR_CMD_POLLING, 0xff, 0},
428 	{0x05f9,
432 	 RTW_PWR_CMD_POLLING, 0xff, 0},
433 	{0x05fa,
437 	 RTW_PWR_CMD_POLLING, 0xff, 0},
438 	{0x05fb,
442 	 RTW_PWR_CMD_POLLING, 0xff, 0},
443 	{0x0002,
447 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
448 	{0x0002,
452 	 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
453 	{0x0002,
457 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
458 	{0x0100,
462 	 RTW_PWR_CMD_WRITE, 0xff, 0x03},
463 	{0x0101,
467 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
468 	{0x0093,
472 	 RTW_PWR_CMD_WRITE, 0xff, 0},
473 	{0x0553,
497 	{12, 2, 2, 0, 1},
498 	{12, 2, 2, 0, 1},
499 	{12, 2, 2, 0, 1},
500 	{12, 2, 2, 0, 1},
501 	{12, 2, 2, 0, 1},
530 		if (ret == 0) {  in try_mac_from_devicetree()
544 	if (ret != 0)  in rtw8703b_read_efuse()
550 	return 0;  in rtw8703b_read_efuse()
569 		dm_info->delta_power_index[path] = 0;  in rtw8703b_pwrtrack_init()
574 	dm_info->txagc_remnant_cck = 0;  in rtw8703b_pwrtrack_init()
575 	dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;  in rtw8703b_pwrtrack_init()
580 	u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8703b_phy_set_param()
587 	rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780);  in rtw8703b_phy_set_param()
588 	rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);  in rtw8703b_phy_set_param()
593 	/* 0xff is from vendor driver, rtw8723d uses  in rtw8703b_phy_set_param()
598 	rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);  in rtw8703b_phy_set_param()
611 	rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);  in rtw8703b_phy_set_param()
612 	rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);  in rtw8703b_phy_set_param()
613 	rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);  in rtw8703b_phy_set_param()
614 	rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);  in rtw8703b_phy_set_param()
617 	rtw_write8(rtwdev, REG_ACKTO, 0x40);  in rtw8703b_phy_set_param()
632 		   TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);  in rtw8703b_phy_set_param()
634 		   (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)  in rtw8703b_phy_set_param()
648 	rtw_write16(rtwdev, REG_ATIMWND, 0x2);  in rtw8703b_phy_set_param()
652 	if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {  in rtw8703b_phy_set_param()
655 		rtwdev->dm_info.rx_cck_agc_report_type = 0;  in rtw8703b_phy_set_param()
661 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8703b_phy_set_param()
662 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);  in rtw8703b_phy_set_param()
689 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);  in rtw8703b_cfg_notch()
690 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
691 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
692 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
693 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
694 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
695 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
703 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);  in rtw8703b_cfg_notch()
704 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
705 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000);  in rtw8703b_cfg_notch()
706 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
707 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
708 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
709 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
712 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);  in rtw8703b_cfg_notch()
713 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
714 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600);  in rtw8703b_cfg_notch()
715 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
716 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
717 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
718 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
721 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);  in rtw8703b_cfg_notch()
722 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
723 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
724 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
725 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
726 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000);  in rtw8703b_cfg_notch()
727 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
730 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);  in rtw8703b_cfg_notch()
731 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
732 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
733 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
734 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
735 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380);  in rtw8703b_cfg_notch()
736 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
739 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);  in rtw8703b_cfg_notch()
740 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
741 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
742 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
743 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
744 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000);  in rtw8703b_cfg_notch()
745 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
751 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
752 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
788 	u32 rf_rck = 0x00000C08;  in rtw8703b_set_channel_rf()
805 		rf_rck = 0x00000C4C;  in rtw8703b_set_channel_rf()
820 	[0] = {
821 		{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD },
822 		{ .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B },
825 		{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 },
826 		{ .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 },
836 	cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];  in rtw8703b_set_channel_bb()
838 	for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++)  in rtw8703b_set_channel_bb()
843 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
844 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
846 				 GENMASK(31, 30), 0x0);  in rtw8703b_set_channel_bb()
847 		rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000);  in rtw8703b_set_channel_bb()
848 		rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000);  in rtw8703b_set_channel_bb()
851 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
852 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
853 		rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000);  in rtw8703b_set_channel_bb()
854 		rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000);  in rtw8703b_set_channel_bb()
856 				 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0);  in rtw8703b_set_channel_bb()
857 		rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,  in rtw8703b_set_channel_bb()
877  * known valid values are positive, so use 0x7f as "invalid".
879 #define LNA_IDX_INVALID 0x7f
889 	s8 lna_gain = 0;  in get_cck_rx_pwr()
894 	if (lna_gain >= 0) {  in get_cck_rx_pwr()
931 	val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F;  in query_phy_status_ofdm()
938 	pkt_stat->signal_power = (val_s8 & 0x7f) - 110;  in query_phy_status_ofdm()
949 	/* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0  in query_phy_status_ofdm()
953 	val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64);  in query_phy_status_ofdm()
954 	val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */  in query_phy_status_ofdm()
967 #define ADDA_ON_VAL_8703B 0x03c00014
973 	rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F);  in rtw8703b_iqk_config_mac()
979 #define IQK_LTE_WRITE_VAL_8703B 0x00007700
994 	rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000);  in rtw8703b_iqk_one_shot()
995 	rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);  in rtw8703b_iqk_one_shot()
999 	ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000,  in rtw8703b_iqk_one_shot()
1021 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0);  in rtw8703b_iqk_txrx_path_post()
1029 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1031 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1035 		"[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1037 		rtw_read32(rtwdev, 0xe98));  in rtw8703b_iqk_check_tx_failed()
1048 	return 0;  in rtw8703b_iqk_check_tx_failed()
1056 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",  in rtw8703b_iqk_check_rx_failed()
1061 		"[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n",  in rtw8703b_iqk_check_rx_failed()
1062 		rtw_read32(rtwdev, 0xea0),  in rtw8703b_iqk_check_rx_failed()
1063 		rtw_read32(rtwdev, 0xea8));  in rtw8703b_iqk_check_rx_failed()
1077 	return 0;  in rtw8703b_iqk_check_rx_failed()
1088 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8703b_iqk_tx_path()
1089 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_tx_path()
1090 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_tx_path()
1091 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1092 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1093 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1094 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);  in rtw8703b_iqk_tx_path()
1095 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);  in rtw8703b_iqk_tx_path()
1096 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);  in rtw8703b_iqk_tx_path()
1097 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_tx_path()
1100 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);  in rtw8703b_iqk_tx_path()
1103 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_tx_path()
1106 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);  in rtw8703b_iqk_tx_path()
1107 	rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7);  in rtw8703b_iqk_tx_path()
1108 	rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400);  in rtw8703b_iqk_tx_path()
1125 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n",  in rtw8703b_iqk_rx_path()
1127 	rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000);  in rtw8703b_iqk_rx_path()
1133 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8703b_iqk_rx_path()
1134 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_rx_path()
1137 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_rx_path()
1138 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1139 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1140 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1141 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);  in rtw8703b_iqk_rx_path()
1142 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);  in rtw8703b_iqk_rx_path()
1143 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);  in rtw8703b_iqk_rx_path()
1144 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_rx_path()
1147 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);  in rtw8703b_iqk_rx_path()
1150 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);  in rtw8703b_iqk_rx_path()
1151 	rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);  in rtw8703b_iqk_rx_path()
1152 	rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);  in rtw8703b_iqk_rx_path()
1153 	rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7);  in rtw8703b_iqk_rx_path()
1157 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1168 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",  in rtw8703b_iqk_rx_path()
1173 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n",  in rtw8703b_iqk_rx_path()
1177 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_rx_path()
1178 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1179 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_rx_path()
1180 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1181 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1182 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000);  in rtw8703b_iqk_rx_path()
1183 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f);  in rtw8703b_iqk_rx_path()
1184 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);  in rtw8703b_iqk_rx_path()
1185 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_rx_path()
1188 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);  in rtw8703b_iqk_rx_path()
1191 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1193 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);  in rtw8703b_iqk_rx_path()
1195 	rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);  in rtw8703b_iqk_rx_path()
1196 	rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);  in rtw8703b_iqk_rx_path()
1197 	rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77);  in rtw8703b_iqk_rx_path()
1200 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);  in rtw8703b_iqk_rx_path()
1201 	rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5);  in rtw8703b_iqk_rx_path()
1224 	rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);  in rtw8703b_iqk_one_round()
1225 	rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600);  in rtw8703b_iqk_one_round()
1226 	rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);  in rtw8703b_iqk_one_round()
1227 	rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000);  in rtw8703b_iqk_one_round()
1229 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8703b_iqk_one_round()
1244 		result[t][IQK_S1_TX_X] = 0x100;  in rtw8703b_iqk_one_round()
1245 		result[t][IQK_S1_TX_Y] = 0x0;  in rtw8703b_iqk_one_round()
1248 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8703b_iqk_one_round()
1263 		result[t][IQK_S1_RX_X] = 0x100;  in rtw8703b_iqk_one_round()
1264 		result[t][IQK_S1_RX_Y] = 0x0;  in rtw8703b_iqk_one_round()
1267 	if (a_ok == 0x0)  in rtw8703b_iqk_one_round()
1277 	u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16);  in rtw8703b_iqk_fill_a_matrix()
1283 	if (result[IQK_S1_TX_X] == 0)  in rtw8703b_iqk_fill_a_matrix()
1306 		"[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",  in rtw8703b_iqk_fill_a_matrix()
1309 		"[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);  in rtw8703b_iqk_fill_a_matrix()
1311 	if (result[IQK_S1_RX_X] == 0)  in rtw8703b_iqk_fill_a_matrix()
1335 	memset(result, 0, sizeof(result));  in rtw8703b_phy_calibration()
1368 		s32 reg_tmp = 0;  in rtw8703b_phy_calibration()
1370 		for (i = 0; i < IQK_NR; i++)  in rtw8703b_phy_calibration()
1373 		if (reg_tmp != 0) {  in rtw8703b_phy_calibration()
1401 			result[i][0], result[i][1], result[i][2], result[i][3],  in rtw8703b_phy_calibration()
1406 		"[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",  in rtw8703b_phy_calibration()
1412 		"[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",  in rtw8703b_phy_calibration()
1455 		/* write new elements A, C, D, and element B is always 0 */  in rtw8703b_set_iqk_matrix_by_result()
1468 		/* write new elements A, C, D, and element B is always 0 */  in rtw8703b_set_iqk_matrix_by_result()
1489 	ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1);  in rtw8703b_set_iqk_matrix()
1503 				 0x00);  in rtw8703b_set_iqk_matrix()
1513 				 0x00);  in rtw8703b_set_iqk_matrix()
1540 	swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1);  in rtw8703b_pwrtrack_set_cck_pwr()
1543 		     != ARRAY_SIZE(rtw8703b_cck_swing_table[0]));  in rtw8703b_pwrtrack_set_cck_pwr()
1545 	for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++)  in rtw8703b_pwrtrack_set_cck_pwr()
1569 	else if (final_ofdm_swing_index < 0)  in rtw8703b_pwrtrack_set()
1570 		rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0,  in rtw8703b_pwrtrack_set()
1573 		rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);  in rtw8703b_pwrtrack_set()
1578 	else if (final_cck_swing_index < 0)  in rtw8703b_pwrtrack_set()
1579 		rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0,  in rtw8703b_pwrtrack_set()
1582 		rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);  in rtw8703b_pwrtrack_set()
1596 	if (rtwdev->efuse.thermal_meter[0] == 0xff)  in rtw8703b_phy_pwrtrack()
1599 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);  in rtw8703b_phy_pwrtrack()
1618 	for (path = 0; path < rtwdev->hal.rf_path_num; path++) {  in rtw8703b_phy_pwrtrack()
1643 	if (efuse->power_track_type != 0) {  in rtw8703b_pwr_track()
1650 			     GENMASK(17, 16), 0x03);  in rtw8703b_pwr_track()
1673 	coex_rfe->ant_switch_polarity = 0;  in rtw8703b_coex_set_rfe_type()
1680 	rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);  in rtw8703b_coex_set_rfe_type()
1681 	rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8703b_coex_set_rfe_type()
1682 	rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8703b_coex_set_rfe_type()
1694 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1699 	0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1704 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1709 	0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1714 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1719 	0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1724 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1729 	0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1734 	0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3,
1735 	-4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1
1739 	0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1,
1757 	[0] = { .phy_pg_tbl	= &rtw8703b_bb_pg_tbl,
1764 	{0xffffffff, 0xffffffff}, /* case-0 */
1765 	{0x55555555, 0x55555555},
1766 	{0x66555555, 0x66555555},
1767 	{0xaaaaaaaa, 0xaaaaaaaa},
1768 	{0x5a5a5a5a, 0x5a5a5a5a},
1769 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1770 	{0x6a5a5555, 0xaaaaaaaa},
1771 	{0x6a5a56aa, 0x6a5a56aa},
1772 	{0x6a5a5a5a, 0x6a5a5a5a},
1773 	{0x66555555, 0x5a5a5a5a},
1774 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1775 	{0x66555555, 0x6a5a5aaa},
1776 	{0x66555555, 0x5a5a5aaa},
1777 	{0x66555555, 0x6aaa5aaa},
1778 	{0x66555555, 0xaaaa5aaa},
1779 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1780 	{0xffff55ff, 0xfafafafa},
1781 	{0xffff55ff, 0x6afa5afa},
1782 	{0xaaffffaa, 0xfafafafa},
1783 	{0xaa5555aa, 0x5a5a5a5a},
1784 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1785 	{0xaa5555aa, 0xaaaaaaaa},
1786 	{0xffffffff, 0x5a5a5a5a},
1787 	{0xffffffff, 0x5a5a5a5a},
1788 	{0xffffffff, 0x55555555},
1789 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1790 	{0x55555555, 0x5a5a5a5a},
1791 	{0x55555555, 0xaaaaaaaa},
1792 	{0x55555555, 0x6a5a6a5a},
1793 	{0x66556655, 0x66556655},
1794 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1795 	{0xffffffff, 0x5aaa5aaa},
1796 	{0x56555555, 0x5a5a5aaa},
1801 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1802 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1803 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1804 	{ {0x61, 0x30, 0x03, 0x11, 0x11} },
1805 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1806 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1807 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1808 	{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
1809 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1810 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1811 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1812 	{ {0x61, 0x08, 0x03, 0x11, 0x14} },
1813 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1814 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1815 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1816 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1817 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1818 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1819 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1820 	{ {0x51, 0x20, 0x03, 0x10, 0x50} },
1821 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1822 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1823 	{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
1824 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1825 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1826 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1827 	{ {0x51, 0x08, 0x03, 0x10, 0x50} },
1828 	{ {0x61, 0x08, 0x03, 0x11, 0x11} },
1855 	 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only
1899 	.csi_buf_pg_num = 0,
1900 	.dig_min = 0x20,
1905 	.max_power_index = 0x3f,
1915 	.lps_deep_mode_supported = 0,
1917 	.sys_func_en = 0xFD,
1929 	.rf_sipi_addr = {0x840, 0x844},
1952 	.coex_para_ver = 0x0133ed6a,
1953 	.bt_desired_ver = 0x1c,
1969 	.table_nsant_num = 0,
1973 	.tdma_nsant_num = 0,
1978 	.bt_afh_span_bw20 = 0x20,
1979 	.bt_afh_span_bw40 = 0x30,
1986 	 * (by address, 0x0067), comment: "0x67[0] = 0 to disable
1993 	.coex_info_hw_regs_num = 0,