Lines Matching +full:bit0 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
46 /* 0xc00[7:0] = 4 turn off 3-wire */}, \
49 /* 0xe00[7:0] = 4 turn off 3-wire */}, \
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
61 /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/}, \
82 /* gpio 0~7 output same value as input ?? */}, \
85 /* gpio0~7 output mode */}, \
88 /* 0x47[7:0] = 00 gpio mode */}, \
94 /*0x14[7] = 1 turn on ZCD */}, \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
120 /*0x14[7] = 0 turn off ZCD */}, \
123 /* gpio0~7 input mode */}, \
144 /* gpio 0~7 output same value as input ?? */}, \
147 /* gpio0~7 output mode */}, \
150 /* 0x47[7:0] = 00 gpio mode */}, \
153 /*0x14[7] = 1 turn on ZCD */}, \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
185 /*0x14[7] = 0 turn off ZCD */}, \
194 /* gpio0~7 input mode */}, \
242 /* 0xc00[7:0] = 4 turn off 3-wire */}, \
245 /* 0xe00[7:0] = 4 turn off 3-wire */}, \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
283 /*Polling 0x109[7]=0 TSF in 40M*/}, \
286 /*. 0x29[7:6] = 2b'00 enable BB clock*/}, \
292 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/}, \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
337 /* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
339 * 0: POFF--Power Off
340 * 1: PDN--Power Down
341 * 2: CARDEMU--Card Emulation
342 * 3: ACT--Active Mode
343 * 4: LPS--Low Power State
344 * 5: SUS--Suspend
371 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
389 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
395 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
398 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
407 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
410 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
413 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
432 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
450 /*0x1F[7:0] = 0 turn off RF*/}, \
452 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
470 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
486 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/}, \
491 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
502 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
526 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
532 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
543 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
549 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
568 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/}, \
570 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
601 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
640 /*Polling 0x109[7]=0 TSF in 40M*/},\
643 /*. 0x29[7:6] = 2b'00 enable BB clock*/},\
649 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/},\
651 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \