40 	if (bitmask != MASKDWORD) {  in rtl8723_phy_set_bb_reg()
71 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in rtl8723_phy_rf_serial_read()
75 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in rtl8723_phy_rf_serial_read()
78 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in rtl8723_phy_rf_serial_read()
80 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in rtl8723_phy_rf_serial_read()
81 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in rtl8723_phy_rf_serial_read()
120 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in rtl8723_phy_rf_serial_write()
279 					  MASKDWORD) >> 22) & 0x3FF;  in rtl8723_phy_path_a_fill_iqk_matrix()
315 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in rtl8723_save_adda_registers()
338 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);  in rtl8723_phy_reload_adda_registers()
365 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);  in rtl8723_phy_path_adda_on()
367 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
372 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
376 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
397 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);  in rtl8723_phy_path_a_standby()
398 	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);  in rtl8723_phy_path_a_standby()
399 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in rtl8723_phy_path_a_standby()
408 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);  in rtl8723_phy_pi_mode_switch()
409 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);  in rtl8723_phy_pi_mode_switch()