Lines Matching +full:0 +full:x7000000

7 #define TXPKT_BUF_SELECT			0x69
8 #define RXPKT_BUF_SELECT			0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS		0x0
11 #define REG_SYS_ISO_CTRL			0x0000
12 #define REG_SYS_FUNC_EN				0x0002
13 #define REG_APS_FSMCO				0x0004
14 #define REG_SYS_CLKR				0x0008
15 #define REG_9346CR				0x000A
16 #define REG_EE_VPD				0x000C
17 #define REG_AFE_MISC				0x0010
18 #define REG_SPS0_CTRL				0x0011
19 #define REG_SPS_OCP_CFG				0x0018
20 #define REG_RSV_CTRL				0x001C
21 #define REG_RF_CTRL				0x001F
22 #define REG_LDOA15_CTRL				0x0020
23 #define REG_LDOV12D_CTRL			0x0021
24 #define REG_LDOHCI12_CTRL			0x0022
25 #define REG_LPLDO_CTRL				0x0023
26 #define REG_AFE_XTAL_CTRL			0x0024
28 #define REG_AFE_LDO_CTRL			0x0027
29 #define REG_AFE_PLL_CTRL			0x0028
30 #define REG_MAC_PHY_CTRL			0x002c
31 #define REG_EFUSE_CTRL				0x0030
32 #define REG_EFUSE_TEST				0x0034
33 #define REG_PWR_DATA				0x0038
34 #define REG_CAL_TIMER				0x003C
35 #define REG_ACLK_MON				0x003E
36 #define REG_GPIO_MUXCFG				0x0040
37 #define REG_GPIO_IO_SEL				0x0042
38 #define REG_MAC_PINMUX_CFG			0x0043
39 #define REG_GPIO_PIN_CTRL			0x0044
40 #define REG_GPIO_INTM				0x0048
41 #define REG_LEDCFG0				0x004C
42 #define REG_LEDCFG1				0x004D
43 #define REG_LEDCFG2				0x004E
44 #define REG_LEDCFG3				0x004F
45 #define REG_FSIMR				0x0050
46 #define REG_FSISR				0x0054
47 #define REG_HSIMR				0x0058
48 #define REG_HSISR				0x005c
49 #define REG_GPIO_PIN_CTRL_2			0x0060
50 #define REG_GPIO_IO_SEL_2			0x0062
51 #define REG_MULTI_FUNC_CTRL			0x0068
52 #define REG_GPIO_OUTPUT				0x006c
53 #define REG_AFE_XTAL_CTRL_EXT			0x0078
54 #define REG_XCK_OUT_CTRL			0x007c
55 #define REG_MCUFWDL				0x0080
56 #define REG_WOL_EVENT				0x0081
57 #define REG_MCUTSTCFG				0x0084
59 #define REG_HIMR				0x00B0
60 #define REG_HISR				0x00B4
61 #define REG_HIMRE				0x00B8
62 #define REG_HISRE				0x00BC
63 #define REG_PMC_DBG_CTRL2			0x00CC
65 #define REG_EFUSE_ACCESS			0x00CF
67 #define REG_BIST_SCAN				0x00D0
68 #define REG_BIST_RPT				0x00D4
69 #define REG_BIST_ROM_RPT			0x00D8
70 #define REG_USB_SIE_INTF			0x00E0
71 #define REG_PCIE_MIO_INTF			0x00E4
72 #define REG_PCIE_MIO_INTD			0x00E8
73 #define REG_HPON_FSM				0x00EC
74 #define REG_SYS_CFG				0x00F0
75 #define REG_GPIO_OUTSTS				0x00F4
76 #define REG_MAC_PHY_CTRL_NORMAL			0x00F8
77 #define REG_SYS_CFG1				0x00FC
78 #define REG_ROM_VERSION				0x00FD
80 #define REG_CR					0x0100
81 #define REG_PBP					0x0104
82 #define REG_PKT_BUFF_ACCESS_CTRL		0x0106
83 #define REG_TRXDMA_CTRL				0x010C
84 #define REG_TRXFF_BNDY				0x0114
85 #define REG_TRXFF_STATUS			0x0118
86 #define REG_RXFF_PTR				0x011C
88 #define REG_CPWM				0x012F
89 #define REG_FWIMR				0x0130
90 #define REG_FWISR				0x0134
91 #define REG_PKTBUF_DBG_CTRL			0x0140
92 #define REG_PKTBUF_DBG_DATA_L			0x0144
93 #define REG_PKTBUF_DBG_DATA_H			0x0148
96 #define REG_TC0_CTRL				0x0150
97 #define REG_TC1_CTRL				0x0154
98 #define REG_TC2_CTRL				0x0158
99 #define REG_TC3_CTRL				0x015C
100 #define REG_TC4_CTRL				0x0160
101 #define REG_TCUNIT_BASE				0x0164
102 #define REG_MBIST_START				0x0174
103 #define REG_MBIST_DONE				0x0178
104 #define REG_MBIST_FAIL				0x017C
105 #define REG_32K_CTRL				0x0194
106 #define REG_C2HEVT_MSG_NORMAL			0x01A0
107 #define REG_C2HEVT_CLEAR			0x01AF
108 #define REG_C2HEVT_MSG_TEST			0x01B8
109 #define REG_MCUTST_1				0x01c0
110 #define REG_FMETHR				0x01C8
111 #define REG_HMETFR				0x01CC
112 #define REG_HMEBOX_0				0x01D0
113 #define REG_HMEBOX_1				0x01D4
114 #define REG_HMEBOX_2				0x01D8
115 #define REG_HMEBOX_3				0x01DC
117 #define REG_LLT_INIT				0x01E0
118 #define REG_BB_ACCEESS_CTRL			0x01E8
119 #define REG_BB_ACCESS_DATA			0x01EC
121 #define REG_HMEBOX_EXT_0			0x01F0
122 #define REG_HMEBOX_EXT_1			0x01F4
123 #define REG_HMEBOX_EXT_2			0x01F8
124 #define REG_HMEBOX_EXT_3			0x01FC
126 #define REG_RQPN				0x0200
127 #define REG_FIFOPAGE				0x0204
128 #define REG_TDECTRL				0x0208
129 #define REG_TXDMA_OFFSET_CHK			0x020C
130 #define REG_TXDMA_STATUS			0x0210
131 #define REG_RQPN_NPQ				0x0214
133 #define REG_RXDMA_AGG_PG_TH			0x0280
135 #define REG_FW_UPD_RDPTR			0x0284
137 #define REG_RXDMA_CONTROL			0x0286
139 #define REG_RXPKT_NUM				0x0287
141 #define	REG_PCIE_CTRL_REG			0x0300
142 #define	REG_INT_MIG				0x0304
143 #define	REG_BCNQ_DESA				0x0308
144 #define	REG_HQ_DESA				0x0310
145 #define	REG_MGQ_DESA				0x0318
146 #define	REG_VOQ_DESA				0x0320
147 #define	REG_VIQ_DESA				0x0328
148 #define	REG_BEQ_DESA				0x0330
149 #define	REG_BKQ_DESA				0x0338
150 #define	REG_RX_DESA				0x0340
152 #define	REG_DBI_WDATA				0x0348
153 #define	REG_DBI_RDATA				0x034C
154 #define	REG_DBI_CTRL				0x0350
155 #define	REG_DBI_ADDR				0x0350
156 #define	REG_DBI_FLAG				0x0352
157 #define	REG_MDIO_WDATA				0x0354
158 #define	REG_MDIO_RDATA				0x0356
159 #define	REG_MDIO_CTL				0x0358
160 #define	REG_DBG_SEL				0x0360
161 #define	REG_PCIE_HRPWM				0x0361
162 #define	REG_PCIE_HCPWM				0x0363
163 #define	REG_UART_CTRL				0x0364
164 #define	REG_WATCH_DOG				0x0368
165 #define	REG_UART_TX_DESA			0x0370
166 #define	REG_UART_RX_DESA			0x0378
168 #define	REG_HDAQ_DESA_NODEF			0x0000
169 #define	REG_CMDQ_DESA_NODEF			0x0000
171 #define REG_VOQ_INFORMATION			0x0400
172 #define REG_VIQ_INFORMATION			0x0404
173 #define REG_BEQ_INFORMATION			0x0408
174 #define REG_BKQ_INFORMATION			0x040C
175 #define REG_MGQ_INFORMATION			0x0410
176 #define REG_HGQ_INFORMATION			0x0414
177 #define REG_BCNQ_INFORMATION			0x0418
178 #define REG_TXPKT_EMPTY				0x041A
180 #define REG_CPU_MGQ_INFORMATION			0x041C
181 #define REG_FWHW_TXQ_CTRL			0x0420
182 #define REG_HWSEQ_CTRL				0x0423
183 #define REG_TXPKTBUF_BCNQ_BDNY			0x0424
184 #define REG_TXPKTBUF_MGQ_BDNY			0x0425
185 #define REG_MULTI_BCNQ_EN			0x0426
186 #define REG_MULTI_BCNQ_OFFSET			0x0427
187 #define REG_SPEC_SIFS				0x0428
188 #define REG_RL					0x042A
189 #define REG_DARFRC				0x0430
190 #define REG_RARFRC				0x0438
191 #define REG_RRSR				0x0440
192 #define REG_ARFR0				0x0444
193 #define REG_ARFR1				0x044C
194 #define REG_AMPDU_MAX_TIME			0x0456
195 #define REG_AGGLEN_LMT				0x0458
196 #define REG_AMPDU_MIN_SPACE			0x045C
197 #define REG_TXPKTBUF_WMAC_LBK_BF_HD		0x045D
198 #define REG_FAST_EDCA_CTRL			0x0460
199 #define REG_RD_RESP_PKT_TH			0x0463
200 #define REG_INIRTS_RATE_SEL			0x0480
201 #define REG_INIDATA_RATE_SEL			0x0484
202 #define REG_POWER_STATUS			0x04A4
203 #define REG_POWER_STAGE1			0x04B4
204 #define REG_POWER_STAGE2			0x04B8
205 #define REG_PKT_LIFE_TIME			0x04C0
206 #define REG_STBC_SETTING			0x04C4
207 #define REG_HT_SINGLE_AMPDU			0x04C7
209 #define REG_PROT_MODE_CTRL			0x04C8
210 #define REG_MAX_AGGR_NUM			0x04CA
211 #define REG_BAR_MODE_CTRL			0x04CC
212 #define REG_RA_TRY_RATE_AGG_LMT			0x04CF
213 #define REG_EARLY_MODE_CONTROL			0x04D0
214 #define REG_NQOS_SEQ				0x04DC
215 #define REG_QOS_SEQ				0x04DE
216 #define REG_NEED_CPU_HANDLE			0x04E0
217 #define REG_PKT_LOSE_RPT			0x04E1
218 #define REG_PTCL_ERR_STATUS			0x04E2
219 #define REG_TX_RPT_CTRL				0x04EC
220 #define REG_TX_RPT_TIME				0x04F0
221 #define REG_DUMMY				0x04FC
223 #define REG_EDCA_VO_PARAM			0x0500
224 #define REG_EDCA_VI_PARAM			0x0504
225 #define REG_EDCA_BE_PARAM			0x0508
226 #define REG_EDCA_BK_PARAM			0x050C
227 #define REG_BCNTCFG				0x0510
228 #define REG_PIFS				0x0512
229 #define REG_RDG_PIFS				0x0513
230 #define REG_SIFS_CTX				0x0514
231 #define REG_SIFS_TRX				0x0516
232 #define REG_AGGR_BREAK_TIME			0x051A
233 #define REG_SLOT				0x051B
234 #define REG_TX_PTCL_CTRL			0x0520
235 #define REG_TXPAUSE				0x0522
236 #define REG_DIS_TXREQ_CLR			0x0523
237 #define REG_RD_CTRL				0x0524
238 #define REG_TBTT_PROHIBIT			0x0540
239 #define REG_RD_NAV_NXT				0x0544
240 #define REG_NAV_PROT_LEN			0x0546
241 #define REG_BCN_CTRL				0x0550
242 #define REG_MBID_NUM				0x0552
243 #define REG_DUAL_TSF_RST			0x0553
244 #define REG_BCN_INTERVAL			0x0554
245 #define REG_MBSSID_BCN_SPACE			0x0554
246 #define REG_DRVERLYINT				0x0558
247 #define REG_BCNDMATIM				0x0559
248 #define REG_ATIMWND				0x055A
249 #define REG_USTIME_TSF				0x055C
250 #define REG_BCN_MAX_ERR				0x055D
251 #define REG_RXTSF_OFFSET_CCK			0x055E
252 #define REG_RXTSF_OFFSET_OFDM			0x055F
253 #define REG_TSFTR				0x0560
254 #define REG_INIT_TSFTR				0x0564
255 #define REG_SECONDARY_CCA_CTRL			0x0577
256 #define REG_PSTIMER				0x0580
257 #define REG_TIMER0				0x0584
258 #define REG_TIMER1				0x0588
259 #define REG_ACMHWCTRL				0x05C0
260 #define REG_ACMRSTCTRL				0x05C1
261 #define REG_ACMAVG				0x05C2
262 #define REG_VO_ADMTIME				0x05C4
263 #define REG_VI_ADMTIME				0x05C6
264 #define REG_BE_ADMTIME				0x05C8
265 #define REG_EDCA_RANDOM_GEN			0x05CC
266 #define REG_SCH_TXCMD				0x05D0
268 #define REG_APSD_CTRL				0x0600
269 #define REG_BWOPMODE				0x0603
270 #define REG_TCR					0x0604
271 #define REG_RCR					0x0608
272 #define REG_RX_PKT_LIMIT			0x060C
273 #define REG_RX_DLK_TIME				0x060D
274 #define REG_RX_DRVINFO_SZ			0x060F
276 #define REG_MACID				0x0610
277 #define REG_BSSID				0x0618
278 #define REG_MAR					0x0620
279 #define REG_MBIDCAMCFG				0x0628
281 #define REG_USTIME_EDCA				0x0638
282 #define REG_MAC_SPEC_SIFS			0x063A
283 #define REG_RESP_SIFS_CCK			0x063C
284 #define REG_RESP_SIFS_OFDM			0x063E
285 #define REG_ACKTO				0x0640
286 #define REG_CTS2TO				0x0641
287 #define REG_EIFS				0x0642
289 #define REG_NAV_CTRL				0x0650
290 #define	REG_NAV_UPPER				0x0652
291 #define REG_BACAMCMD				0x0654
292 #define REG_BACAMCONTENT			0x0658
293 #define REG_LBDLY				0x0660
294 #define REG_FWDLY				0x0661
295 #define REG_RXERR_RPT				0x0664
296 #define REG_TRXPTCL_CTL				0x0668
298 #define REG_CAMCMD				0x0670
299 #define REG_CAMWRITE				0x0674
300 #define REG_CAMREAD				0x0678
301 #define REG_CAMDBG				0x067C
302 #define REG_SECCFG				0x0680
304 #define REG_WOW_CTRL				0x0690
305 #define REG_PSSTATUS				0x0691
306 #define REG_PS_RX_INFO				0x0692
307 #define REG_UAPSD_TID				0x0693
308 #define REG_LPNAV_CTRL				0x0694
309 #define REG_WKFMCAM_NUM				0x0698
310 #define REG_WKFMCAM_RWD				0x069C
311 #define REG_RXFLTMAP0				0x06A0
312 #define REG_RXFLTMAP1				0x06A2
313 #define REG_RXFLTMAP2				0x06A4
314 #define REG_BCN_PSR_RPT				0x06A8
315 #define REG_CALB32K_CTRL			0x06AC
316 #define REG_PKT_MON_CTRL			0x06B4
317 #define REG_BT_COEX_TABLE			0x06C0
318 #define REG_WMAC_RESP_TXINFO			0x06D8
320 #define REG_USB_INFO				0xFE17
321 #define REG_USB_SPECIAL_OPTION			0xFE55
322 #define REG_USB_DMA_AGG_TO			0xFE5B
323 #define REG_USB_AGG_TO				0xFE5C
324 #define REG_USB_AGG_TH				0xFE5D
326 #define REG_TEST_USB_TXQS			0xFE48
327 #define REG_TEST_SIE_VID			0xFE60
328 #define REG_TEST_SIE_PID			0xFE62
329 #define REG_TEST_SIE_OPTIONAL			0xFE64
330 #define REG_TEST_SIE_CHIRP_K			0xFE65
331 #define REG_TEST_SIE_PHY			0xFE66
332 #define REG_TEST_SIE_MAC_ADDR			0xFE70
333 #define REG_TEST_SIE_STRING			0xFE80
335 #define REG_NORMAL_SIE_VID			0xFE60
336 #define REG_NORMAL_SIE_PID			0xFE62
337 #define REG_NORMAL_SIE_OPTIONAL			0xFE64
338 #define REG_NORMAL_SIE_EP			0xFE65
339 #define REG_NORMAL_SIE_PHY			0xFE68
340 #define REG_NORMAL_SIE_MAC_ADDR			0xFE70
341 #define REG_NORMAL_SIE_STRING			0xFE80
356 #define	UNUSED_REGISTER			0x1BF
362 #define	INVALID_BBRF_VALUE		0x12345678
364 #define	MAX_MSS_DENSITY_2T		0x13
365 #define	MAX_MSS_DENSITY_1T		0x0A
373 #define	GPIOSEL_GPIO			0
381 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
382 #define	HSIMR_GPIO12_0_INT_EN			BIT(0)
388 /*  8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
389 #define	HSISR_GPIO12_0_INT			BIT(0)
395 #define	MSR_NOLINK				0x00
396 #define	MSR_ADHOC				0x01
397 #define	MSR_INFRA				0x02
398 #define	MSR_AP					0x03
402 #define	RRSR_RSC_BW_40M				0x600000
403 #define	RRSR_RSC_UPSUBCHNL			0x400000
404 #define	RRSR_RSC_LOWSUBCHNL			0x200000
405 #define	RRSR_SHORT				0x800000
406 #define	RRSR_1M					BIT(0)
428 #define	RATR_1M					0x00000001
429 #define	RATR_2M					0x00000002
430 #define	RATR_55M				0x00000004
431 #define	RATR_11M				0x00000008
432 #define	RATR_6M					0x00000010
433 #define	RATR_9M					0x00000020
434 #define	RATR_12M				0x00000040
435 #define	RATR_18M				0x00000080
436 #define	RATR_24M				0x00000100
437 #define	RATR_36M				0x00000200
438 #define	RATR_48M				0x00000400
439 #define	RATR_54M				0x00000800
440 #define	RATR_MCS0				0x00001000
441 #define	RATR_MCS1				0x00002000
442 #define	RATR_MCS2				0x00004000
443 #define	RATR_MCS3				0x00008000
444 #define	RATR_MCS4				0x00010000
445 #define	RATR_MCS5				0x00020000
446 #define	RATR_MCS6				0x00040000
447 #define	RATR_MCS7				0x00080000
448 #define	RATR_MCS8				0x00100000
449 #define	RATR_MCS9				0x00200000
450 #define	RATR_MCS10				0x00400000
451 #define	RATR_MCS11				0x00800000
452 #define	RATR_MCS12				0x01000000
453 #define	RATR_MCS13				0x02000000
454 #define	RATR_MCS14				0x04000000
455 #define	RATR_MCS15				0x08000000
457 #define RATE_1M					BIT(0)
498 #define	BW_OPMODE_11J				BIT(0)
501 #define	CAM_NOTVALID				0x0000
504 #define	CAM_NONE				0x0
505 #define	CAM_WEP40				0x01
506 #define	CAM_TKIP				0x02
507 #define	CAM_AES					0x04
508 #define	CAM_WEP104				0x05
514 #define	CAM_READ				0x00000000
517 #define	SCR_USEDK				0x01
518 #define	SCR_TXSEC_ENABLE			0x02
519 #define	SCR_RXSEC_ENABLE			0x04
521 #define	WOW_PMEN				BIT(0)
530 #define	IMR_DISABLED				0x0
531 /* IMR DW0(0x0060-0063) Bit 0-31 */
547 #define	IMR_BCNDMAINT0		BIT(20)	/* Beacon DMA Interrupt 0 */
575 #define	IMR_ROK			BIT(0)	/* Receive DMA OK */
577 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
610 #define	EEPROM_DEFAULT_TSSI			0x0
611 #define EEPROM_DEFAULT_TXPOWERDIFF		0x0
612 #define EEPROM_DEFAULT_CRYSTALCAP		0x5
613 #define EEPROM_DEFAULT_BOARDTYPE		0x02
614 #define EEPROM_DEFAULT_TXPOWER			0x1010
615 #define	EEPROM_DEFAULT_HT2T_TXPWR		0x10
617 #define	EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF	0x3
618 #define	EEPROM_DEFAULT_THERMALMETER		0x18
619 #define	EEPROM_DEFAULT_ANTTXPOWERDIFF		0x0
620 #define	EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP	0x5
621 #define	EEPROM_DEFAULT_TXPOWERLEVEL		0x22
622 #define	EEPROM_DEFAULT_HT40_2SDIFF		0x0
624 #define	EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF	0x3
625 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET	0
626 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET	0
628 #define RF_OPTION1				0x79
629 #define RF_OPTION2				0x7A
630 #define RF_OPTION3				0x7B
631 #define EEPROM_RF_BT_SETTING_8723B		0xC3
633 #define EEPROM_DEFAULT_PID			0x1234
634 #define EEPROM_DEFAULT_VID			0x5678
635 #define EEPROM_DEFAULT_CUSTOMERID		0xAB
636 #define EEPROM_DEFAULT_SUBCUSTOMERID		0xCD
637 #define EEPROM_DEFAULT_VERSION			0
639 #define	EEPROM_CHANNEL_PLAN_FCC			0x0
640 #define	EEPROM_CHANNEL_PLAN_IC			0x1
641 #define	EEPROM_CHANNEL_PLAN_ETSI		0x2
642 #define	EEPROM_CHANNEL_PLAN_SPAIN		0x3
643 #define	EEPROM_CHANNEL_PLAN_FRANCE		0x4
644 #define	EEPROM_CHANNEL_PLAN_MKK			0x5
645 #define	EEPROM_CHANNEL_PLAN_MKK1		0x6
646 #define	EEPROM_CHANNEL_PLAN_ISRAEL		0x7
647 #define	EEPROM_CHANNEL_PLAN_TELEC		0x8
648 #define	EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN	0x9
649 #define	EEPROM_CHANNEL_PLAN_WORLD_WIDE_13	0xA
650 #define	EEPROM_CHANNEL_PLAN_NCC			0xB
651 #define	EEPROM_CHANNEL_PLAN_BY_HW_MASK		0x80
653 #define EEPROM_CID_DEFAULT			0x0
654 #define EEPROM_CID_TOSHIBA			0x4
655 #define	EEPROM_CID_CCX				0x10
656 #define	EEPROM_CID_QMI				0x0D
657 #define EEPROM_CID_WHQL				0xFE
659 #define	RTL8723BE_EEPROM_ID			0x8129
661 #define EEPROM_HPON				0x02
662 #define EEPROM_CLK				0x06
663 #define EEPROM_TESTR				0x08
665 #define EEPROM_TXPOWERCCK			0x10
666 #define	EEPROM_TXPOWERHT40_1S			0x16
667 #define EEPROM_TXPOWERHT20DIFF			0x1B
668 #define EEPROM_TXPOWER_OFDMDIFF			0x1B
670 #define	EEPROM_TX_PWR_INX			0x10
672 #define	EEPROM_CHANNELPLAN			0xB8
673 #define	EEPROM_XTAL_8723BE			0xB9
674 #define	EEPROM_THERMAL_METER_88E		0xBA
675 #define	EEPROM_IQK_LCK_88E			0xBB
677 #define	EEPROM_RF_BOARD_OPTION_88E		0xC1
678 #define	EEPROM_RF_FEATURE_OPTION_88E		0xC2
679 #define	EEPROM_RF_BT_SETTING_88E		0xC3
680 #define	EEPROM_VERSION				0xC4
681 #define	EEPROM_CUSTOMER_ID			0xC5
682 #define	EEPROM_RF_ANTENNA_OPT_88E		0xC9
684 #define	EEPROM_MAC_ADDR				0xD0
685 #define EEPROM_VID				0xD6
686 #define EEPROM_DID				0xD8
687 #define EEPROM_SVID				0xDA
688 #define EEPROM_SMID				0xDC
696 #define	STOPBK					BIT(0)
720 #define	RCR_AAP					BIT(0)
724 #define RSV_CTRL				0x001C
725 #define RD_CTRL					0x0524
727 #define REG_USB_INFO				0xFE17
728 #define REG_USB_SPECIAL_OPTION			0xFE55
729 #define REG_USB_DMA_AGG_TO			0xFE5B
730 #define REG_USB_AGG_TO				0xFE5C
731 #define REG_USB_AGG_TH				0xFE5D
733 #define REG_USB_VID				0xFE60
734 #define REG_USB_PID				0xFE62
735 #define REG_USB_OPTIONAL			0xFE64
736 #define REG_USB_CHIRP_K				0xFE65
737 #define REG_USB_PHY				0xFE66
738 #define REG_USB_MAC_ADDR			0xFE70
739 #define REG_USB_HRPWM				0xFE58
740 #define REG_USB_HCPWM				0xFE57
744 #define ISO_MD2PP				BIT(0)
758 #define FEN_BBRSTB				BIT(0)
775 #define PFM_LDALL				BIT(0)
802 #define ANAD16V_EN				BIT(0)
817 #define AFE_BGEN				BIT(0)
821 #define WLOCK_ALL				BIT(0)
830 #define RF_EN					BIT(0)
834 #define LDA15_EN				BIT(0)
838 #define _LDA15_VOADJ(x)				(((x) & 0x7) << 4)
840 #define LDV12_EN				BIT(0)
844 #define _LDV12_VADJ(x)				(((x) & 0xF) << 4)
846 #define XTAL_EN					BIT(0)
848 #define _XTAL_BOSC(x)				(((x) & 0x3) << 2)
849 #define _XTAL_CADJ(x)				(((x) & 0xF) << 4)
851 #define _XTAL_USB_DRV(x)			(((x) & 0x3) << 9)
853 #define _XTAL_AFE_DRV(x)			(((x) & 0x3) << 12)
855 #define _XTAL_RF_DRV(x)				(((x) & 0x3) << 15)
857 #define _XTAL_DIG_DRV(x)			(((x) & 0x3) << 18)
859 #define _XTAL_BT_DRV(x)				(((x) & 0x3) << 21)
860 #define _XTAL_GPIO(x)				(((x) & 0x7) << 23)
867 #define APLL_EN					BIT(0)
874 #define APLL_REF_CLK_13MHZ			0x1
875 #define APLL_REF_CLK_19_2MHZ			0x2
876 #define APLL_REF_CLK_20MHZ			0x3
877 #define APLL_REF_CLK_25MHZ			0x4
878 #define APLL_REF_CLK_26MHZ			0x5
879 #define APLL_REF_CLK_38_4MHZ			0x6
880 #define APLL_REF_CLK_40MHZ			0x7
893 #define RSM_EN					BIT(0)
913 #define MCUFWDL_EN				BIT(0)
922 #define XCLK_VLD				BIT(0)
941 #define CHIP_VER_RTL_MASK			0xF000
946 #define HCI_TXDMA_EN				BIT(0)
957 #define _NETTYPE(x)				(((x) & 0x3) << 16)
958 #define MASK_NETTYPE				0x30000
959 #define NT_NO_LINK				0x0
960 #define NT_LINK_AD_HOC				0x1
961 #define NT_LINK_AP				0x2
962 #define NT_AS_AP				0x3
964 #define _LBMODE(x)				(((x) & 0xF) << 24)
965 #define MASK_LBMODE				0xF000000
966 #define LOOPBACK_NORMAL				0x0
967 #define LOOPBACK_IMMEDIATELY			0xB
968 #define LOOPBACK_MAC_DELAY			0x3
969 #define LOOPBACK_PHY				0x1
970 #define LOOPBACK_DMA				0x7
972 #define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
973 #define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
974 #define _PSRX_MASK				0xF
975 #define _PSTX_MASK				0xF0
979 #define PBP_64					0x0
980 #define PBP_128					0x1
981 #define PBP_256					0x2
982 #define PBP_512					0x3
983 #define PBP_1024				0x4
985 #define RXDMA_ARBBW_EN				BIT(0)
995 #define HQSEL_VOQ				BIT(0)
1002 #define _TXDMA_HIQ_MAP(x)			(((x)&0x3) << 14)
1003 #define _TXDMA_MGQ_MAP(x)			(((x)&0x3) << 12)
1004 #define _TXDMA_BKQ_MAP(x)			(((x)&0x3) << 10)
1005 #define _TXDMA_BEQ_MAP(x)			(((x)&0x3) << 8)
1006 #define _TXDMA_VIQ_MAP(x)			(((x)&0x3) << 6)
1007 #define _TXDMA_VOQ_MAP(x)			(((x)&0x3) << 4)
1013 #define _LLT_NO_ACTIVE				0x0
1014 #define _LLT_WRITE_ACCESS			0x1
1015 #define _LLT_READ_ACCESS			0x2
1017 #define _LLT_INIT_DATA(x)			((x) & 0xFF)
1018 #define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
1019 #define _LLT_OP(x)				(((x) & 0x3) << 30)
1020 #define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
1026 #define _HPQ(x)					((x) & 0xFF)
1027 #define _LPQ(x)					(((x) & 0xFF) << 8)
1028 #define _PUBQ(x)				(((x) & 0xFF) << 16)
1029 #define _NPQ(x)					((x) & 0xFF)
1036 #define BCN_HEAD(x)				(((x) & 0xFF) << 8)
1037 #define	BCN_HEAD_MASK				0xFF00
1040 #define BLK_DESC_NUM_MASK			0xF
1046 #define _INIRTSMCS_SEL(x)			((x) & 0x3F)
1048 #define _SPEC_SIFS_CCK(x)			((x) & 0xFF)
1049 #define _SPEC_SIFS_OFDM(x)			(((x) & 0xFF) << 8)
1051 #define RATE_REG_BITMAP_ALL			0xFFFFF
1053 #define _RRSC_BITMAP(x)				((x) & 0xFFFFF)
1055 #define _RRSR_RSC(x)				(((x) & 0x3) << 21)
1056 #define RRSR_RSC_RESERVED			0x0
1057 #define RRSR_RSC_UPPER_SUBCHANNEL		0x1
1058 #define RRSR_RSC_LOWER_SUBCHANNEL		0x2
1059 #define RRSR_RSC_DUPLICATE_MODE			0x3
1063 #define _AGGLMT_MCS0(x)				((x) & 0xF)
1064 #define _AGGLMT_MCS1(x)				(((x) & 0xF) << 4)
1065 #define _AGGLMT_MCS2(x)				(((x) & 0xF) << 8)
1066 #define _AGGLMT_MCS3(x)				(((x) & 0xF) << 12)
1067 #define _AGGLMT_MCS4(x)				(((x) & 0xF) << 16)
1068 #define _AGGLMT_MCS5(x)				(((x) & 0xF) << 20)
1069 #define _AGGLMT_MCS6(x)				(((x) & 0xF) << 24)
1070 #define _AGGLMT_MCS7(x)				(((x) & 0xF) << 28)
1073 #define	RETRY_LIMIT_LONG_SHIFT			0
1075 #define _DARF_RC1(x)				((x) & 0x1F)
1076 #define _DARF_RC2(x)				(((x) & 0x1F) << 8)
1077 #define _DARF_RC3(x)				(((x) & 0x1F) << 16)
1078 #define _DARF_RC4(x)				(((x) & 0x1F) << 24)
1079 #define _DARF_RC5(x)				((x) & 0x1F)
1080 #define _DARF_RC6(x)				(((x) & 0x1F) << 8)
1081 #define _DARF_RC7(x)				(((x) & 0x1F) << 16)
1082 #define _DARF_RC8(x)				(((x) & 0x1F) << 24)
1084 #define _RARF_RC1(x)				((x) & 0x1F)
1085 #define _RARF_RC2(x)				(((x) & 0x1F) << 8)
1086 #define _RARF_RC3(x)				(((x) & 0x1F) << 16)
1087 #define _RARF_RC4(x)				(((x) & 0x1F) << 24)
1088 #define _RARF_RC5(x)				((x) & 0x1F)
1089 #define _RARF_RC6(x)				(((x) & 0x1F) << 8)
1090 #define _RARF_RC7(x)				(((x) & 0x1F) << 16)
1091 #define _RARF_RC8(x)				(((x) & 0x1F) << 24)
1096 #define AC_PARAM_AIFS_OFFSET			0
1102 #define _BCNIFS(x)				((x) & 0xFF)
1103 #define _BCNECW(x)				((((x) & 0xF)) << 8)
1105 #define _LRL(x)					((x) & 0x3F)
1106 #define _SRL(x)					(((x) & 0x3F) << 8)
1108 #define _SIFS_CCK_CTX(x)			((x) & 0xFF)
1109 #define _SIFS_CCK_TRX(x)			(((x) & 0xFF) << 8)
1111 #define _SIFS_OFDM_CTX(x)			((x) & 0xFF)
1112 #define _SIFS_OFDM_TRX(x)			(((x) & 0xFF) << 8)
1114 #define _TBTT_PROHIBIT_HOLD(x)			(((x) & 0xFF) << 8)
1122 #define TSFTR_RST				BIT(0)
1130 #define	ACMHW_HWEN				BIT(0)
1143 #define RATE_BITMAP_ALL				0xFFFFF
1145 #define RATE_RRSR_CCK_ONLY_1M			0xFFFF1
1147 #define TSFRST					BIT(0)
1156 #define AAP					BIT(0)
1182 #define _MIN_SPACE(x)				((x) & 0x7)
1183 #define _SHORT_GI_PADDING(x)		(((x) & 0x1F) << 3)
1185 #define RXERR_TYPE_OFDM_PPDU		0
1200 #define RXERR_COUNTER_MASK			0xFFFFF
1204 #define	SCR_TXUSEDK				BIT(0)
1213 #define XCLK_VLD				BIT(0)
1233 #define USB_IS_HIGH_SPEED			0
1237 #define USB_NORMAL_SIE_EP_MASK			0xF
1240 #define USB_TEST_EP_MASK			0x30
1251 #define	MAX_MSS_DENSITY_2T			0x13
1252 #define	MAX_MSS_DENSITY_1T			0x0A
1255 #define EPROM_CMD_CONFIG			0x3
1262 #define	RPMAC_RESET				0x100
1263 #define	RPMAC_TXSTART				0x104
1264 #define	RPMAC_TXLEGACYSIG			0x108
1265 #define	RPMAC_TXHTSIG1				0x10c
1266 #define	RPMAC_TXHTSIG2				0x110
1267 #define	RPMAC_PHYDEBUG				0x114
1268 #define	RPMAC_TXPACKETNUM			0x118
1269 #define	RPMAC_TXIDLE				0x11c
1270 #define	RPMAC_TXMACHEADER0			0x120
1271 #define	RPMAC_TXMACHEADER1			0x124
1272 #define	RPMAC_TXMACHEADER2			0x128
1273 #define	RPMAC_TXMACHEADER3			0x12c
1274 #define	RPMAC_TXMACHEADER4			0x130
1275 #define	RPMAC_TXMACHEADER5			0x134
1276 #define	RPMAC_TXDADATYPE			0x138
1277 #define	RPMAC_TXRANDOMSEED			0x13c
1278 #define	RPMAC_CCKPLCPPREAMBLE			0x140
1279 #define	RPMAC_CCKPLCPHEADER			0x144
1280 #define	RPMAC_CCKCRC16				0x148
1281 #define	RPMAC_OFDMRXCRC32OK			0x170
1282 #define	RPMAC_OFDMRXCRC32ER			0x174
1283 #define	RPMAC_OFDMRXPARITYER			0x178
1284 #define	RPMAC_OFDMRXCRC8ER			0x17c
1285 #define	RPMAC_CCKCRXRC16ER			0x180
1286 #define	RPMAC_CCKCRXRC32ER			0x184
1287 #define	RPMAC_CCKCRXRC32OK			0x188
1288 #define	RPMAC_TXSTATUS				0x18c
1290 #define	RFPGA0_RFMOD				0x800
1292 #define	RFPGA0_TXINFO				0x804
1293 #define	RFPGA0_PSDFUNCTION			0x808
1295 #define	RFPGA0_TXGAINSTAGE			0x80c
1297 #define	RFPGA0_RFTIMING1			0x810
1298 #define	RFPGA0_RFTIMING2			0x814
1300 #define	RFPGA0_XA_HSSIPARAMETER1	0x820
1301 #define	RFPGA0_XA_HSSIPARAMETER2	0x824
1302 #define	RFPGA0_XB_HSSIPARAMETER1	0x828
1303 #define	RFPGA0_XB_HSSIPARAMETER2	0x82c
1305 #define	RFPGA0_XA_LSSIPARAMETER		0x840
1306 #define	RFPGA0_XB_LSSIPARAMETER		0x844
1308 #define	RFPGA0_RFWAKEUPPARAMETER	0x850
1309 #define	RFPGA0_RFSLEEPUPPARAMETER	0x854
1311 #define	RFPGA0_XAB_SWITCHCONTROL	0x858
1312 #define	RFPGA0_XCD_SWITCHCONTROL	0x85c
1314 #define	RFPGA0_XA_RFINTERFACEOE		0x860
1315 #define	RFPGA0_XB_RFINTERFACEOE		0x864
1317 #define	RFPGA0_XAB_RFINTERFACESW	0x870
1318 #define	RFPGA0_XCD_RFINTERFACESW	0x874
1320 #define	RFPGA0_XAB_RFPARAMETER		0x878
1321 #define	RFPGA0_XCD_RFPARAMETER		0x87c
1323 #define	RFPGA0_ANALOGPARAMETER1		0x880
1324 #define	RFPGA0_ANALOGPARAMETER2		0x884
1325 #define	RFPGA0_ANALOGPARAMETER3		0x888
1326 #define	RFPGA0_ANALOGPARAMETER4		0x88c
1328 #define	RFPGA0_XA_LSSIREADBACK		0x8a0
1329 #define	RFPGA0_XB_LSSIREADBACK		0x8a4
1330 #define	RFPGA0_XC_LSSIREADBACK		0x8a8
1331 #define	RFPGA0_XD_LSSIREADBACK		0x8ac
1333 #define	RFPGA0_PSDREPORT		0x8b4
1334 #define	TRANSCEIVEA_HSPI_READBACK	0x8b8
1335 #define	TRANSCEIVEB_HSPI_READBACK	0x8bc
1336 #define	REG_SC_CNT			0x8c4
1337 #define	RFPGA0_XAB_RFINTERFACERB	0x8e0
1338 #define	RFPGA0_XCD_RFINTERFACERB	0x8e4
1340 #define	RFPGA1_RFMOD			0x900
1342 #define	RFPGA1_TXBLOCK			0x904
1343 #define	RFPGA1_DEBUGSELECT		0x908
1344 #define	RFPGA1_TXINFO			0x90c
1346 #define	RCCK0_SYSTEM			0xa00
1348 #define	RCCK0_AFESETTING		0xa04
1349 #define	RCCK0_CCA			0xa08
1351 #define	RCCK0_RXAGC1			0xa0c
1352 #define	RCCK0_RXAGC2			0xa10
1354 #define	RCCK0_RXHP			0xa14
1356 #define	RCCK0_DSPPARAMETER1		0xa18
1357 #define	RCCK0_DSPPARAMETER2		0xa1c
1359 #define	RCCK0_TXFILTER1			0xa20
1360 #define	RCCK0_TXFILTER2			0xa24
1361 #define	RCCK0_DEBUGPORT			0xa28
1362 #define	RCCK0_FALSEALARMREPORT		0xa2c
1363 #define	RCCK0_TRSSIREPORT		0xa50
1364 #define	RCCK0_RXREPORT			0xa54
1365 #define	RCCK0_FACOUNTERLOWER		0xa5c
1366 #define	RCCK0_FACOUNTERUPPER		0xa58
1367 #define	RCCK0_CCA_CNT			0xa60
1369 /* PageB(0xB00) */
1370 #define	RPDP_ANTA			0xb00
1371 #define	RPDP_ANTA_4			0xb04
1372 #define	RPDP_ANTA_8			0xb08
1373 #define	RPDP_ANTA_C			0xb0c
1374 #define	RPDP_ANTA_10			0xb10
1375 #define	RPDP_ANTA_14			0xb14
1376 #define	RPDP_ANTA_18			0xb18
1377 #define	RPDP_ANTA_1C			0xb1c
1378 #define	RPDP_ANTA_20			0xb20
1379 #define	RPDP_ANTA_24			0xb24
1381 #define	RCONFIG_PMPD_ANTA		0xb28
1382 #define	RCONFIG_ram64x16		0xb2c
1384 #define	RBNDA				0xb30
1385 #define	RHSSIPAR			0xb34
1387 #define	RCONFIG_ANTA			0xb68
1388 #define	RCONFIG_ANTB			0xb6c
1390 #define	RPDP_ANTB			0xb70
1391 #define	RPDP_ANTB_4			0xb74
1392 #define	RPDP_ANTB_8			0xb78
1393 #define	RPDP_ANTB_C			0xb7c
1394 #define	RPDP_ANTB_10			0xb80
1395 #define	RPDP_ANTB_14			0xb84
1396 #define	RPDP_ANTB_18			0xb88
1397 #define	RPDP_ANTB_1C			0xb8c
1398 #define	RPDP_ANTB_20			0xb90
1399 #define	RPDP_ANTB_24			0xb94
1401 #define	RCONFIG_PMPD_ANTB		0xb98
1403 #define	RBNDB				0xba0
1405 #define	RAPK				0xbd8
1406 #define	RPM_RX0_ANTA			0xbdc
1407 #define	RPM_RX1_ANTA			0xbe0
1408 #define	RPM_RX2_ANTA			0xbe4
1409 #define	RPM_RX3_ANTA			0xbe8
1410 #define	RPM_RX0_ANTB			0xbec
1411 #define	RPM_RX1_ANTB			0xbf0
1412 #define	RPM_RX2_ANTB			0xbf4
1413 #define	RPM_RX3_ANTB			0xbf8
1416 #define	ROFDM0_LSTF			0xc00
1418 #define	ROFDM0_TRXPATHENABLE		0xc04
1419 #define	ROFDM0_TRMUXPAR			0xc08
1420 #define	ROFDM0_TRSWISOLATION		0xc0c
1422 #define	ROFDM0_XARXAFE			0xc10
1423 #define	ROFDM0_XARXIQIMBALANCE		0xc14
1424 #define	ROFDM0_XBRXAFE			0xc18
1425 #define	ROFDM0_XBRXIQIMBALANCE		0xc1c
1426 #define	ROFDM0_XCRXAFE			0xc20
1427 #define	ROFDM0_XCRXIQIMBANLANCE		0xc24
1428 #define	ROFDM0_XDRXAFE			0xc28
1429 #define	ROFDM0_XDRXIQIMBALANCE		0xc2c
1431 #define	ROFDM0_RXDETECTOR1		0xc30
1432 #define	ROFDM0_RXDETECTOR2		0xc34
1433 #define	ROFDM0_RXDETECTOR3		0xc38
1434 #define	ROFDM0_RXDETECTOR4		0xc3c
1436 #define	ROFDM0_RXDSP			0xc40
1437 #define	ROFDM0_CFOANDDAGC		0xc44
1438 #define	ROFDM0_CCADROPTHRESHOLD		0xc48
1439 #define	ROFDM0_ECCATHRESHOLD		0xc4c
1441 #define	ROFDM0_XAAGCCORE1		0xc50
1442 #define	ROFDM0_XAAGCCORE2		0xc54
1443 #define	ROFDM0_XBAGCCORE1		0xc58
1444 #define	ROFDM0_XBAGCCORE2		0xc5c
1445 #define	ROFDM0_XCAGCCORE1		0xc60
1446 #define	ROFDM0_XCAGCCORE2		0xc64
1447 #define	ROFDM0_XDAGCCORE1		0xc68
1448 #define	ROFDM0_XDAGCCORE2		0xc6c
1450 #define	ROFDM0_AGCPARAMETER1		0xc70
1451 #define	ROFDM0_AGCPARAMETER2		0xc74
1452 #define	ROFDM0_AGCRSSITABLE		0xc78
1453 #define	ROFDM0_HTSTFAGC			0xc7c
1455 #define	ROFDM0_XATXIQIMBALANCE		0xc80
1456 #define	ROFDM0_XATXAFE			0xc84
1457 #define	ROFDM0_XBTXIQIMBALANCE		0xc88
1458 #define	ROFDM0_XBTXAFE			0xc8c
1459 #define	ROFDM0_XCTXIQIMBALANCE		0xc90
1460 #define	ROFDM0_XCTXAFE			0xc94
1461 #define	ROFDM0_XDTXIQIMBALANCE		0xc98
1462 #define	ROFDM0_XDTXAFE			0xc9c
1464 #define ROFDM0_RXIQEXTANTA		0xca0
1465 #define	ROFDM0_TXCOEFF1			0xca4
1466 #define	ROFDM0_TXCOEFF2			0xca8
1467 #define	ROFDM0_TXCOEFF3			0xcac
1468 #define	ROFDM0_TXCOEFF4			0xcb0
1469 #define	ROFDM0_TXCOEFF5			0xcb4
1470 #define	ROFDM0_TXCOEFF6			0xcb8
1472 #define	ROFDM0_RXHPPARAMETER		0xce0
1473 #define	ROFDM0_TXPSEUDONOISEWGT		0xce4
1474 #define	ROFDM0_FRAMESYNC		0xcf0
1475 #define	ROFDM0_DFSREPORT		0xcf4
1477 #define	ROFDM1_LSTF			0xd00
1478 #define	ROFDM1_TRXPATHENABLE		0xd04
1480 #define	ROFDM1_CF0			0xd08
1481 #define	ROFDM1_CSI1			0xd10
1482 #define	ROFDM1_SBD			0xd14
1483 #define	ROFDM1_CSI2			0xd18
1484 #define	ROFDM1_CFOTRACKING		0xd2c
1485 #define	ROFDM1_TRXMESAURE1		0xd34
1486 #define	ROFDM1_INTFDET			0xd3c
1487 #define	ROFDM1_PSEUDONOISESTATEAB	0xd50
1488 #define	ROFDM1_PSEUDONOISESTATECD	0xd54
1489 #define	ROFDM1_RXPSEUDONOISEWGT		0xd58
1491 #define	ROFDM_PHYCOUNTER1		0xda0
1492 #define	ROFDM_PHYCOUNTER2		0xda4
1493 #define	ROFDM_PHYCOUNTER3		0xda8
1495 #define	ROFDM_SHORTCFOAB		0xdac
1496 #define	ROFDM_SHORTCFOCD		0xdb0
1497 #define	ROFDM_LONGCFOAB			0xdb4
1498 #define	ROFDM_LONGCFOCD			0xdb8
1499 #define	ROFDM_TAILCF0AB			0xdbc
1500 #define	ROFDM_TAILCF0CD			0xdc0
1501 #define	ROFDM_PWMEASURE1		0xdc4
1502 #define	ROFDM_PWMEASURE2		0xdc8
1503 #define	ROFDM_BWREPORT			0xdcc
1504 #define	ROFDM_AGCREPORT			0xdd0
1505 #define	ROFDM_RXSNR			0xdd4
1506 #define	ROFDM_RXEVMCSI			0xdd8
1507 #define	ROFDM_SIGREPORT			0xddc
1509 #define	RTXAGC_A_RATE18_06		0xe00
1510 #define	RTXAGC_A_RATE54_24		0xe04
1511 #define	RTXAGC_A_CCK1_MCS32		0xe08
1512 #define	RTXAGC_A_MCS03_MCS00		0xe10
1513 #define	RTXAGC_A_MCS07_MCS04		0xe14
1514 #define	RTXAGC_A_MCS11_MCS08		0xe18
1515 #define	RTXAGC_A_MCS15_MCS12		0xe1c
1517 #define	RTXAGC_B_RATE18_06		0x830
1518 #define	RTXAGC_B_RATE54_24		0x834
1519 #define	RTXAGC_B_CCK1_55_MCS32		0x838
1520 #define	RTXAGC_B_MCS03_MCS00		0x83c
1521 #define	RTXAGC_B_MCS07_MCS04		0x848
1522 #define	RTXAGC_B_MCS11_MCS08		0x84c
1523 #define	RTXAGC_B_MCS15_MCS12		0x868
1524 #define	RTXAGC_B_CCK11_A_CCK2_11	0x86c
1526 #define	RFPGA0_IQK			0xe28
1527 #define	RTX_IQK_TONE_A			0xe30
1528 #define	RRX_IQK_TONE_A			0xe34
1529 #define	RTX_IQK_PI_A			0xe38
1530 #define	RRX_IQK_PI_A			0xe3c
1532 #define	RTX_IQK				0xe40
1533 #define	RRX_IQK				0xe44
1534 #define	RIQK_AGC_PTS			0xe48
1535 #define	RIQK_AGC_RSP			0xe4c
1536 #define	RTX_IQK_TONE_B			0xe50
1537 #define	RRX_IQK_TONE_B			0xe54
1538 #define	RTX_IQK_PI_B			0xe58
1539 #define	RRX_IQK_PI_B			0xe5c
1540 #define	RIQK_AGC_CONT			0xe60
1542 #define	RBLUE_TOOTH			0xe6c
1543 #define	RRX_WAIT_CCA			0xe70
1544 #define	RTX_CCK_RFON			0xe74
1545 #define	RTX_CCK_BBON			0xe78
1546 #define	RTX_OFDM_RFON			0xe7c
1547 #define	RTX_OFDM_BBON			0xe80
1548 #define	RTX_TO_RX			0xe84
1549 #define	RTX_TO_TX			0xe88
1550 #define	RRX_CCK				0xe8c
1552 #define	RTX_POWER_BEFORE_IQK_A		0xe94
1553 #define	RTX_POWER_AFTER_IQK_A		0xe9c
1555 #define	RRX_POWER_BEFORE_IQK_A		0xea0
1556 #define	RRX_POWER_BEFORE_IQK_A_2	0xea4
1557 #define	RRX_POWER_AFTER_IQK_A		0xea8
1558 #define	RRX_POWER_AFTER_IQK_A_2		0xeac
1560 #define	RTX_POWER_BEFORE_IQK_B		0xeb4
1561 #define	RTX_POWER_AFTER_IQK_B		0xebc
1563 #define	RRX_POWER_BEFORE_IQK_B		0xec0
1564 #define	RRX_POWER_BEFORE_IQK_B_2	0xec4
1565 #define	RRX_POWER_AFTER_IQK_B		0xec8
1566 #define	RRX_POWER_AFTER_IQK_B_2		0xecc
1568 #define	RRX_OFDM			0xed0
1569 #define	RRX_WAIT_RIFS			0xed4
1570 #define	RRX_TO_RX			0xed8
1571 #define	RSTANDBY			0xedc
1572 #define	RSLEEP				0xee0
1573 #define	RPMPD_ANAEN			0xeec
1575 #define	RZEBRA1_HSSIENABLE			0x0
1576 #define	RZEBRA1_TRXENABLE1			0x1
1577 #define	RZEBRA1_TRXENABLE2			0x2
1578 #define	RZEBRA1_AGC				0x4
1579 #define	RZEBRA1_CHARGEPUMP			0x5
1580 #define	RZEBRA1_CHANNEL				0x7
1582 #define	RZEBRA1_TXGAIN				0x8
1583 #define	RZEBRA1_TXLPF				0x9
1584 #define	RZEBRA1_RXLPF				0xb
1585 #define	RZEBRA1_RXHPFCORNER			0xc
1587 #define	RGLOBALCTRL				0
1590 #define	RRTL8258_TXLPF				0x11
1591 #define	RRTL8258_RXLPF				0x13
1592 #define	RRTL8258_RSSILPF			0xa
1594 #define	RF_AC					0x00
1596 #define	RF_IQADJ_G1				0x01
1597 #define	RF_IQADJ_G2				0x02
1598 #define	RF_POW_TRSW				0x05
1600 #define	RF_GAIN_RX				0x06
1601 #define	RF_GAIN_TX				0x07
1603 #define	RF_TXM_IDAC				0x08
1604 #define	RF_BS_IQGEN				0x0F
1606 #define	RF_MODE1				0x10
1607 #define	RF_MODE2				0x11
1609 #define	RF_RX_AGC_HP				0x12
1610 #define	RF_TX_AGC				0x13
1611 #define	RF_BIAS					0x14
1612 #define	RF_IPA					0x15
1613 #define	RF_POW_ABILITY				0x17
1614 #define	RF_MODE_AG				0x18
1615 #define	RRFCHANNEL				0x18
1616 #define	RF_CHNLBW				0x18
1617 #define	RF_TOP					0x19
1619 #define	RF_RX_G1				0x1A
1620 #define	RF_RX_G2				0x1B
1622 #define	RF_RX_BB2				0x1C
1623 #define	RF_RX_BB1				0x1D
1625 #define	RF_RCK1					0x1E
1626 #define	RF_RCK2					0x1F
1628 #define	RF_TX_G1				0x20
1629 #define	RF_TX_G2				0x21
1630 #define	RF_TX_G3				0x22
1632 #define	RF_TX_BB1				0x23
1633 #define	RF_T_METER				0x42
1635 #define	RF_SYN_G1				0x25
1636 #define	RF_SYN_G2				0x26
1637 #define	RF_SYN_G3				0x27
1638 #define	RF_SYN_G4				0x28
1639 #define	RF_SYN_G5				0x29
1640 #define	RF_SYN_G6				0x2A
1641 #define	RF_SYN_G7				0x2B
1642 #define	RF_SYN_G8				0x2C
1644 #define	RF_RCK_OS				0x30
1645 #define	RF_TXPA_G1				0x31
1646 #define	RF_TXPA_G2				0x32
1647 #define	RF_TXPA_G3				0x33
1649 #define	RF_TX_BIAS_A				0x35
1650 #define	RF_TX_BIAS_D				0x36
1651 #define	RF_LOBF_9				0x38
1652 #define	RF_RXRF_A3				0x3C
1653 #define	RF_TRSW					0x3F
1655 #define	RF_TXRF_A2				0x41
1656 #define	RF_TXPA_G4				0x46
1657 #define	RF_TXPA_A4				0x4B
1659 #define	RF_WE_LUT				0xEF
1661 #define	BBBRESETB				0x100
1662 #define	BGLOBALRESETB				0x200
1663 #define	BOFDMTXSTART				0x4
1664 #define	BCCKTXSTART				0x8
1665 #define	BCRC32DEBUG				0x100
1666 #define	BPMACLOOPBACK				0x10
1667 #define	BTXLSIG					0xffffff
1668 #define	BOFDMTXRATE				0xf
1669 #define	BOFDMTXRESERVED				0x10
1670 #define	BOFDMTXLENGTH				0x1ffe0
1671 #define	BOFDMTXPARITY				0x20000
1672 #define	BTXHTSIG1				0xffffff
1673 #define	BTXHTMCSRATE				0x7f
1674 #define	BTXHTBW					0x80
1675 #define	BTXHTLENGTH				0xffff00
1676 #define	BTXHTSIG2				0xffffff
1677 #define	BTXHTSMOOTHING				0x1
1678 #define	BTXHTSOUNDING				0x2
1679 #define	BTXHTRESERVED				0x4
1680 #define	BTXHTAGGREATION				0x8
1681 #define	BTXHTSTBC				0x30
1682 #define	BTXHTADVANCECODING			0x40
1683 #define	BTXHTSHORTGI				0x80
1684 #define	BTXHTNUMBERHT_LTF			0x300
1685 #define	BTXHTCRC8				0x3fc00
1686 #define	BCOUNTERRESET				0x10000
1687 #define	BNUMOFOFDMTX				0xffff
1688 #define	BNUMOFCCKTX				0xffff0000
1689 #define	BTXIDLEINTERVAL				0xffff
1690 #define	BOFDMSERVICE				0xffff0000
1691 #define	BTXMACHEADER				0xffffffff
1692 #define	BTXDATAINIT				0xff
1693 #define	BTXHTMODE				0x100
1694 #define	BTXDATATYPE				0x30000
1695 #define	BTXRANDOMSEED				0xffffffff
1696 #define	BCCKTXPREAMBLE				0x1
1697 #define	BCCKTXSFD				0xffff0000
1698 #define	BCCKTXSIG				0xff
1699 #define	BCCKTXSERVICE				0xff00
1700 #define	BCCKLENGTHEXT				0x8000
1701 #define	BCCKTXLENGHT				0xffff0000
1702 #define	BCCKTXCRC16				0xffff
1703 #define	BCCKTXSTATUS				0x1
1704 #define	BOFDMTXSTATUS				0x2
1706 	((_offset >= 0x800) && (_offset <= 0xfff))
1708 #define	BRFMOD					0x1
1709 #define	BJAPANMODE				0x2
1710 #define	BCCKTXSC				0x30
1711 #define	BCCKEN					0x1000000
1712 #define	BOFDMEN					0x2000000
1714 #define	BOFDMRXADCPHASE			0x10000
1715 #define	BOFDMTXDACPHASE			0x40000
1716 #define	BXATXAGC			0x3f
1718 #define	BXBTXAGC			0xf00
1719 #define	BXCTXAGC			0xf000
1720 #define	BXDTXAGC			0xf0000
1722 #define	BPASTART			0xf0000000
1723 #define	BTRSTART			0x00f00000
1724 #define	BRFSTART			0x0000f000
1725 #define	BBBSTART			0x000000f0
1726 #define	BBBCCKSTART			0x0000000f
1727 #define	BPAEND				0xf
1728 #define	BTREND				0x0f000000
1729 #define	BRFEND				0x000f0000
1730 #define	BCCAMASK			0x000000f0
1731 #define	BR2RCCAMASK			0x00000f00
1732 #define	BHSSI_R2TDELAY			0xf8000000
1733 #define	BHSSI_T2RDELAY			0xf80000
1734 #define	BCONTXHSSI			0x400
1735 #define	BIGFROMCCK			0x200
1736 #define	BAGCADDRESS			0x3f
1737 #define	BRXHPTX				0x7000
1738 #define	BRXHP2RX			0x38000
1739 #define	BRXHPCCKINI			0xc0000
1740 #define	BAGCTXCODE			0xc00000
1741 #define	BAGCRXCODE			0x300000
1743 #define	B3WIREDATALENGTH		0x800
1744 #define	B3WIREADDREAALENGTH		0x400
1746 #define	B3WIRERFPOWERDOWN		0x1
1747 #define	B5GPAPEPOLARITY			0x40000000
1748 #define	B2GPAPEPOLARITY			0x80000000
1749 #define	BRFSW_TXDEFAULTANT		0x3
1750 #define	BRFSW_TXOPTIONANT		0x30
1751 #define	BRFSW_RXDEFAULTANT		0x300
1752 #define	BRFSW_RXOPTIONANT		0x3000
1753 #define	BRFSI_3WIREDATA			0x1
1754 #define	BRFSI_3WIRECLOCK		0x2
1755 #define	BRFSI_3WIRELOAD			0x4
1756 #define	BRFSI_3WIRERW			0x8
1757 #define	BRFSI_3WIRE			0xf
1759 #define	BRFSI_RFENV			0x10
1761 #define	BRFSI_TRSW			0x20
1762 #define	BRFSI_TRSWB			0x40
1763 #define	BRFSI_ANTSW			0x100
1764 #define	BRFSI_ANTSWB			0x200
1765 #define	BRFSI_PAPE			0x400
1766 #define	BRFSI_PAPE5G			0x800
1767 #define	BBANDSELECT			0x1
1768 #define	BHTSIG2_GI			0x80
1769 #define	BHTSIG2_SMOOTHING		0x01
1770 #define	BHTSIG2_SOUNDING		0x02
1771 #define	BHTSIG2_AGGREATON		0x08
1772 #define	BHTSIG2_STBC			0x30
1773 #define	BHTSIG2_ADVCODING		0x40
1774 #define	BHTSIG2_NUMOFHTLTF		0x300
1775 #define	BHTSIG2_CRC8			0x3fc
1776 #define	BHTSIG1_MCS			0x7f
1777 #define	BHTSIG1_BANDWIDTH		0x80
1778 #define	BHTSIG1_HTLENGTH		0xffff
1779 #define	BLSIG_RATE			0xf
1780 #define	BLSIG_RESERVED			0x10
1781 #define	BLSIG_LENGTH			0x1fffe
1782 #define	BLSIG_PARITY			0x20
1783 #define	BCCKRXPHASE			0x4
1785 #define	BLSSIREADADDRESS		0x7f800000
1786 #define	BLSSIREADEDGE			0x80000000
1788 #define	BLSSIREADBACKDATA		0xfffff
1790 #define	BLSSIREADOKFLAG			0x1000
1791 #define	BCCKSAMPLERATE			0x8
1792 #define	BREGULATOR0STANDBY		0x1
1793 #define	BREGULATORPLLSTANDBY		0x2
1794 #define	BREGULATOR1STANDBY		0x4
1795 #define	BPLLPOWERUP			0x8
1796 #define	BDPLLPOWERUP			0x10
1797 #define	BDA10POWERUP			0x20
1798 #define	BAD7POWERUP			0x200
1799 #define	BDA6POWERUP			0x2000
1800 #define	BXTALPOWERUP			0x4000
1801 #define	B40MDCLKPOWERUP			0x8000
1802 #define	BDA6DEBUGMODE			0x20000
1803 #define	BDA6SWING			0x380000
1805 #define	BADCLKPHASE			0x4000000
1806 #define	B80MCLKDELAY			0x18000000
1807 #define	BAFEWATCHDOGENABLE		0x20000000
1809 #define	BXTALCAP01			0xc0000000
1810 #define	BXTALCAP23			0x3
1811 #define	BXTALCAP92X			0x0f000000
1812 #define BXTALCAP			0x0f000000
1814 #define	BINTDIFCLKENABLE		0x400
1815 #define	BEXTSIGCLKENABLE		0x800
1816 #define	BBANDGAP_MBIAS_POWERUP		0x10000
1817 #define	BAD11SH_GAIN			0xc0000
1818 #define	BAD11NPUT_RANGE			0x700000
1819 #define	BAD110P_CURRENT			0x3800000
1820 #define	BLPATH_LOOPBACK			0x4000000
1821 #define	BQPATH_LOOPBACK			0x8000000
1822 #define	BAFE_LOOPBACK			0x10000000
1823 #define	BDA10_SWING			0x7e0
1824 #define	BDA10_REVERSE			0x800
1825 #define	BDA_CLK_SOURCE			0x1000
1826 #define	BDA7INPUT_RANGE			0x6000
1827 #define	BDA7_GAIN			0x38000
1828 #define	BDA7OUTPUT_CM_MODE		0x40000
1829 #define	BDA7INPUT_CM_MODE		0x380000
1830 #define	BDA7CURRENT			0xc00000
1831 #define	BREGULATOR_ADJUST		0x7000000
1832 #define	BAD11POWERUP_ATTX		0x1
1833 #define	BDA10PS_ATTX			0x10
1834 #define	BAD11POWERUP_ATRX		0x100
1835 #define	BDA10PS_ATRX			0x1000
1836 #define	BCCKRX_AGC_FORMAT		0x200
1837 #define	BPSDFFT_SAMPLE_POINT		0xc000
1838 #define	BPSD_AVERAGE_NUM		0x3000
1839 #define	BIQPATH_CONTROL			0xc00
1840 #define	BPSD_FREQ			0x3ff
1841 #define	BPSD_ANTENNA_PATH		0x30
1842 #define	BPSD_IQ_SWITCH			0x40
1843 #define	BPSD_RX_TRIGGER			0x400000
1844 #define	BPSD_TX_TRIGGER			0x80000000
1845 #define	BPSD_SINE_TONE_SCALE		0x7f000000
1846 #define	BPSD_REPORT			0xffff
1848 #define	BOFDM_TXSC			0x30000000
1849 #define	BCCK_TXON			0x1
1850 #define	BOFDM_TXON			0x2
1851 #define	BDEBUG_PAGE			0xfff
1852 #define	BDEBUG_ITEM			0xff
1853 #define	BANTL				0x10
1854 #define	BANT_NONHT			0x100
1855 #define	BANT_HT1			0x1000
1856 #define	BANT_HT2			0x10000
1857 #define	BANT_HT1S1			0x100000
1858 #define	BANT_NONHTS1			0x1000000
1860 #define	BCCK_BBMODE			0x3
1861 #define	BCCK_TXPOWERSAVING		0x80
1862 #define	BCCK_RXPOWERSAVING		0x40
1864 #define	BCCK_SIDEBAND			0x10
1866 #define	BCCK_SCRAMBLE			0x8
1867 #define	BCCK_ANTDIVERSITY		0x8000
1868 #define	BCCK_CARRIER_RECOVERY		0x4000
1869 #define	BCCK_TXRATE			0x3000
1870 #define	BCCK_DCCANCEL			0x0800
1871 #define	BCCK_ISICANCEL			0x0400
1872 #define	BCCK_MATCH_FILTER		0x0200
1873 #define	BCCK_EQUALIZER			0x0100
1874 #define	BCCK_PREAMBLE_DETECT		0x800000
1875 #define	BCCK_FAST_FALSECCA		0x400000
1876 #define	BCCK_CH_ESTSTART		0x300000
1877 #define	BCCK_CCA_COUNT			0x080000
1878 #define	BCCK_CS_LIM			0x070000
1879 #define	BCCK_BIST_MODE			0x80000000
1880 #define	BCCK_CCAMASK			0x40000000
1881 #define	BCCK_TX_DAC_PHASE		0x4
1882 #define	BCCK_RX_ADC_PHASE		0x20000000
1883 #define	BCCKR_CP_MODE			0x0100
1884 #define	BCCK_TXDC_OFFSET		0xf0
1885 #define	BCCK_RXDC_OFFSET		0xf
1886 #define	BCCK_CCA_MODE			0xc000
1887 #define	BCCK_FALSECS_LIM		0x3f00
1888 #define	BCCK_CS_RATIO			0xc00000
1889 #define	BCCK_CORGBIT_SEL		0x300000
1890 #define	BCCK_PD_LIM			0x0f0000
1891 #define	BCCK_NEWCCA			0x80000000
1892 #define	BCCK_RXHP_OF_IG			0x8000
1893 #define	BCCK_RXIG			0x7f00
1894 #define	BCCK_LNA_POLARITY		0x800000
1895 #define	BCCK_RX1ST_BAIN			0x7f0000
1896 #define	BCCK_RF_EXTEND			0x20000000
1897 #define	BCCK_RXAGC_SATLEVEL		0x1f000000
1898 #define	BCCK_RXAGC_SATCOUNT		0xe0
1899 #define	BCCKRXRFSETTLE			0x1f
1900 #define	BCCK_FIXED_RXAGC		0x8000
1901 #define	BCCK_ANTENNA_POLARITY		0x2000
1902 #define	BCCK_TXFILTER_TYPE		0x0c00
1903 #define	BCCK_RXAGC_REPORTTYPE		0x0300
1904 #define	BCCK_RXDAGC_EN			0x80000000
1905 #define	BCCK_RXDAGC_PERIOD		0x20000000
1906 #define	BCCK_RXDAGC_SATLEVEL		0x1f000000
1907 #define	BCCK_TIMING_RECOVERY		0x800000
1908 #define	BCCK_TXC0			0x3f0000
1909 #define	BCCK_TXC1			0x3f000000
1910 #define	BCCK_TXC2			0x3f
1911 #define	BCCK_TXC3			0x3f00
1912 #define	BCCK_TXC4			0x3f0000
1913 #define	BCCK_TXC5			0x3f000000
1914 #define	BCCK_TXC6			0x3f
1915 #define	BCCK_TXC7			0x3f00
1916 #define	BCCK_DEBUGPORT			0xff0000
1917 #define	BCCK_DAC_DEBUG			0x0f000000
1918 #define	BCCK_FALSEALARM_ENABLE		0x8000
1919 #define	BCCK_FALSEALARM_READ		0x4000
1920 #define	BCCK_TRSSI			0x7f
1921 #define	BCCK_RXAGC_REPORT		0xfe
1922 #define	BCCK_RXREPORT_ANTSEL		0x80000000
1923 #define	BCCK_RXREPORT_MFOFF		0x40000000
1924 #define	BCCK_RXREPORT_SQLOSS		0x20000000
1925 #define	BCCK_RXREPORT_PKTLOSS		0x10000000
1926 #define	BCCK_RXREPORT_LOCKEDBIT		0x08000000
1927 #define	BCCK_RXREPORT_RATEERROR		0x04000000
1928 #define	BCCK_RXREPORT_RXRATE		0x03000000
1929 #define	BCCK_RXFA_COUNTER_LOWER		0xff
1930 #define	BCCK_RXFA_COUNTER_UPPER		0xff000000
1931 #define	BCCK_RXHPAGC_START		0xe000
1932 #define	BCCK_RXHPAGC_FINAL		0x1c00
1933 #define	BCCK_RXFALSEALARM_ENABLE	0x8000
1934 #define	BCCK_FACOUNTER_FREEZE		0x4000
1935 #define	BCCK_TXPATH_SEL			0x10000000
1936 #define	BCCK_DEFAULT_RXPATH		0xc000000
1937 #define	BCCK_OPTION_RXPATH		0x3000000
1939 #define	BNUM_OFSTF			0x3
1940 #define	BSHIFT_L			0xc0
1941 #define	BGI_TH				0xc
1942 #define	BRXPATH_A			0x1
1943 #define	BRXPATH_B			0x2
1944 #define	BRXPATH_C			0x4
1945 #define	BRXPATH_D			0x8
1946 #define	BTXPATH_A			0x1
1947 #define	BTXPATH_B			0x2
1948 #define	BTXPATH_C			0x4
1949 #define	BTXPATH_D			0x8
1950 #define	BTRSSI_FREQ			0x200
1951 #define	BADC_BACKOFF			0x3000
1952 #define	BDFIR_BACKOFF			0xc000
1953 #define	BTRSSI_LATCH_PHASE		0x10000
1954 #define	BRX_LDC_OFFSET			0xff
1955 #define	BRX_QDC_OFFSET			0xff00
1956 #define	BRX_DFIR_MODE			0x1800000
1957 #define	BRX_DCNF_TYPE			0xe000000
1958 #define	BRXIQIMB_A			0x3ff
1959 #define	BRXIQIMB_B			0xfc00
1960 #define	BRXIQIMB_C			0x3f0000
1961 #define	BRXIQIMB_D			0xffc00000
1962 #define	BDC_DC_NOTCH			0x60000
1963 #define	BRXNB_NOTCH			0x1f000000
1964 #define	BPD_TH				0xf
1965 #define	BPD_TH_OPT2			0xc000
1966 #define	BPWED_TH			0x700
1967 #define	BIFMF_WIN_L			0x800
1968 #define	BPD_OPTION			0x1000
1969 #define	BMF_WIN_L			0xe000
1970 #define	BBW_SEARCH_L			0x30000
1971 #define	BWIN_ENH_L			0xc0000
1972 #define	BBW_TH				0x700000
1973 #define	BED_TH2				0x3800000
1974 #define	BBW_OPTION			0x4000000
1975 #define	BRADIO_TH			0x18000000
1976 #define	BWINDOW_L			0xe0000000
1977 #define	BSBD_OPTION			0x1
1978 #define	BFRAME_TH			0x1c
1979 #define	BFS_OPTION			0x60
1980 #define	BDC_SLOPE_CHECK			0x80
1981 #define	BFGUARD_COUNTER_DC_L		0xe00
1982 #define	BFRAME_WEIGHT_SHORT		0x7000
1983 #define	BSUB_TUNE			0xe00000
1984 #define	BFRAME_DC_LENGTH		0xe000000
1985 #define	BSBD_START_OFFSET		0x30000000
1986 #define	BFRAME_TH_2			0x7
1987 #define	BFRAME_GI2_TH			0x38
1988 #define	BGI2_SYNC_EN			0x40
1989 #define	BSARCH_SHORT_EARLY		0x300
1990 #define	BSARCH_SHORT_LATE		0xc00
1991 #define	BSARCH_GI2_LATE			0x70000
1992 #define	BCFOANTSUM			0x1
1993 #define	BCFOACC				0x2
1994 #define	BCFOSTARTOFFSET			0xc
1995 #define	BCFOLOOPBACK			0x70
1996 #define	BCFOSUMWEIGHT			0x80
1997 #define	BDAGCENABLE			0x10000
1998 #define	BTXIQIMB_A			0x3ff
1999 #define	BTXIQIMB_b			0xfc00
2000 #define	BTXIQIMB_C			0x3f0000
2001 #define	BTXIQIMB_D			0xffc00000
2002 #define	BTXIDCOFFSET			0xff
2003 #define	BTXIQDCOFFSET			0xff00
2004 #define	BTXDFIRMODE			0x10000
2005 #define	BTXPESUDO_NOISEON		0x4000000
2006 #define	BTXPESUDO_NOISE_A		0xff
2007 #define	BTXPESUDO_NOISE_B		0xff00
2008 #define	BTXPESUDO_NOISE_C		0xff0000
2009 #define	BTXPESUDO_NOISE_D		0xff000000
2010 #define	BCCA_DROPOPTION			0x20000
2011 #define	BCCA_DROPTHRES			0xfff00000
2012 #define	BEDCCA_H			0xf
2013 #define	BEDCCA_L			0xf0
2014 #define	BLAMBDA_ED			0x300
2015 #define	BRX_INITIALGAIN			0x7f
2016 #define	BRX_ANTDIV_EN			0x80
2017 #define	BRX_AGC_ADDRESS_FOR_LNA		0x7f00
2018 #define	BRX_HIGHPOWER_FLOW		0x8000
2019 #define	BRX_AGC_FREEZE_THRES		0xc0000
2020 #define	BRX_FREEZESTEP_AGC1		0x300000
2021 #define	BRX_FREEZESTEP_AGC2		0xc00000
2022 #define	BRX_FREEZESTEP_AGC3		0x3000000
2023 #define	BRX_FREEZESTEP_AGC0		0xc000000
2024 #define	BRXRSSI_CMP_EN			0x10000000
2025 #define	BRXQUICK_AGCEN			0x20000000
2026 #define	BRXAGC_FREEZE_THRES_MODE	0x40000000
2027 #define	BRX_OVERFLOW_CHECKTYPE		0x80000000
2028 #define	BRX_AGCSHIFT			0x7f
2029 #define	BTRSW_TRI_ONLY			0x80
2030 #define	BPOWER_THRES			0x300
2031 #define	BRXAGC_EN			0x1
2032 #define	BRXAGC_TOGETHER_EN		0x2
2033 #define	BRXAGC_MIN			0x4
2034 #define	BRXHP_INI			0x7
2035 #define	BRXHP_TRLNA			0x70
2036 #define	BRXHP_RSSI			0x700
2037 #define	BRXHP_BBP1			0x7000
2038 #define	BRXHP_BBP2			0x70000
2039 #define	BRXHP_BBP3			0x700000
2040 #define	BRSSI_H				0x7f0000
2041 #define	BRSSI_GEN			0x7f000000
2042 #define	BRXSETTLE_TRSW			0x7
2043 #define	BRXSETTLE_LNA			0x38
2044 #define	BRXSETTLE_RSSI			0x1c0
2045 #define	BRXSETTLE_BBP			0xe00
2046 #define	BRXSETTLE_RXHP			0x7000
2047 #define	BRXSETTLE_ANTSW_RSSI		0x38000
2048 #define	BRXSETTLE_ANTSW			0xc0000
2049 #define	BRXPROCESS_TIME_DAGC		0x300000
2050 #define	BRXSETTLE_HSSI			0x400000
2051 #define	BRXPROCESS_TIME_BBPPW		0x800000
2052 #define	BRXANTENNA_POWER_SHIFT		0x3000000
2053 #define	BRSSI_TABLE_SELECT		0xc000000
2054 #define	BRXHP_FINAL			0x7000000
2055 #define	BRXHPSETTLE_BBP			0x7
2056 #define	BRXHTSETTLE_HSSI		0x8
2057 #define	BRXHTSETTLE_RXHP		0x70
2058 #define	BRXHTSETTLE_BBPPW		0x80
2059 #define	BRXHTSETTLE_IDLE		0x300
2060 #define	BRXHTSETTLE_RESERVED		0x1c00
2061 #define	BRXHT_RXHP_EN			0x8000
2062 #define	BRXAGC_FREEZE_THRES		0x30000
2063 #define	BRXAGC_TOGETHEREN		0x40000
2064 #define	BRXHTAGC_MIN			0x80000
2065 #define	BRXHTAGC_EN			0x100000
2066 #define	BRXHTDAGC_EN			0x200000
2067 #define	BRXHT_RXHP_BBP			0x1c00000
2068 #define	BRXHT_RXHP_FINAL		0xe0000000
2069 #define	BRXPW_RADIO_TH			0x3
2070 #define	BRXPW_RADIO_EN			0x4
2071 #define	BRXMF_HOLD			0x3800
2072 #define	BRXPD_DELAY_TH1			0x38
2073 #define	BRXPD_DELAY_TH2			0x1c0
2074 #define	BRXPD_DC_COUNT_MAX		0x600
2075 #define	BRXPD_DELAY_TH			0x8000
2076 #define	BRXPROCESS_DELAY		0xf0000
2077 #define	BRXSEARCHRANGE_GI2_EARLY	0x700000
2078 #define	BRXFRAME_FUARD_COUNTER_L	0x3800000
2079 #define	BRXSGI_GUARD_L			0xc000000
2080 #define	BRXSGI_SEARCH_L			0x30000000
2081 #define	BRXSGI_TH			0xc0000000
2082 #define	BDFSCNT0			0xff
2083 #define	BDFSCNT1			0xff00
2084 #define	BDFSFLAG			0xf0000
2085 #define	BMF_WEIGHT_SUM			0x300000
2086 #define	BMINIDX_TH			0x7f000000
2087 #define	BDAFORMAT			0x40000
2088 #define	BTXCH_EMU_ENABLE		0x01000000
2089 #define	BTRSW_ISOLATION_A		0x7f
2090 #define	BTRSW_ISOLATION_B		0x7f00
2091 #define	BTRSW_ISOLATION_C		0x7f0000
2092 #define	BTRSW_ISOLATION_D		0x7f000000
2093 #define	BEXT_LNA_GAIN			0x7c00
2095 #define	BSTBC_EN			0x4
2096 #define	BANTENNA_MAPPING		0x10
2097 #define	BNSS				0x20
2098 #define	BCFO_ANTSUM_ID			0x200
2099 #define	BPHY_COUNTER_RESET		0x8000000
2100 #define	BCFO_REPORT_GET			0x4000000
2101 #define	BOFDM_CONTINUE_TX		0x10000000
2102 #define	BOFDM_SINGLE_CARRIER		0x20000000
2103 #define	BOFDM_SINGLE_TONE		0x40000000
2104 #define	BHT_DETECT			0x100
2105 #define	BCFOEN				0x10000
2106 #define	BCFOVALUE			0xfff00000
2107 #define	BSIGTONE_RE			0x3f
2108 #define	BSIGTONE_IM			0x7f00
2109 #define	BCOUNTER_CCA			0xffff
2110 #define	BCOUNTER_PARITYFAIL		0xffff0000
2111 #define	BCOUNTER_RATEILLEGAL		0xffff
2112 #define	BCOUNTER_CRC8FAIL		0xffff0000
2113 #define	BCOUNTER_MCSNOSUPPORT		0xffff
2114 #define	BCOUNTER_FASTSYNC		0xffff
2115 #define	BSHORTCFO			0xfff
2118 #define	BLONGCFO			0x7ff
2121 #define	BTAILCFO			0x1fff
2124 #define	BNOISE_EN_PWDB			0xffff
2125 #define	BCC_POWER_DB			0xffff0000
2126 #define	BMOISE_PWDB			0xffff
2129 #define	BRX_HT_BW			0x1
2130 #define	BRXSC				0x6
2131 #define	BRX_HT				0x8
2132 #define	BNB_INTF_DET_ON			0x1
2133 #define	BINTF_WIN_LEN_CFG		0x30
2134 #define	BNB_INTF_TH_CFG			0x1c0
2135 #define	BRFGAIN				0x3f
2136 #define	BTABLESEL			0x40
2137 #define	BTRSW				0x80
2138 #define	BRXSNR_A			0xff
2139 #define	BRXSNR_B			0xff00
2140 #define	BRXSNR_C			0xff0000
2141 #define	BRXSNR_D			0xff000000
2144 #define	BCSI1ST				0xff
2145 #define	BCSI2ND				0xff00
2146 #define	BRXEVM1ST			0xff0000
2147 #define	BRXEVM2ND			0xff000000
2148 #define	BSIGEVM				0xff
2149 #define	BPWDB				0xff00
2150 #define	BSGIEN				0x10000
2152 #define	BSFACTOR_QMA1			0xf
2153 #define	BSFACTOR_QMA2			0xf0
2154 #define	BSFACTOR_QMA3			0xf00
2155 #define	BSFACTOR_QMA4			0xf000
2156 #define	BSFACTOR_QMA5			0xf0000
2157 #define	BSFACTOR_QMA6			0xf0000
2158 #define	BSFACTOR_QMA7			0xf00000
2159 #define	BSFACTOR_QMA8			0xf000000
2160 #define	BSFACTOR_QMA9			0xf0000000
2161 #define	BCSI_SCHEME			0x100000
2163 #define	BNOISE_LVL_TOP_SET		0x3
2164 #define	BCHSMOOTH			0x4
2165 #define	BCHSMOOTH_CFG1			0x38
2166 #define	BCHSMOOTH_CFG2			0x1c0
2167 #define	BCHSMOOTH_CFG3			0xe00
2168 #define	BCHSMOOTH_CFG4			0x7000
2169 #define	BMRCMODE			0x800000
2170 #define	BTHEVMCFG			0x7000000
2172 #define	BLOOP_FIT_TYPE			0x1
2173 #define	BUPD_CFO			0x40
2174 #define	BUPD_CFO_OFFDATA		0x80
2175 #define	BADV_UPD_CFO			0x100
2176 #define	BADV_TIME_CTRL			0x800
2177 #define	BUPD_CLKO			0x1000
2178 #define	BFC				0x6000
2179 #define	BTRACKING_MODE			0x8000
2180 #define	BPHCMP_ENABLE			0x10000
2181 #define	BUPD_CLKO_LTF			0x20000
2182 #define	BCOM_CH_CFO			0x40000
2183 #define	BCSI_ESTI_MODE			0x80000
2184 #define	BADV_UPD_EQZ			0x100000
2185 #define	BUCHCFG				0x7000000
2186 #define	BUPDEQZ				0x8000000
2188 #define	BRX_PESUDO_NOISE_ON		0x20000000
2189 #define	BRX_PESUDO_NOISE_A		0xff
2190 #define	BRX_PESUDO_NOISE_B		0xff00
2191 #define	BRX_PESUDO_NOISE_C		0xff0000
2192 #define	BRX_PESUDO_NOISE_D		0xff000000
2193 #define	BRX_PESUDO_NOISESTATE_A		0xffff
2194 #define	BRX_PESUDO_NOISESTATE_B		0xffff0000
2195 #define	BRX_PESUDO_NOISESTATE_C		0xffff
2196 #define	BRX_PESUDO_NOISESTATE_D		0xffff0000
2198 #define	BZEBRA1_HSSIENABLE		0x8
2199 #define	BZEBRA1_TRXCONTROL		0xc00
2200 #define	BZEBRA1_TRXGAINSETTING		0x07f
2201 #define	BZEBRA1_RXCOUNTER		0xc00
2202 #define	BZEBRA1_TXCHANGEPUMP		0x38
2203 #define	BZEBRA1_RXCHANGEPUMP		0x7
2204 #define	BZEBRA1_CHANNEL_NUM		0xf80
2205 #define	BZEBRA1_TXLPFBW			0x400
2206 #define	BZEBRA1_RXLPFBW			0x600
2208 #define	BRTL8256REG_MODE_CTRL1		0x100
2209 #define	BRTL8256REG_MODE_CTRL0		0x40
2210 #define	BRTL8256REG_TXLPFBW		0x18
2211 #define	BRTL8256REG_RXLPFBW		0x600
2213 #define	BRTL8258_TXLPFBW		0xc
2214 #define	BRTL8258_RXLPFBW		0xc00
2215 #define	BRTL8258_RSSILPFBW		0xc0
2217 #define	BBYTE0				0x1
2218 #define	BBYTE1				0x2
2219 #define	BBYTE2				0x4
2220 #define	BBYTE3				0x8
2221 #define	BWORD0				0x3
2222 #define	BWORD1				0xc
2223 #define	BWORD				0xf
2225 #define	MASKBYTE0			0xff
2226 #define	MASKBYTE1			0xff00
2227 #define	MASKBYTE2			0xff0000
2228 #define	MASKBYTE3			0xff000000
2229 #define	MASKHWORD			0xffff0000
2230 #define	MASKLWORD			0x0000ffff
2231 #define	MASKDWORD			0xffffffff
2232 #define	MASK12BITS			0xfff
2233 #define	MASKH4BITS			0xf0000000
2234 #define MASKOFDM_D			0xffc00000
2235 #define	MASKCCK				0x3f3f3f3f
2237 #define	MASK4BITS			0x0f
2238 #define	MASK20BITS			0xfffff
2239 #define RFREG_OFFSET_MASK		0xfffff
2241 #define	BENABLE				0x1
2242 #define	BDISABLE			0x0
2244 #define	LEFT_ANTENNA			0x0
2245 #define	RIGHT_ANTENNA			0x1
2250 #define	REG_UN_used_register		0x01bf
2253 #define	HAL92C_WOL_PTK_UPDATE_EVENT	BIT(0)
2259 #define		WOL_REASON_PTK_UPDATE		BIT(0)
2266 #define EFUSE_SEL(x)				(((x) & 0x3) << 8)
2267 #define EFUSE_SEL_MASK				0x300
2268 #define EFUSE_WIFI_SEL_0			0x0
2270 #define	WL_HWPDN_EN	BIT(0)	/* Enable GPIO[9] as WiFi HW PDn source*/