Lines Matching +full:0 +full:x0075
11 * 0: POFF--Power Off
43 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
47 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
48 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
50 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
52 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
55 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
56 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
59 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
60 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
63 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
64 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
65 /* wait till 0x04[17] = 1 power ready*/ \
66 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
69 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
71 /* release WLON reset 0x04[16]=1*/ \
72 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
74 /* disable HWPDN 0x04[15]=0*/ \
75 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
78 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
80 /* polling until return 0*/ \
81 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
83 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
84 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
86 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
92 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
95 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
97 /*Enable HSISR GPIO[C:0] interrupt*/ \
98 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
101 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
104 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
107 {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
114 /*0x1F[7:0] = 0 turn off RF*/ \
115 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
116 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
117 /*0x4C[24] = 0x4F[0] = 0, */ \
118 /*switch DPDT_SEL_P output from register 0x65[2] */ \
119 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
120 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
122 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
123 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
124 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
125 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
127 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
128 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
129 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
131 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
133 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
134 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
137 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
138 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
140 PWR_CMD_WRITE, BIT(0), 0},
146 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
147 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
149 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
150 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
153 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
154 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
156 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
157 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
159 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
160 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
163 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
164 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
166 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
167 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
174 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
177 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
178 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
180 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
182 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
183 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
184 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
185 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
186 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
193 /*0x07=0x20 , SOP option to disable BG/MB*/ \
194 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
196 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
200 /*0x04[10] = 1, enable SW LPS*/ \
201 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
203 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
204 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
206 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
207 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
210 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
211 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
213 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
214 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
221 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
224 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
225 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
227 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
229 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
230 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
232 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
233 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
234 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
235 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
236 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
237 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
239 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
246 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
247 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
249 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
250 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
252 PWR_CMD_WRITE, 0xFF, 0x20}, \
253 /* 0x04[16] = 0*/ \
254 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
255 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
256 /* 0x04[15] = 1*/ \
257 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
264 /* 0x04[15] = 0*/ \
265 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
273 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
274 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
276 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
279 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
280 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
282 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
283 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
285 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
286 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
288 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
289 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
291 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
294 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
295 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
297 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
300 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
303 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
304 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
306 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
309 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
317 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
318 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
320 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
321 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
323 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
324 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
326 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
327 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
328 /*. 0x08[4] = 0 switch TSF to 40M*/ \
329 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
330 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
331 /*Polling 0x109[7]=0 TSF in 40M*/ \
332 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
333 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
334 /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
335 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
336 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
337 /*. 0x101[1] = 1*/ \
338 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
340 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
341 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
342 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
343 /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
344 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
345 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
346 /*. 0x522 = 0*/ \
347 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
348 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
354 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
355 PWR_CMD_END, 0, 0},