Lines Matching +full:0 +full:x7000000
7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
17 #define REG_RF_CTRL 0x001F
18 #define REG_LDOA15_CTRL 0x0020
19 #define REG_LDOV12D_CTRL 0x0021
20 #define REG_LDOHCI12_CTRL 0x0022
21 #define REG_LPLDO_CTRL 0x0023
22 #define REG_AFE_XTAL_CTRL 0x0024
23 #define REG_AFE_PLL_CTRL 0x0028
24 #define REG_EFUSE_CTRL 0x0030
25 #define REG_EFUSE_TEST 0x0034
26 #define REG_PWR_DATA 0x0038
27 #define REG_CAL_TIMER 0x003C
28 #define REG_ACLK_MON 0x003E
29 #define REG_GPIO_MUXCFG 0x0040
30 #define REG_GPIO_IO_SEL 0x0042
31 #define REG_MAC_PINMUX_CFG 0x0043
32 #define REG_GPIO_PIN_CTRL 0x0044
33 #define REG_GPIO_INTM 0x0048
34 #define REG_LEDCFG0 0x004C
35 #define REG_LEDCFG1 0x004D
36 #define REG_LEDCFG2 0x004E
37 #define REG_LEDCFG3 0x004F
38 #define REG_FSIMR 0x0050
39 #define REG_FSISR 0x0054
40 #define REG_GPIO_PIN_CTRL_2 0x0060
41 #define REG_GPIO_IO_SEL_2 0x0062
42 #define REG_MULTI_FUNC_CTRL 0x0068
44 #define REG_MCUFWDL 0x0080
46 #define REG_HMEBOX_EXT_0 0x0088
47 #define REG_HMEBOX_EXT_1 0x008A
48 #define REG_HMEBOX_EXT_2 0x008C
49 #define REG_HMEBOX_EXT_3 0x008E
51 #define REG_BIST_SCAN 0x00D0
52 #define REG_BIST_RPT 0x00D4
53 #define REG_BIST_ROM_RPT 0x00D8
54 #define REG_USB_SIE_INTF 0x00E0
55 #define REG_PCIE_MIO_INTF 0x00E4
56 #define REG_PCIE_MIO_INTD 0x00E8
57 #define REG_SYS_CFG 0x00F0
58 #define REG_GPIO_OUTSTS 0x00F4
60 #define REG_CR 0x0100
61 #define REG_PBP 0x0104
62 #define REG_TRXDMA_CTRL 0x010C
63 #define REG_TRXFF_BNDY 0x0114
64 #define REG_TRXFF_STATUS 0x0118
65 #define REG_RXFF_PTR 0x011C
66 #define REG_HIMR 0x0120
67 #define REG_HISR 0x0124
68 #define REG_HIMRE 0x0128
69 #define REG_HISRE 0x012C
70 #define REG_CPWM 0x012F
71 #define REG_FWIMR 0x0130
72 #define REG_FWISR 0x0134
73 #define REG_PKTBUF_DBG_CTRL 0x0140
74 #define REG_PKTBUF_DBG_DATA_L 0x0144
75 #define REG_PKTBUF_DBG_DATA_H 0x0148
77 #define REG_TC0_CTRL 0x0150
78 #define REG_TC1_CTRL 0x0154
79 #define REG_TC2_CTRL 0x0158
80 #define REG_TC3_CTRL 0x015C
81 #define REG_TC4_CTRL 0x0160
82 #define REG_TCUNIT_BASE 0x0164
83 #define REG_MBIST_START 0x0174
84 #define REG_MBIST_DONE 0x0178
85 #define REG_MBIST_FAIL 0x017C
86 #define REG_C2HEVT_MSG_NORMAL 0x01A0
87 #define REG_C2HEVT_MSG_TEST 0x01B8
88 #define REG_MCUTST_1 0x01c0
89 #define REG_FMETHR 0x01C8
90 #define REG_HMETFR 0x01CC
91 #define REG_HMEBOX_0 0x01D0
92 #define REG_HMEBOX_1 0x01D4
93 #define REG_HMEBOX_2 0x01D8
94 #define REG_HMEBOX_3 0x01DC
96 #define REG_LLT_INIT 0x01E0
97 #define REG_BB_ACCEESS_CTRL 0x01E8
98 #define REG_BB_ACCESS_DATA 0x01EC
100 #define REG_RQPN 0x0200
101 #define REG_FIFOPAGE 0x0204
102 #define REG_TDECTRL 0x0208
103 #define REG_TXDMA_OFFSET_CHK 0x020C
104 #define REG_TXDMA_STATUS 0x0210
105 #define REG_RQPN_NPQ 0x0214
107 #define REG_RXDMA_AGG_PG_TH 0x0280
108 #define REG_RXPKT_NUM 0x0284
109 #define REG_RXDMA_STATUS 0x0288
111 #define REG_PCIE_CTRL_REG 0x0300
112 #define REG_INT_MIG 0x0304
113 #define REG_BCNQ_DESA 0x0308
114 #define REG_HQ_DESA 0x0310
115 #define REG_MGQ_DESA 0x0318
116 #define REG_VOQ_DESA 0x0320
117 #define REG_VIQ_DESA 0x0328
118 #define REG_BEQ_DESA 0x0330
119 #define REG_BKQ_DESA 0x0338
120 #define REG_RX_DESA 0x0340
121 #define REG_DBI 0x0348
122 #define REG_MDIO 0x0354
123 #define REG_DBG_SEL 0x0360
124 #define REG_PCIE_HRPWM 0x0361
125 #define REG_PCIE_HCPWM 0x0363
126 #define REG_UART_CTRL 0x0364
127 #define REG_UART_TX_DESA 0x0370
128 #define REG_UART_RX_DESA 0x0378
130 #define REG_HDAQ_DESA_NODEF 0x0000
131 #define REG_CMDQ_DESA_NODEF 0x0000
133 #define REG_VOQ_INFORMATION 0x0400
134 #define REG_VIQ_INFORMATION 0x0404
135 #define REG_BEQ_INFORMATION 0x0408
136 #define REG_BKQ_INFORMATION 0x040C
137 #define REG_MGQ_INFORMATION 0x0410
138 #define REG_HGQ_INFORMATION 0x0414
139 #define REG_BCNQ_INFORMATION 0x0418
141 #define REG_CPU_MGQ_INFORMATION 0x041C
142 #define REG_FWHW_TXQ_CTRL 0x0420
143 #define REG_HWSEQ_CTRL 0x0423
144 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
145 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
146 #define REG_MULTI_BCNQ_EN 0x0426
147 #define REG_MULTI_BCNQ_OFFSET 0x0427
148 #define REG_SPEC_SIFS 0x0428
149 #define REG_RL 0x042A
150 #define REG_DARFRC 0x0430
151 #define REG_RARFRC 0x0438
152 #define REG_RRSR 0x0440
153 #define REG_ARFR0 0x0444
154 #define REG_ARFR1 0x0448
155 #define REG_ARFR2 0x044C
156 #define REG_ARFR3 0x0450
157 #define REG_AGGLEN_LMT 0x0458
158 #define REG_AMPDU_MIN_SPACE 0x045C
159 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
160 #define REG_FAST_EDCA_CTRL 0x0460
161 #define REG_RD_RESP_PKT_TH 0x0463
162 #define REG_INIRTS_RATE_SEL 0x0480
163 #define REG_INIDATA_RATE_SEL 0x0484
164 #define REG_POWER_STATUS 0x04A4
165 #define REG_POWER_STAGE1 0x04B4
166 #define REG_POWER_STAGE2 0x04B8
167 #define REG_PKT_LIFE_TIME 0x04C0
168 #define REG_STBC_SETTING 0x04C4
169 #define REG_PROT_MODE_CTRL 0x04C8
170 #define REG_BAR_MODE_CTRL 0x04CC
171 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
172 #define REG_NQOS_SEQ 0x04DC
173 #define REG_QOS_SEQ 0x04DE
174 #define REG_NEED_CPU_HANDLE 0x04E0
175 #define REG_PKT_LOSE_RPT 0x04E1
176 #define REG_PTCL_ERR_STATUS 0x04E2
177 #define REG_DUMMY 0x04FC
179 #define REG_EDCA_VO_PARAM 0x0500
180 #define REG_EDCA_VI_PARAM 0x0504
181 #define REG_EDCA_BE_PARAM 0x0508
182 #define REG_EDCA_BK_PARAM 0x050C
183 #define REG_BCNTCFG 0x0510
184 #define REG_PIFS 0x0512
185 #define REG_RDG_PIFS 0x0513
186 #define REG_SIFS_CTX 0x0514
187 #define REG_SIFS_TRX 0x0516
188 #define REG_AGGR_BREAK_TIME 0x051A
189 #define REG_SLOT 0x051B
190 #define REG_TX_PTCL_CTRL 0x0520
191 #define REG_TXPAUSE 0x0522
192 #define REG_DIS_TXREQ_CLR 0x0523
193 #define REG_RD_CTRL 0x0524
194 #define REG_TBTT_PROHIBIT 0x0540
195 #define REG_RD_NAV_NXT 0x0544
196 #define REG_NAV_PROT_LEN 0x0546
197 #define REG_BCN_CTRL 0x0550
198 #define REG_MBID_NUM 0x0552
199 #define REG_DUAL_TSF_RST 0x0553
200 #define REG_BCN_INTERVAL 0x0554
201 #define REG_MBSSID_BCN_SPACE 0x0554
202 #define REG_DRVERLYINT 0x0558
203 #define REG_BCNDMATIM 0x0559
204 #define REG_ATIMWND 0x055A
205 #define REG_USTIME_TSF 0x055C
206 #define REG_BCN_MAX_ERR 0x055D
207 #define REG_RXTSF_OFFSET_CCK 0x055E
208 #define REG_RXTSF_OFFSET_OFDM 0x055F
209 #define REG_TSFTR 0x0560
210 #define REG_INIT_TSFTR 0x0564
211 #define REG_PSTIMER 0x0580
212 #define REG_TIMER0 0x0584
213 #define REG_TIMER1 0x0588
214 #define REG_ACMHWCTRL 0x05C0
215 #define REG_ACMRSTCTRL 0x05C1
216 #define REG_ACMAVG 0x05C2
217 #define REG_VO_ADMTIME 0x05C4
218 #define REG_VI_ADMTIME 0x05C6
219 #define REG_BE_ADMTIME 0x05C8
220 #define REG_EDCA_RANDOM_GEN 0x05CC
221 #define REG_SCH_TXCMD 0x05D0
223 #define REG_APSD_CTRL 0x0600
224 #define REG_BWOPMODE 0x0603
225 #define REG_TCR 0x0604
226 #define REG_RCR 0x0608
227 #define REG_RX_PKT_LIMIT 0x060C
228 #define REG_RX_DLK_TIME 0x060D
229 #define REG_RX_DRVINFO_SZ 0x060F
231 #define REG_MACID 0x0610
232 #define REG_BSSID 0x0618
233 #define REG_MAR 0x0620
234 #define REG_MBIDCAMCFG 0x0628
236 #define REG_USTIME_EDCA 0x0638
237 #define REG_MAC_SPEC_SIFS 0x063A
238 #define REG_RESP_SIFS_CCK 0x063C
239 #define REG_RESP_SIFS_OFDM 0x063E
240 #define REG_ACKTO 0x0640
241 #define REG_CTS2TO 0x0641
242 #define REG_EIFS 0x0642
244 #define REG_NAV_CTRL 0x0650
245 #define REG_BACAMCMD 0x0654
246 #define REG_BACAMCONTENT 0x0658
247 #define REG_LBDLY 0x0660
248 #define REG_FWDLY 0x0661
249 #define REG_RXERR_RPT 0x0664
250 #define REG_WMAC_TRXPTCL_CTL 0x0668
252 #define REG_CAMCMD 0x0670
253 #define REG_CAMWRITE 0x0674
254 #define REG_CAMREAD 0x0678
255 #define REG_CAMDBG 0x067C
256 #define REG_SECCFG 0x0680
258 #define REG_WOW_CTRL 0x0690
259 #define REG_PSSTATUS 0x0691
260 #define REG_PS_RX_INFO 0x0692
261 #define REG_LPNAV_CTRL 0x0694
262 #define REG_WKFMCAM_CMD 0x0698
263 #define REG_WKFMCAM_RWD 0x069C
264 #define REG_RXFLTMAP0 0x06A0
265 #define REG_RXFLTMAP1 0x06A2
266 #define REG_RXFLTMAP2 0x06A4
267 #define REG_BCN_PSR_RPT 0x06A8
268 #define REG_CALB32K_CTRL 0x06AC
269 #define REG_PKT_MON_CTRL 0x06B4
270 #define REG_BT_COEX_TABLE 0x06C0
271 #define REG_WMAC_RESP_TXINFO 0x06D8
273 #define REG_USB_INFO 0xFE17
274 #define REG_USB_SPECIAL_OPTION 0xFE55
275 #define REG_USB_DMA_AGG_TO 0xFE5B
276 #define REG_USB_AGG_TO 0xFE5C
277 #define REG_USB_AGG_TH 0xFE5D
279 #define REG_TEST_USB_TXQS 0xFE48
280 #define REG_TEST_SIE_VID 0xFE60
281 #define REG_TEST_SIE_PID 0xFE62
282 #define REG_TEST_SIE_OPTIONAL 0xFE64
283 #define REG_TEST_SIE_CHIRP_K 0xFE65
284 #define REG_TEST_SIE_PHY 0xFE66
285 #define REG_TEST_SIE_MAC_ADDR 0xFE70
286 #define REG_TEST_SIE_STRING 0xFE80
288 #define REG_NORMAL_SIE_VID 0xFE60
289 #define REG_NORMAL_SIE_PID 0xFE62
290 #define REG_NORMAL_SIE_OPTIONAL 0xFE64
291 #define REG_NORMAL_SIE_EP 0xFE65
292 #define REG_NORMAL_SIE_PHY 0xFE68
293 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70
294 #define REG_NORMAL_SIE_STRING 0xFE80
309 #define UNUSED_REGISTER 0x1BF
315 #define INVALID_BBRF_VALUE 0x12345678
317 #define MAX_MSS_DENSITY_2T 0x13
318 #define MAX_MSS_DENSITY_1T 0x0A
326 #define GPIOSEL_GPIO 0
334 #define MSR_NOLINK 0x00
335 #define MSR_ADHOC 0x01
336 #define MSR_INFRA 0x02
337 #define MSR_AP 0x03
341 #define RRSR_RSC_BW_40M 0x600000
342 #define RRSR_RSC_UPSUBCHNL 0x400000
343 #define RRSR_RSC_LOWSUBCHNL 0x200000
344 #define RRSR_SHORT 0x800000
345 #define RRSR_1M BIT(0)
367 #define RATR_1M 0x00000001
368 #define RATR_2M 0x00000002
369 #define RATR_55M 0x00000004
370 #define RATR_11M 0x00000008
371 #define RATR_6M 0x00000010
372 #define RATR_9M 0x00000020
373 #define RATR_12M 0x00000040
374 #define RATR_18M 0x00000080
375 #define RATR_24M 0x00000100
376 #define RATR_36M 0x00000200
377 #define RATR_48M 0x00000400
378 #define RATR_54M 0x00000800
379 #define RATR_MCS0 0x00001000
380 #define RATR_MCS1 0x00002000
381 #define RATR_MCS2 0x00004000
382 #define RATR_MCS3 0x00008000
383 #define RATR_MCS4 0x00010000
384 #define RATR_MCS5 0x00020000
385 #define RATR_MCS6 0x00040000
386 #define RATR_MCS7 0x00080000
387 #define RATR_MCS8 0x00100000
388 #define RATR_MCS9 0x00200000
389 #define RATR_MCS10 0x00400000
390 #define RATR_MCS11 0x00800000
391 #define RATR_MCS12 0x01000000
392 #define RATR_MCS13 0x02000000
393 #define RATR_MCS14 0x04000000
394 #define RATR_MCS15 0x08000000
396 #define RATE_1M BIT(0)
437 #define BW_OPMODE_11J BIT(0)
440 #define CAM_NOTVALID 0x0000
443 #define CAM_NONE 0x0
444 #define CAM_WEP40 0x01
445 #define CAM_TKIP 0x02
446 #define CAM_AES 0x04
447 #define CAM_WEP104 0x05
453 #define CAM_READ 0x00000000
456 #define SCR_USEDK 0x01
457 #define SCR_TXSEC_ENABLE 0x02
458 #define SCR_RXSEC_ENABLE 0x04
460 #define WOW_PMEN BIT(0)
465 #define IMR8190_DISABLED 0x0
497 #define IMR_ROK BIT(0)
503 #define IMR_WLANOFF BIT(0)
506 /* IMR DW0 Bit 0-31 */
538 #define PHIMR_ROK BIT(0)
562 #define EEPROM_DEFAULT_TSSI 0x0
563 #define EEPROM_DEFAULT_TXPOWERDIFF 0x0
564 #define EEPROM_DEFAULT_CRYSTALCAP 0x5
565 #define EEPROM_DEFAULT_BOARDTYPE 0x02
566 #define EEPROM_DEFAULT_TXPOWER 0x1010
567 #define EEPROM_DEFAULT_HT2T_TXPWR 0x10
569 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
570 #define EEPROM_DEFAULT_THERMALMETER 0x12
571 #define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
572 #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
573 #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
574 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0
576 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
577 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
578 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
580 #define EEPROM_DEFAULT_PID 0x1234
581 #define EEPROM_DEFAULT_VID 0x5678
582 #define EEPROM_DEFAULT_CUSTOMERID 0xAB
583 #define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
584 #define EEPROM_DEFAULT_VERSION 0
586 #define EEPROM_CHANNEL_PLAN_FCC 0x0
587 #define EEPROM_CHANNEL_PLAN_IC 0x1
588 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
589 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
590 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
591 #define EEPROM_CHANNEL_PLAN_MKK 0x5
592 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
593 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
594 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
595 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
596 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
597 #define EEPROM_CHANNEL_PLAN_NCC 0xB
598 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
600 #define EEPROM_CID_DEFAULT 0x0
601 #define EEPROM_CID_TOSHIBA 0x4
602 #define EEPROM_CID_CCX 0x10
603 #define EEPROM_CID_QMI 0x0D
604 #define EEPROM_CID_WHQL 0xFE
606 #define RTL8192_EEPROM_ID 0x8129
608 #define RTL8190_EEPROM_ID 0x8129
609 #define EEPROM_HPON 0x02
610 #define EEPROM_CLK 0x06
611 #define EEPROM_TESTR 0x08
613 #define EEPROM_VID 0x49
614 #define EEPROM_DID 0x4B
615 #define EEPROM_SVID 0x4D
616 #define EEPROM_SMID 0x4F
618 #define EEPROM_MAC_ADDR 0x67
620 #define EEPROM_CCK_TX_PWR_INX 0x5A
621 #define EEPROM_HT40_1S_TX_PWR_INX 0x60
622 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
623 #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
624 #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
625 #define EEPROM_HT40_MAX_PWR_OFFSET 0x25
626 #define EEPROM_HT20_MAX_PWR_OFFSET 0x22
628 #define EEPROM_THERMAL_METER 0x2a
629 #define EEPROM_XTAL_K 0x78
630 #define EEPROM_RF_OPT1 0x79
631 #define EEPROM_RF_OPT2 0x7A
632 #define EEPROM_RF_OPT3 0x7B
633 #define EEPROM_RF_OPT4 0x7C
634 #define EEPROM_CHANNEL_PLAN 0x28
635 #define EEPROM_VERSION 0x30
636 #define EEPROM_CUSTOMER_ID 0x31
638 #define EEPROM_PWRDIFF 0x54
640 #define EEPROM_TXPOWERCCK 0x10
641 #define EEPROM_TXPOWERHT40_1S 0x16
642 #define EEPROM_TXPOWERHT40_2SDIFF 0x66
643 #define EEPROM_TXPOWERHT20DIFF 0x1C
644 #define EEPROM_TXPOWER_OFDMDIFF 0x1F
646 #define EEPROM_TXPWR_GROUP 0x22
648 #define EEPROM_TSSI_A 0x29
649 #define EEPROM_TSSI_B 0x77
651 #define EEPROM_CHANNELPLAN 0x28
653 #define RF_OPTION1 0x2B
654 #define RF_OPTION2 0x2C
655 #define RF_OPTION3 0x2D
656 #define RF_OPTION4 0x2E
664 #define STOPBK BIT(0)
688 #define RCR_AAP BIT(0)
692 #define RSV_CTRL 0x001C
693 #define RD_CTRL 0x0524
695 #define REG_USB_INFO 0xFE17
696 #define REG_USB_SPECIAL_OPTION 0xFE55
697 #define REG_USB_DMA_AGG_TO 0xFE5B
698 #define REG_USB_AGG_TO 0xFE5C
699 #define REG_USB_AGG_TH 0xFE5D
701 #define REG_USB_VID 0xFE60
702 #define REG_USB_PID 0xFE62
703 #define REG_USB_OPTIONAL 0xFE64
704 #define REG_USB_CHIRP_K 0xFE65
705 #define REG_USB_PHY 0xFE66
706 #define REG_USB_MAC_ADDR 0xFE70
707 #define REG_USB_HRPWM 0xFE58
708 #define REG_USB_HCPWM 0xFE57
712 #define ISO_MD2PP BIT(0)
726 #define FEN_BBRSTB BIT(0)
743 #define PFM_LDALL BIT(0)
770 #define ANAD16V_EN BIT(0)
785 #define AFE_BGEN BIT(0)
789 #define WLOCK_ALL BIT(0)
798 #define RF_EN BIT(0)
802 #define LDA15_EN BIT(0)
806 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
808 #define LDV12_EN BIT(0)
812 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
814 #define XTAL_EN BIT(0)
816 #define _XTAL_BOSC(x) (((x) & 0x3) << 2)
817 #define _XTAL_CADJ(x) (((x) & 0xF) << 4)
819 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
821 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
823 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
825 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
827 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
828 #define _XTAL_GPIO(x) (((x) & 0x7) << 23)
835 #define APLL_EN BIT(0)
842 #define APLL_REF_CLK_13MHZ 0x1
843 #define APLL_REF_CLK_19_2MHZ 0x2
844 #define APLL_REF_CLK_20MHZ 0x3
845 #define APLL_REF_CLK_25MHZ 0x4
846 #define APLL_REF_CLK_26MHZ 0x5
847 #define APLL_REF_CLK_38_4MHZ 0x6
848 #define APLL_REF_CLK_40MHZ 0x7
861 #define RSM_EN BIT(0)
881 #define MCUFWDL_EN BIT(0)
890 #define XCLK_VLD BIT(0)
910 #define CHIP_VER_RTL_MASK 0xF000
915 #define HCI_TXDMA_EN BIT(0)
926 #define _NETTYPE(x) (((x) & 0x3) << 16)
927 #define MASK_NETTYPE 0x30000
928 #define NT_NO_LINK 0x0
929 #define NT_LINK_AD_HOC 0x1
930 #define NT_LINK_AP 0x2
931 #define NT_AS_AP 0x3
933 #define _LBMODE(x) (((x) & 0xF) << 24)
934 #define MASK_LBMODE 0xF000000
935 #define LOOPBACK_NORMAL 0x0
936 #define LOOPBACK_IMMEDIATELY 0xB
937 #define LOOPBACK_MAC_DELAY 0x3
938 #define LOOPBACK_PHY 0x1
939 #define LOOPBACK_DMA 0x7
941 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
942 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
943 #define _PSRX_MASK 0xF
944 #define _PSTX_MASK 0xF0
948 #define PBP_64 0x0
949 #define PBP_128 0x1
950 #define PBP_256 0x2
951 #define PBP_512 0x3
952 #define PBP_1024 0x4
954 #define RXDMA_ARBBW_EN BIT(0)
964 #define HQSEL_VOQ BIT(0)
971 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
972 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
973 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
974 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
975 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
976 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
982 #define _LLT_NO_ACTIVE 0x0
983 #define _LLT_WRITE_ACCESS 0x1
984 #define _LLT_READ_ACCESS 0x2
986 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
987 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
988 #define _LLT_OP(x) (((x) & 0x3) << 30)
989 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
995 #define _HPQ(x) ((x) & 0xFF)
996 #define _LPQ(x) (((x) & 0xFF) << 8)
997 #define _PUBQ(x) (((x) & 0xFF) << 16)
998 #define _NPQ(x) ((x) & 0xFF)
1005 #define BCN_HEAD(x) (((x) & 0xFF) << 8)
1006 #define BCN_HEAD_MASK 0xFF00
1009 #define BLK_DESC_NUM_MASK 0xF
1015 #define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1017 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1018 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1020 #define RATE_REG_BITMAP_ALL 0xFFFFF
1022 #define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1024 #define _RRSR_RSC(x) (((x) & 0x3) << 21)
1025 #define RRSR_RSC_RESERVED 0x0
1026 #define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1027 #define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1028 #define RRSR_RSC_DUPLICATE_MODE 0x3
1032 #define _AGGLMT_MCS0(x) ((x) & 0xF)
1033 #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1034 #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1035 #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1036 #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1037 #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1038 #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1039 #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1042 #define RETRY_LIMIT_LONG_SHIFT 0
1044 #define _DARF_RC1(x) ((x) & 0x1F)
1045 #define _DARF_RC2(x) (((x) & 0x1F) << 8)
1046 #define _DARF_RC3(x) (((x) & 0x1F) << 16)
1047 #define _DARF_RC4(x) (((x) & 0x1F) << 24)
1048 #define _DARF_RC5(x) ((x) & 0x1F)
1049 #define _DARF_RC6(x) (((x) & 0x1F) << 8)
1050 #define _DARF_RC7(x) (((x) & 0x1F) << 16)
1051 #define _DARF_RC8(x) (((x) & 0x1F) << 24)
1053 #define _RARF_RC1(x) ((x) & 0x1F)
1054 #define _RARF_RC2(x) (((x) & 0x1F) << 8)
1055 #define _RARF_RC3(x) (((x) & 0x1F) << 16)
1056 #define _RARF_RC4(x) (((x) & 0x1F) << 24)
1057 #define _RARF_RC5(x) ((x) & 0x1F)
1058 #define _RARF_RC6(x) (((x) & 0x1F) << 8)
1059 #define _RARF_RC7(x) (((x) & 0x1F) << 16)
1060 #define _RARF_RC8(x) (((x) & 0x1F) << 24)
1065 #define AC_PARAM_AIFS_OFFSET 0
1071 #define _BCNIFS(x) ((x) & 0xFF)
1072 #define _BCNECW(x) ((((x) & 0xF)) << 8)
1074 #define _LRL(x) ((x) & 0x3F)
1075 #define _SRL(x) (((x) & 0x3F) << 8)
1077 #define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1078 #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
1080 #define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1081 #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
1083 #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1091 #define TSFTR_RST BIT(0)
1099 #define ACMHW_HWEN BIT(0)
1112 #define RATE_BITMAP_ALL 0xFFFFF
1114 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1116 #define TSFRST BIT(0)
1125 #define AAP BIT(0)
1151 #define _MIN_SPACE(x) ((x) & 0x7)
1152 #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1154 #define RXERR_TYPE_OFDM_PPDU 0
1169 #define RXERR_COUNTER_MASK 0xFFFFF
1173 #define SCR_TXUSEDK BIT(0)
1182 #define USB_IS_HIGH_SPEED 0
1186 #define USB_NORMAL_SIE_EP_MASK 0xF
1189 #define USB_TEST_EP_MASK 0x30
1200 #define MAX_MSS_DENSITY_2T 0x13
1201 #define MAX_MSS_DENSITY_1T 0x0A
1204 #define EPROM_CMD_CONFIG 0x3
1211 #define RPMAC_RESET 0x100
1212 #define RPMAC_TXSTART 0x104
1213 #define RPMAC_TXLEGACYSIG 0x108
1214 #define RPMAC_TXHTSIG1 0x10c
1215 #define RPMAC_TXHTSIG2 0x110
1216 #define RPMAC_PHYDEBUG 0x114
1217 #define RPMAC_TXPACKETNUM 0x118
1218 #define RPMAC_TXIDLE 0x11c
1219 #define RPMAC_TXMACHEADER0 0x120
1220 #define RPMAC_TXMACHEADER1 0x124
1221 #define RPMAC_TXMACHEADER2 0x128
1222 #define RPMAC_TXMACHEADER3 0x12c
1223 #define RPMAC_TXMACHEADER4 0x130
1224 #define RPMAC_TXMACHEADER5 0x134
1225 #define RPMAC_TXDADATYPE 0x138
1226 #define RPMAC_TXRANDOMSEED 0x13c
1227 #define RPMAC_CCKPLCPPREAMBLE 0x140
1228 #define RPMAC_CCKPLCPHEADER 0x144
1229 #define RPMAC_CCKCRC16 0x148
1230 #define RPMAC_OFDMRXCRC32OK 0x170
1231 #define RPMAC_OFDMRXCRC32ER 0x174
1232 #define RPMAC_OFDMRXPARITYER 0x178
1233 #define RPMAC_OFDMRXCRC8ER 0x17c
1234 #define RPMAC_CCKCRXRC16ER 0x180
1235 #define RPMAC_CCKCRXRC32ER 0x184
1236 #define RPMAC_CCKCRXRC32OK 0x188
1237 #define RPMAC_TXSTATUS 0x18c
1239 #define RFPGA0_RFMOD 0x800
1241 #define RFPGA0_TXINFO 0x804
1242 #define RFPGA0_PSDFUNCTION 0x808
1244 #define RFPGA0_TXGAINSTAGE 0x80c
1246 #define RFPGA0_RFTIMING1 0x810
1247 #define RFPGA0_RFTIMING2 0x814
1249 #define RFPGA0_XA_HSSIPARAMETER1 0x820
1250 #define RFPGA0_XA_HSSIPARAMETER2 0x824
1251 #define RFPGA0_XB_HSSIPARAMETER1 0x828
1252 #define RFPGA0_XB_HSSIPARAMETER2 0x82c
1254 #define RFPGA0_XA_LSSIPARAMETER 0x840
1255 #define RFPGA0_XB_LSSIPARAMETER 0x844
1257 #define RFPGA0_RFWAKEUPPARAMETER 0x850
1258 #define RFPGA0_RFSLEEPUPPARAMETER 0x854
1260 #define RFPGA0_XAB_SWITCHCONTROL 0x858
1261 #define RFPGA0_XCD_SWITCHCONTROL 0x85c
1263 #define RFPGA0_XA_RFINTERFACEOE 0x860
1264 #define RFPGA0_XB_RFINTERFACEOE 0x864
1266 #define RFPGA0_XAB_RFINTERFACESW 0x870
1267 #define RFPGA0_XCD_RFINTERFACESW 0x874
1269 #define RFPGA0_XAB_RFPARAMETER 0x878
1270 #define RFPGA0_XCD_RFPARAMETER 0x87c
1272 #define RFPGA0_ANALOGPARAMETER1 0x880
1273 #define RFPGA0_ANALOGPARAMETER2 0x884
1274 #define RFPGA0_ANALOGPARAMETER3 0x888
1275 #define RFPGA0_ANALOGPARAMETER4 0x88c
1277 #define RFPGA0_XA_LSSIREADBACK 0x8a0
1278 #define RFPGA0_XB_LSSIREADBACK 0x8a4
1279 #define RFPGA0_XC_LSSIREADBACK 0x8a8
1280 #define RFPGA0_XD_LSSIREADBACK 0x8ac
1282 #define RFPGA0_PSDREPORT 0x8b4
1283 #define TRANSCEIVEA_HSPI_READBACK 0x8b8
1284 #define TRANSCEIVEB_HSPI_READBACK 0x8bc
1285 #define RFPGA0_XAB_RFINTERFACERB 0x8e0
1286 #define RFPGA0_XCD_RFINTERFACERB 0x8e4
1288 #define RFPGA1_RFMOD 0x900
1290 #define RFPGA1_TXBLOCK 0x904
1291 #define RFPGA1_DEBUGSELECT 0x908
1292 #define RFPGA1_TXINFO 0x90c
1294 #define RCCK0_SYSTEM 0xa00
1296 #define RCCK0_AFESETTING 0xa04
1297 #define RCCK0_CCA 0xa08
1299 #define RCCK0_RXAGC1 0xa0c
1300 #define RCCK0_RXAGC2 0xa10
1302 #define RCCK0_RXHP 0xa14
1304 #define RCCK0_DSPPARAMETER1 0xa18
1305 #define RCCK0_DSPPARAMETER2 0xa1c
1307 #define RCCK0_TXFILTER1 0xa20
1308 #define RCCK0_TXFILTER2 0xa24
1309 #define RCCK0_DEBUGPORT 0xa28
1310 #define RCCK0_FALSEALARMREPORT 0xa2c
1311 #define RCCK0_TRSSIREPORT 0xa50
1312 #define RCCK0_RXREPORT 0xa54
1313 #define RCCK0_FACOUNTERLOWER 0xa5c
1314 #define RCCK0_FACOUNTERUPPER 0xa58
1316 #define ROFDM0_LSTF 0xc00
1318 #define ROFDM0_TRXPATHENABLE 0xc04
1319 #define ROFDM0_TRMUXPAR 0xc08
1320 #define ROFDM0_TRSWISOLATION 0xc0c
1322 #define ROFDM0_XARXAFE 0xc10
1323 #define ROFDM0_XARXIQIMBALANCE 0xc14
1324 #define ROFDM0_XBRXAFE 0xc18
1325 #define ROFDM0_XBRXIQIMBALANCE 0xc1c
1326 #define ROFDM0_XCRXAFE 0xc20
1327 #define ROFDM0_XCRXIQIMBANLANCE 0xc24
1328 #define ROFDM0_XDRXAFE 0xc28
1329 #define ROFDM0_XDRXIQIMBALANCE 0xc2c
1331 #define ROFDM0_RXDETECTOR1 0xc30
1332 #define ROFDM0_RXDETECTOR2 0xc34
1333 #define ROFDM0_RXDETECTOR3 0xc38
1334 #define ROFDM0_RXDETECTOR4 0xc3c
1336 #define ROFDM0_RXDSP 0xc40
1337 #define ROFDM0_CFOANDDAGC 0xc44
1338 #define ROFDM0_CCADROPTHRESHOLD 0xc48
1339 #define ROFDM0_ECCATHRESHOLD 0xc4c
1341 #define ROFDM0_XAAGCCORE1 0xc50
1342 #define ROFDM0_XAAGCCORE2 0xc54
1343 #define ROFDM0_XBAGCCORE1 0xc58
1344 #define ROFDM0_XBAGCCORE2 0xc5c
1345 #define ROFDM0_XCAGCCORE1 0xc60
1346 #define ROFDM0_XCAGCCORE2 0xc64
1347 #define ROFDM0_XDAGCCORE1 0xc68
1348 #define ROFDM0_XDAGCCORE2 0xc6c
1350 #define ROFDM0_AGCPARAMETER1 0xc70
1351 #define ROFDM0_AGCPARAMETER2 0xc74
1352 #define ROFDM0_AGCRSSITABLE 0xc78
1353 #define ROFDM0_HTSTFAGC 0xc7c
1355 #define ROFDM0_XATXIQIMBALANCE 0xc80
1356 #define ROFDM0_XATXAFE 0xc84
1357 #define ROFDM0_XBTXIQIMBALANCE 0xc88
1358 #define ROFDM0_XBTXAFE 0xc8c
1359 #define ROFDM0_XCTXIQIMBALANCE 0xc90
1360 #define ROFDM0_XCTXAFE 0xc94
1361 #define ROFDM0_XDTXIQIMBALANCE 0xc98
1362 #define ROFDM0_XDTXAFE 0xc9c
1364 #define ROFDM0_RXIQEXTANTA 0xca0
1366 #define ROFDM0_RXHPPARAMETER 0xce0
1367 #define ROFDM0_TXPSEUDONOISEWGT 0xce4
1368 #define ROFDM0_FRAMESYNC 0xcf0
1369 #define ROFDM0_DFSREPORT 0xcf4
1370 #define ROFDM0_TXCOEFF1 0xca4
1371 #define ROFDM0_TXCOEFF2 0xca8
1372 #define ROFDM0_TXCOEFF3 0xcac
1373 #define ROFDM0_TXCOEFF4 0xcb0
1374 #define ROFDM0_TXCOEFF5 0xcb4
1375 #define ROFDM0_TXCOEFF6 0xcb8
1377 #define ROFDM1_LSTF 0xd00
1378 #define ROFDM1_TRXPATHENABLE 0xd04
1380 #define ROFDM1_CF0 0xd08
1381 #define ROFDM1_CSI1 0xd10
1382 #define ROFDM1_SBD 0xd14
1383 #define ROFDM1_CSI2 0xd18
1384 #define ROFDM1_CFOTRACKING 0xd2c
1385 #define ROFDM1_TRXMESAURE1 0xd34
1386 #define ROFDM1_INTFDET 0xd3c
1387 #define ROFDM1_PSEUDONOISESTATEAB 0xd50
1388 #define ROFDM1_PSEUDONOISESTATECD 0xd54
1389 #define ROFDM1_RXPSEUDONOISEWGT 0xd58
1391 #define ROFDM_PHYCOUNTER1 0xda0
1392 #define ROFDM_PHYCOUNTER2 0xda4
1393 #define ROFDM_PHYCOUNTER3 0xda8
1395 #define ROFDM_SHORTCFOAB 0xdac
1396 #define ROFDM_SHORTCFOCD 0xdb0
1397 #define ROFDM_LONGCFOAB 0xdb4
1398 #define ROFDM_LONGCFOCD 0xdb8
1399 #define ROFDM_TAILCF0AB 0xdbc
1400 #define ROFDM_TAILCF0CD 0xdc0
1401 #define ROFDM_PWMEASURE1 0xdc4
1402 #define ROFDM_PWMEASURE2 0xdc8
1403 #define ROFDM_BWREPORT 0xdcc
1404 #define ROFDM_AGCREPORT 0xdd0
1405 #define ROFDM_RXSNR 0xdd4
1406 #define ROFDM_RXEVMCSI 0xdd8
1407 #define ROFDM_SIGREPORT 0xddc
1409 #define RTXAGC_A_RATE18_06 0xe00
1410 #define RTXAGC_A_RATE54_24 0xe04
1411 #define RTXAGC_A_CCK1_MCS32 0xe08
1412 #define RTXAGC_A_MCS03_MCS00 0xe10
1413 #define RTXAGC_A_MCS07_MCS04 0xe14
1414 #define RTXAGC_A_MCS11_MCS08 0xe18
1415 #define RTXAGC_A_MCS15_MCS12 0xe1c
1417 #define RTXAGC_B_RATE18_06 0x830
1418 #define RTXAGC_B_RATE54_24 0x834
1419 #define RTXAGC_B_CCK1_55_MCS32 0x838
1420 #define RTXAGC_B_MCS03_MCS00 0x83c
1421 #define RTXAGC_B_MCS07_MCS04 0x848
1422 #define RTXAGC_B_MCS11_MCS08 0x84c
1423 #define RTXAGC_B_MCS15_MCS12 0x868
1424 #define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1426 #define RZEBRA1_HSSIENABLE 0x0
1427 #define RZEBRA1_TRXENABLE1 0x1
1428 #define RZEBRA1_TRXENABLE2 0x2
1429 #define RZEBRA1_AGC 0x4
1430 #define RZEBRA1_CHARGEPUMP 0x5
1431 #define RZEBRA1_CHANNEL 0x7
1433 #define RZEBRA1_TXGAIN 0x8
1434 #define RZEBRA1_TXLPF 0x9
1435 #define RZEBRA1_RXLPF 0xb
1436 #define RZEBRA1_RXHPFCORNER 0xc
1438 #define RGLOBALCTRL 0
1441 #define RRTL8258_TXLPF 0x11
1442 #define RRTL8258_RXLPF 0x13
1443 #define RRTL8258_RSSILPF 0xa
1445 #define RF_AC 0x00
1447 #define RF_IQADJ_G1 0x01
1448 #define RF_IQADJ_G2 0x02
1449 #define RF_POW_TRSW 0x05
1451 #define RF_GAIN_RX 0x06
1452 #define RF_GAIN_TX 0x07
1454 #define RF_TXM_IDAC 0x08
1455 #define RF_BS_IQGEN 0x0F
1457 #define RF_MODE1 0x10
1458 #define RF_MODE2 0x11
1460 #define RF_RX_AGC_HP 0x12
1461 #define RF_TX_AGC 0x13
1462 #define RF_BIAS 0x14
1463 #define RF_IPA 0x15
1464 #define RF_POW_ABILITY 0x17
1465 #define RF_MODE_AG 0x18
1466 #define RRFCHANNEL 0x18
1467 #define RF_CHNLBW 0x18
1468 #define RF_TOP 0x19
1470 #define RF_RX_G1 0x1A
1471 #define RF_RX_G2 0x1B
1473 #define RF_RX_BB2 0x1C
1474 #define RF_RX_BB1 0x1D
1476 #define RF_RCK1 0x1E
1477 #define RF_RCK2 0x1F
1479 #define RF_TX_G1 0x20
1480 #define RF_TX_G2 0x21
1481 #define RF_TX_G3 0x22
1483 #define RF_TX_BB1 0x23
1484 #define RF_T_METER 0x24
1486 #define RF_SYN_G1 0x25
1487 #define RF_SYN_G2 0x26
1488 #define RF_SYN_G3 0x27
1489 #define RF_SYN_G4 0x28
1490 #define RF_SYN_G5 0x29
1491 #define RF_SYN_G6 0x2A
1492 #define RF_SYN_G7 0x2B
1493 #define RF_SYN_G8 0x2C
1495 #define RF_RCK_OS 0x30
1496 #define RF_TXPA_G1 0x31
1497 #define RF_TXPA_G2 0x32
1498 #define RF_TXPA_G3 0x33
1500 #define BBBRESETB 0x100
1501 #define BGLOBALRESETB 0x200
1502 #define BOFDMTXSTART 0x4
1503 #define BCCKTXSTART 0x8
1504 #define BCRC32DEBUG 0x100
1505 #define BPMACLOOPBACK 0x10
1506 #define BTXLSIG 0xffffff
1507 #define BOFDMTXRATE 0xf
1508 #define BOFDMTXRESERVED 0x10
1509 #define BOFDMTXLENGTH 0x1ffe0
1510 #define BOFDMTXPARITY 0x20000
1511 #define BTXHTSIG1 0xffffff
1512 #define BTXHTMCSRATE 0x7f
1513 #define BTXHTBW 0x80
1514 #define BTXHTLENGTH 0xffff00
1515 #define BTXHTSIG2 0xffffff
1516 #define BTXHTSMOOTHING 0x1
1517 #define BTXHTSOUNDING 0x2
1518 #define BTXHTRESERVED 0x4
1519 #define BTXHTAGGREATION 0x8
1520 #define BTXHTSTBC 0x30
1521 #define BTXHTADVANCECODING 0x40
1522 #define BTXHTSHORTGI 0x80
1523 #define BTXHTNUMBERHT_LTF 0x300
1524 #define BTXHTCRC8 0x3fc00
1525 #define BCOUNTERRESET 0x10000
1526 #define BNUMOFOFDMTX 0xffff
1527 #define BNUMOFCCKTX 0xffff0000
1528 #define BTXIDLEINTERVAL 0xffff
1529 #define BOFDMSERVICE 0xffff0000
1530 #define BTXMACHEADER 0xffffffff
1531 #define BTXDATAINIT 0xff
1532 #define BTXHTMODE 0x100
1533 #define BTXDATATYPE 0x30000
1534 #define BTXRANDOMSEED 0xffffffff
1535 #define BCCKTXPREAMBLE 0x1
1536 #define BCCKTXSFD 0xffff0000
1537 #define BCCKTXSIG 0xff
1538 #define BCCKTXSERVICE 0xff00
1539 #define BCCKLENGTHEXT 0x8000
1540 #define BCCKTXLENGHT 0xffff0000
1541 #define BCCKTXCRC16 0xffff
1542 #define BCCKTXSTATUS 0x1
1543 #define BOFDMTXSTATUS 0x2
1545 ((_offset >= 0x800) && (_offset <= 0xfff))
1547 #define BRFMOD 0x1
1548 #define BJAPANMODE 0x2
1549 #define BCCKTXSC 0x30
1550 #define BCCKEN 0x1000000
1551 #define BOFDMEN 0x2000000
1553 #define BOFDMRXADCPHASE 0x10000
1554 #define BOFDMTXDACPHASE 0x40000
1555 #define BXATXAGC 0x3f
1557 #define BXBTXAGC 0xf00
1558 #define BXCTXAGC 0xf000
1559 #define BXDTXAGC 0xf0000
1561 #define BPASTART 0xf0000000
1562 #define BTRSTART 0x00f00000
1563 #define BRFSTART 0x0000f000
1564 #define BBBSTART 0x000000f0
1565 #define BBBCCKSTART 0x0000000f
1566 #define BPAEND 0xf
1567 #define BTREND 0x0f000000
1568 #define BRFEND 0x000f0000
1569 #define BCCAMASK 0x000000f0
1570 #define BR2RCCAMASK 0x00000f00
1571 #define BHSSI_R2TDELAY 0xf8000000
1572 #define BHSSI_T2RDELAY 0xf80000
1573 #define BCONTXHSSI 0x400
1574 #define BIGFROMCCK 0x200
1575 #define BAGCADDRESS 0x3f
1576 #define BRXHPTX 0x7000
1577 #define BRXHP2RX 0x38000
1578 #define BRXHPCCKINI 0xc0000
1579 #define BAGCTXCODE 0xc00000
1580 #define BAGCRXCODE 0x300000
1582 #define B3WIREDATALENGTH 0x800
1583 #define B3WIREADDREAALENGTH 0x400
1585 #define B3WIRERFPOWERDOWN 0x1
1586 #define B5GPAPEPOLARITY 0x40000000
1587 #define B2GPAPEPOLARITY 0x80000000
1588 #define BRFSW_TXDEFAULTANT 0x3
1589 #define BRFSW_TXOPTIONANT 0x30
1590 #define BRFSW_RXDEFAULTANT 0x300
1591 #define BRFSW_RXOPTIONANT 0x3000
1592 #define BRFSI_3WIREDATA 0x1
1593 #define BRFSI_3WIRECLOCK 0x2
1594 #define BRFSI_3WIRELOAD 0x4
1595 #define BRFSI_3WIRERW 0x8
1596 #define BRFSI_3WIRE 0xf
1598 #define BRFSI_RFENV 0x10
1600 #define BRFSI_TRSW 0x20
1601 #define BRFSI_TRSWB 0x40
1602 #define BRFSI_ANTSW 0x100
1603 #define BRFSI_ANTSWB 0x200
1604 #define BRFSI_PAPE 0x400
1605 #define BRFSI_PAPE5G 0x800
1606 #define BBANDSELECT 0x1
1607 #define BHTSIG2_GI 0x80
1608 #define BHTSIG2_SMOOTHING 0x01
1609 #define BHTSIG2_SOUNDING 0x02
1610 #define BHTSIG2_AGGREATON 0x08
1611 #define BHTSIG2_STBC 0x30
1612 #define BHTSIG2_ADVCODING 0x40
1613 #define BHTSIG2_NUMOFHTLTF 0x300
1614 #define BHTSIG2_CRC8 0x3fc
1615 #define BHTSIG1_MCS 0x7f
1616 #define BHTSIG1_BANDWIDTH 0x80
1617 #define BHTSIG1_HTLENGTH 0xffff
1618 #define BLSIG_RATE 0xf
1619 #define BLSIG_RESERVED 0x10
1620 #define BLSIG_LENGTH 0x1fffe
1621 #define BLSIG_PARITY 0x20
1622 #define BCCKRXPHASE 0x4
1624 #define BLSSIREADADDRESS 0x7f800000
1625 #define BLSSIREADEDGE 0x80000000
1627 #define BLSSIREADBACKDATA 0xfffff
1629 #define BLSSIREADOKFLAG 0x1000
1630 #define BCCKSAMPLERATE 0x8
1631 #define BREGULATOR0STANDBY 0x1
1632 #define BREGULATORPLLSTANDBY 0x2
1633 #define BREGULATOR1STANDBY 0x4
1634 #define BPLLPOWERUP 0x8
1635 #define BDPLLPOWERUP 0x10
1636 #define BDA10POWERUP 0x20
1637 #define BAD7POWERUP 0x200
1638 #define BDA6POWERUP 0x2000
1639 #define BXTALPOWERUP 0x4000
1640 #define B40MDCLKPOWERUP 0x8000
1641 #define BDA6DEBUGMODE 0x20000
1642 #define BDA6SWING 0x380000
1644 #define BADCLKPHASE 0x4000000
1645 #define B80MCLKDELAY 0x18000000
1646 #define BAFEWATCHDOGENABLE 0x20000000
1648 #define BXTALCAP01 0xc0000000
1649 #define BXTALCAP23 0x3
1650 #define BXTALCAP92X 0x0f000000
1651 #define BXTALCAP 0x0f000000
1653 #define BINTDIFCLKENABLE 0x400
1654 #define BEXTSIGCLKENABLE 0x800
1655 #define BBANDGAP_MBIAS_POWERUP 0x10000
1656 #define BAD11SH_GAIN 0xc0000
1657 #define BAD11NPUT_RANGE 0x700000
1658 #define BAD110P_CURRENT 0x3800000
1659 #define BLPATH_LOOPBACK 0x4000000
1660 #define BQPATH_LOOPBACK 0x8000000
1661 #define BAFE_LOOPBACK 0x10000000
1662 #define BDA10_SWING 0x7e0
1663 #define BDA10_REVERSE 0x800
1664 #define BDA_CLK_SOURCE 0x1000
1665 #define BDA7INPUT_RANGE 0x6000
1666 #define BDA7_GAIN 0x38000
1667 #define BDA7OUTPUT_CM_MODE 0x40000
1668 #define BDA7INPUT_CM_MODE 0x380000
1669 #define BDA7CURRENT 0xc00000
1670 #define BREGULATOR_ADJUST 0x7000000
1671 #define BAD11POWERUP_ATTX 0x1
1672 #define BDA10PS_ATTX 0x10
1673 #define BAD11POWERUP_ATRX 0x100
1674 #define BDA10PS_ATRX 0x1000
1675 #define BCCKRX_AGC_FORMAT 0x200
1676 #define BPSDFFT_SAMPLE_POINT 0xc000
1677 #define BPSD_AVERAGE_NUM 0x3000
1678 #define BIQPATH_CONTROL 0xc00
1679 #define BPSD_FREQ 0x3ff
1680 #define BPSD_ANTENNA_PATH 0x30
1681 #define BPSD_IQ_SWITCH 0x40
1682 #define BPSD_RX_TRIGGER 0x400000
1683 #define BPSD_TX_TRIGGER 0x80000000
1684 #define BPSD_SINE_TONE_SCALE 0x7f000000
1685 #define BPSD_REPORT 0xffff
1687 #define BOFDM_TXSC 0x30000000
1688 #define BCCK_TXON 0x1
1689 #define BOFDM_TXON 0x2
1690 #define BDEBUG_PAGE 0xfff
1691 #define BDEBUG_ITEM 0xff
1692 #define BANTL 0x10
1693 #define BANT_NONHT 0x100
1694 #define BANT_HT1 0x1000
1695 #define BANT_HT2 0x10000
1696 #define BANT_HT1S1 0x100000
1697 #define BANT_NONHTS1 0x1000000
1699 #define BCCK_BBMODE 0x3
1700 #define BCCK_TXPOWERSAVING 0x80
1701 #define BCCK_RXPOWERSAVING 0x40
1703 #define BCCK_SIDEBAND 0x10
1705 #define BCCK_SCRAMBLE 0x8
1706 #define BCCK_ANTDIVERSITY 0x8000
1707 #define BCCK_CARRIER_RECOVERY 0x4000
1708 #define BCCK_TXRATE 0x3000
1709 #define BCCK_DCCANCEL 0x0800
1710 #define BCCK_ISICANCEL 0x0400
1711 #define BCCK_MATCH_FILTER 0x0200
1712 #define BCCK_EQUALIZER 0x0100
1713 #define BCCK_PREAMBLE_DETECT 0x800000
1714 #define BCCK_FAST_FALSECCA 0x400000
1715 #define BCCK_CH_ESTSTART 0x300000
1716 #define BCCK_CCA_COUNT 0x080000
1717 #define BCCK_CS_LIM 0x070000
1718 #define BCCK_BIST_MODE 0x80000000
1719 #define BCCK_CCAMASK 0x40000000
1720 #define BCCK_TX_DAC_PHASE 0x4
1721 #define BCCK_RX_ADC_PHASE 0x20000000
1722 #define BCCKR_CP_MODE 0x0100
1723 #define BCCK_TXDC_OFFSET 0xf0
1724 #define BCCK_RXDC_OFFSET 0xf
1725 #define BCCK_CCA_MODE 0xc000
1726 #define BCCK_FALSECS_LIM 0x3f00
1727 #define BCCK_CS_RATIO 0xc00000
1728 #define BCCK_CORGBIT_SEL 0x300000
1729 #define BCCK_PD_LIM 0x0f0000
1730 #define BCCK_NEWCCA 0x80000000
1731 #define BCCK_RXHP_OF_IG 0x8000
1732 #define BCCK_RXIG 0x7f00
1733 #define BCCK_LNA_POLARITY 0x800000
1734 #define BCCK_RX1ST_BAIN 0x7f0000
1735 #define BCCK_RF_EXTEND 0x20000000
1736 #define BCCK_RXAGC_SATLEVEL 0x1f000000
1737 #define BCCK_RXAGC_SATCOUNT 0xe0
1738 #define BCCKRXRFSETTLE 0x1f
1739 #define BCCK_FIXED_RXAGC 0x8000
1740 #define BCCK_ANTENNA_POLARITY 0x2000
1741 #define BCCK_TXFILTER_TYPE 0x0c00
1742 #define BCCK_RXAGC_REPORTTYPE 0x0300
1743 #define BCCK_RXDAGC_EN 0x80000000
1744 #define BCCK_RXDAGC_PERIOD 0x20000000
1745 #define BCCK_RXDAGC_SATLEVEL 0x1f000000
1746 #define BCCK_TIMING_RECOVERY 0x800000
1747 #define BCCK_TXC0 0x3f0000
1748 #define BCCK_TXC1 0x3f000000
1749 #define BCCK_TXC2 0x3f
1750 #define BCCK_TXC3 0x3f00
1751 #define BCCK_TXC4 0x3f0000
1752 #define BCCK_TXC5 0x3f000000
1753 #define BCCK_TXC6 0x3f
1754 #define BCCK_TXC7 0x3f00
1755 #define BCCK_DEBUGPORT 0xff0000
1756 #define BCCK_DAC_DEBUG 0x0f000000
1757 #define BCCK_FALSEALARM_ENABLE 0x8000
1758 #define BCCK_FALSEALARM_READ 0x4000
1759 #define BCCK_TRSSI 0x7f
1760 #define BCCK_RXAGC_REPORT 0xfe
1761 #define BCCK_RXREPORT_ANTSEL 0x80000000
1762 #define BCCK_RXREPORT_MFOFF 0x40000000
1763 #define BCCK_RXREPORT_SQLOSS 0x20000000
1764 #define BCCK_RXREPORT_PKTLOSS 0x10000000
1765 #define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1766 #define BCCK_RXREPORT_RATEERROR 0x04000000
1767 #define BCCK_RXREPORT_RXRATE 0x03000000
1768 #define BCCK_RXFA_COUNTER_LOWER 0xff
1769 #define BCCK_RXFA_COUNTER_UPPER 0xff000000
1770 #define BCCK_RXHPAGC_START 0xe000
1771 #define BCCK_RXHPAGC_FINAL 0x1c00
1772 #define BCCK_RXFALSEALARM_ENABLE 0x8000
1773 #define BCCK_FACOUNTER_FREEZE 0x4000
1774 #define BCCK_TXPATH_SEL 0x10000000
1775 #define BCCK_DEFAULT_RXPATH 0xc000000
1776 #define BCCK_OPTION_RXPATH 0x3000000
1778 #define BNUM_OFSTF 0x3
1779 #define BSHIFT_L 0xc0
1780 #define BGI_TH 0xc
1781 #define BRXPATH_A 0x1
1782 #define BRXPATH_B 0x2
1783 #define BRXPATH_C 0x4
1784 #define BRXPATH_D 0x8
1785 #define BTXPATH_A 0x1
1786 #define BTXPATH_B 0x2
1787 #define BTXPATH_C 0x4
1788 #define BTXPATH_D 0x8
1789 #define BTRSSI_FREQ 0x200
1790 #define BADC_BACKOFF 0x3000
1791 #define BDFIR_BACKOFF 0xc000
1792 #define BTRSSI_LATCH_PHASE 0x10000
1793 #define BRX_LDC_OFFSET 0xff
1794 #define BRX_QDC_OFFSET 0xff00
1795 #define BRX_DFIR_MODE 0x1800000
1796 #define BRX_DCNF_TYPE 0xe000000
1797 #define BRXIQIMB_A 0x3ff
1798 #define BRXIQIMB_B 0xfc00
1799 #define BRXIQIMB_C 0x3f0000
1800 #define BRXIQIMB_D 0xffc00000
1801 #define BDC_DC_NOTCH 0x60000
1802 #define BRXNB_NOTCH 0x1f000000
1803 #define BPD_TH 0xf
1804 #define BPD_TH_OPT2 0xc000
1805 #define BPWED_TH 0x700
1806 #define BIFMF_WIN_L 0x800
1807 #define BPD_OPTION 0x1000
1808 #define BMF_WIN_L 0xe000
1809 #define BBW_SEARCH_L 0x30000
1810 #define BWIN_ENH_L 0xc0000
1811 #define BBW_TH 0x700000
1812 #define BED_TH2 0x3800000
1813 #define BBW_OPTION 0x4000000
1814 #define BRADIO_TH 0x18000000
1815 #define BWINDOW_L 0xe0000000
1816 #define BSBD_OPTION 0x1
1817 #define BFRAME_TH 0x1c
1818 #define BFS_OPTION 0x60
1819 #define BDC_SLOPE_CHECK 0x80
1820 #define BFGUARD_COUNTER_DC_L 0xe00
1821 #define BFRAME_WEIGHT_SHORT 0x7000
1822 #define BSUB_TUNE 0xe00000
1823 #define BFRAME_DC_LENGTH 0xe000000
1824 #define BSBD_START_OFFSET 0x30000000
1825 #define BFRAME_TH_2 0x7
1826 #define BFRAME_GI2_TH 0x38
1827 #define BGI2_SYNC_EN 0x40
1828 #define BSARCH_SHORT_EARLY 0x300
1829 #define BSARCH_SHORT_LATE 0xc00
1830 #define BSARCH_GI2_LATE 0x70000
1831 #define BCFOANTSUM 0x1
1832 #define BCFOACC 0x2
1833 #define BCFOSTARTOFFSET 0xc
1834 #define BCFOLOOPBACK 0x70
1835 #define BCFOSUMWEIGHT 0x80
1836 #define BDAGCENABLE 0x10000
1837 #define BTXIQIMB_A 0x3ff
1838 #define BTXIQIMB_b 0xfc00
1839 #define BTXIQIMB_C 0x3f0000
1840 #define BTXIQIMB_D 0xffc00000
1841 #define BTXIDCOFFSET 0xff
1842 #define BTXIQDCOFFSET 0xff00
1843 #define BTXDFIRMODE 0x10000
1844 #define BTXPESUDO_NOISEON 0x4000000
1845 #define BTXPESUDO_NOISE_A 0xff
1846 #define BTXPESUDO_NOISE_B 0xff00
1847 #define BTXPESUDO_NOISE_C 0xff0000
1848 #define BTXPESUDO_NOISE_D 0xff000000
1849 #define BCCA_DROPOPTION 0x20000
1850 #define BCCA_DROPTHRES 0xfff00000
1851 #define BEDCCA_H 0xf
1852 #define BEDCCA_L 0xf0
1853 #define BLAMBDA_ED 0x300
1854 #define BRX_INITIALGAIN 0x7f
1855 #define BRX_ANTDIV_EN 0x80
1856 #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1857 #define BRX_HIGHPOWER_FLOW 0x8000
1858 #define BRX_AGC_FREEZE_THRES 0xc0000
1859 #define BRX_FREEZESTEP_AGC1 0x300000
1860 #define BRX_FREEZESTEP_AGC2 0xc00000
1861 #define BRX_FREEZESTEP_AGC3 0x3000000
1862 #define BRX_FREEZESTEP_AGC0 0xc000000
1863 #define BRXRSSI_CMP_EN 0x10000000
1864 #define BRXQUICK_AGCEN 0x20000000
1865 #define BRXAGC_FREEZE_THRES_MODE 0x40000000
1866 #define BRX_OVERFLOW_CHECKTYPE 0x80000000
1867 #define BRX_AGCSHIFT 0x7f
1868 #define BTRSW_TRI_ONLY 0x80
1869 #define BPOWER_THRES 0x300
1870 #define BRXAGC_EN 0x1
1871 #define BRXAGC_TOGETHER_EN 0x2
1872 #define BRXAGC_MIN 0x4
1873 #define BRXHP_INI 0x7
1874 #define BRXHP_TRLNA 0x70
1875 #define BRXHP_RSSI 0x700
1876 #define BRXHP_BBP1 0x7000
1877 #define BRXHP_BBP2 0x70000
1878 #define BRXHP_BBP3 0x700000
1879 #define BRSSI_H 0x7f0000
1880 #define BRSSI_GEN 0x7f000000
1881 #define BRXSETTLE_TRSW 0x7
1882 #define BRXSETTLE_LNA 0x38
1883 #define BRXSETTLE_RSSI 0x1c0
1884 #define BRXSETTLE_BBP 0xe00
1885 #define BRXSETTLE_RXHP 0x7000
1886 #define BRXSETTLE_ANTSW_RSSI 0x38000
1887 #define BRXSETTLE_ANTSW 0xc0000
1888 #define BRXPROCESS_TIME_DAGC 0x300000
1889 #define BRXSETTLE_HSSI 0x400000
1890 #define BRXPROCESS_TIME_BBPPW 0x800000
1891 #define BRXANTENNA_POWER_SHIFT 0x3000000
1892 #define BRSSI_TABLE_SELECT 0xc000000
1893 #define BRXHP_FINAL 0x7000000
1894 #define BRXHPSETTLE_BBP 0x7
1895 #define BRXHTSETTLE_HSSI 0x8
1896 #define BRXHTSETTLE_RXHP 0x70
1897 #define BRXHTSETTLE_BBPPW 0x80
1898 #define BRXHTSETTLE_IDLE 0x300
1899 #define BRXHTSETTLE_RESERVED 0x1c00
1900 #define BRXHT_RXHP_EN 0x8000
1901 #define BRXAGC_FREEZE_THRES 0x30000
1902 #define BRXAGC_TOGETHEREN 0x40000
1903 #define BRXHTAGC_MIN 0x80000
1904 #define BRXHTAGC_EN 0x100000
1905 #define BRXHTDAGC_EN 0x200000
1906 #define BRXHT_RXHP_BBP 0x1c00000
1907 #define BRXHT_RXHP_FINAL 0xe0000000
1908 #define BRXPW_RADIO_TH 0x3
1909 #define BRXPW_RADIO_EN 0x4
1910 #define BRXMF_HOLD 0x3800
1911 #define BRXPD_DELAY_TH1 0x38
1912 #define BRXPD_DELAY_TH2 0x1c0
1913 #define BRXPD_DC_COUNT_MAX 0x600
1914 #define BRXPD_DELAY_TH 0x8000
1915 #define BRXPROCESS_DELAY 0xf0000
1916 #define BRXSEARCHRANGE_GI2_EARLY 0x700000
1917 #define BRXFRAME_FUARD_COUNTER_L 0x3800000
1918 #define BRXSGI_GUARD_L 0xc000000
1919 #define BRXSGI_SEARCH_L 0x30000000
1920 #define BRXSGI_TH 0xc0000000
1921 #define BDFSCNT0 0xff
1922 #define BDFSCNT1 0xff00
1923 #define BDFSFLAG 0xf0000
1924 #define BMF_WEIGHT_SUM 0x300000
1925 #define BMINIDX_TH 0x7f000000
1926 #define BDAFORMAT 0x40000
1927 #define BTXCH_EMU_ENABLE 0x01000000
1928 #define BTRSW_ISOLATION_A 0x7f
1929 #define BTRSW_ISOLATION_B 0x7f00
1930 #define BTRSW_ISOLATION_C 0x7f0000
1931 #define BTRSW_ISOLATION_D 0x7f000000
1932 #define BEXT_LNA_GAIN 0x7c00
1934 #define BSTBC_EN 0x4
1935 #define BANTENNA_MAPPING 0x10
1936 #define BNSS 0x20
1937 #define BCFO_ANTSUM_ID 0x200
1938 #define BPHY_COUNTER_RESET 0x8000000
1939 #define BCFO_REPORT_GET 0x4000000
1940 #define BOFDM_CONTINUE_TX 0x10000000
1941 #define BOFDM_SINGLE_CARRIER 0x20000000
1942 #define BOFDM_SINGLE_TONE 0x40000000
1943 #define BHT_DETECT 0x100
1944 #define BCFOEN 0x10000
1945 #define BCFOVALUE 0xfff00000
1946 #define BSIGTONE_RE 0x3f
1947 #define BSIGTONE_IM 0x7f00
1948 #define BCOUNTER_CCA 0xffff
1949 #define BCOUNTER_PARITYFAIL 0xffff0000
1950 #define BCOUNTER_RATEILLEGAL 0xffff
1951 #define BCOUNTER_CRC8FAIL 0xffff0000
1952 #define BCOUNTER_MCSNOSUPPORT 0xffff
1953 #define BCOUNTER_FASTSYNC 0xffff
1954 #define BSHORTCFO 0xfff
1957 #define BLONGCFO 0x7ff
1960 #define BTAILCFO 0x1fff
1963 #define BNOISE_EN_PWDB 0xffff
1964 #define BCC_POWER_DB 0xffff0000
1965 #define BMOISE_PWDB 0xffff
1968 #define BRX_HT_BW 0x1
1969 #define BRXSC 0x6
1970 #define BRX_HT 0x8
1971 #define BNB_INTF_DET_ON 0x1
1972 #define BINTF_WIN_LEN_CFG 0x30
1973 #define BNB_INTF_TH_CFG 0x1c0
1974 #define BRFGAIN 0x3f
1975 #define BTABLESEL 0x40
1976 #define BTRSW 0x80
1977 #define BRXSNR_A 0xff
1978 #define BRXSNR_B 0xff00
1979 #define BRXSNR_C 0xff0000
1980 #define BRXSNR_D 0xff000000
1983 #define BCSI1ST 0xff
1984 #define BCSI2ND 0xff00
1985 #define BRXEVM1ST 0xff0000
1986 #define BRXEVM2ND 0xff000000
1987 #define BSIGEVM 0xff
1988 #define BPWDB 0xff00
1989 #define BSGIEN 0x10000
1991 #define BSFACTOR_QMA1 0xf
1992 #define BSFACTOR_QMA2 0xf0
1993 #define BSFACTOR_QMA3 0xf00
1994 #define BSFACTOR_QMA4 0xf000
1995 #define BSFACTOR_QMA5 0xf0000
1996 #define BSFACTOR_QMA6 0xf0000
1997 #define BSFACTOR_QMA7 0xf00000
1998 #define BSFACTOR_QMA8 0xf000000
1999 #define BSFACTOR_QMA9 0xf0000000
2000 #define BCSI_SCHEME 0x100000
2002 #define BNOISE_LVL_TOP_SET 0x3
2003 #define BCHSMOOTH 0x4
2004 #define BCHSMOOTH_CFG1 0x38
2005 #define BCHSMOOTH_CFG2 0x1c0
2006 #define BCHSMOOTH_CFG3 0xe00
2007 #define BCHSMOOTH_CFG4 0x7000
2008 #define BMRCMODE 0x800000
2009 #define BTHEVMCFG 0x7000000
2011 #define BLOOP_FIT_TYPE 0x1
2012 #define BUPD_CFO 0x40
2013 #define BUPD_CFO_OFFDATA 0x80
2014 #define BADV_UPD_CFO 0x100
2015 #define BADV_TIME_CTRL 0x800
2016 #define BUPD_CLKO 0x1000
2017 #define BFC 0x6000
2018 #define BTRACKING_MODE 0x8000
2019 #define BPHCMP_ENABLE 0x10000
2020 #define BUPD_CLKO_LTF 0x20000
2021 #define BCOM_CH_CFO 0x40000
2022 #define BCSI_ESTI_MODE 0x80000
2023 #define BADV_UPD_EQZ 0x100000
2024 #define BUCHCFG 0x7000000
2025 #define BUPDEQZ 0x8000000
2027 #define BRX_PESUDO_NOISE_ON 0x20000000
2028 #define BRX_PESUDO_NOISE_A 0xff
2029 #define BRX_PESUDO_NOISE_B 0xff00
2030 #define BRX_PESUDO_NOISE_C 0xff0000
2031 #define BRX_PESUDO_NOISE_D 0xff000000
2032 #define BRX_PESUDO_NOISESTATE_A 0xffff
2033 #define BRX_PESUDO_NOISESTATE_B 0xffff0000
2034 #define BRX_PESUDO_NOISESTATE_C 0xffff
2035 #define BRX_PESUDO_NOISESTATE_D 0xffff0000
2037 #define BZEBRA1_HSSIENABLE 0x8
2038 #define BZEBRA1_TRXCONTROL 0xc00
2039 #define BZEBRA1_TRXGAINSETTING 0x07f
2040 #define BZEBRA1_RXCOUNTER 0xc00
2041 #define BZEBRA1_TXCHANGEPUMP 0x38
2042 #define BZEBRA1_RXCHANGEPUMP 0x7
2043 #define BZEBRA1_CHANNEL_NUM 0xf80
2044 #define BZEBRA1_TXLPFBW 0x400
2045 #define BZEBRA1_RXLPFBW 0x600
2047 #define BRTL8256REG_MODE_CTRL1 0x100
2048 #define BRTL8256REG_MODE_CTRL0 0x40
2049 #define BRTL8256REG_TXLPFBW 0x18
2050 #define BRTL8256REG_RXLPFBW 0x600
2052 #define BRTL8258_TXLPFBW 0xc
2053 #define BRTL8258_RXLPFBW 0xc00
2054 #define BRTL8258_RSSILPFBW 0xc0
2056 #define BBYTE0 0x1
2057 #define BBYTE1 0x2
2058 #define BBYTE2 0x4
2059 #define BBYTE3 0x8
2060 #define BWORD0 0x3
2061 #define BWORD1 0xc
2062 #define BWORD 0xf
2064 #define MASKBYTE0 0xff
2065 #define MASKBYTE1 0xff00
2066 #define MASKBYTE2 0xff0000
2067 #define MASKBYTE3 0xff000000
2068 #define MASKHWORD 0xffff0000
2069 #define MASKLWORD 0x0000ffff
2070 #define MASKDWORD 0xffffffff
2071 #define MASK12BITS 0xfff
2072 #define MASKH4BITS 0xf0000000
2073 #define MASKOFDM_D 0xffc00000
2074 #define MASKCCK 0x3f3f3f3f
2076 #define MASK4BITS 0x0f
2077 #define MASK20BITS 0xfffff
2078 #define RFREG_OFFSET_MASK 0xfffff
2080 #define BENABLE 0x1
2081 #define BDISABLE 0x0
2083 #define LEFT_ANTENNA 0x0
2084 #define RIGHT_ANTENNA 0x1
2090 #define EFUSE_SEL(x) (((x) & 0x3) << 8)
2091 #define EFUSE_SEL_MASK 0x300
2092 #define EFUSE_WIFI_SEL_0 0x0
2094 #define WL_HWPDN_EN BIT(0)