Lines Matching +full:00 +full:- +full:40 +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
9 * Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
11 * 0: POFF--Power Off
12 * 1: PDN--Power Down
13 * 2: CARDEMU--Card Emulation
14 * 3: ACT--Active Mode
15 * 4: LPS--Low Power State
16 * 5: SUS--Suspend
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
49 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
77 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
85 BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
91 BIT(3)|BIT(4), BIT(3)}, \
95 PWR_CMD_WRITE, BIT(3)|BIT(4), \
96 BIT(3)|BIT(4)}, \
100 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
104 PWR_CMD_POLLING, BIT(1), 0},
112 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
115 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
116 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
131 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
135 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
139 PWR_CMD_POLLING, BIT(1), 0},
148 PWR_CMD_WRITE, BIT(0), 0}, \
152 PWR_CMD_POLLING, BIT(1), BIT(1)},\
153 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
156 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
167 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
170 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
177 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
208 PWR_CMD_WRITE, BIT(0), 0},\
214 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
220 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
224 PWR_CMD_WRITE, BIT(5), BIT(5)},\
241 /*. 0x08[4] = 0 switch TSF to 40M*/\
244 PWR_CMD_WRITE, BIT(4), 0}, \
245 /*Polling 0x109[7]=0 TSF in 40M*/\
248 PWR_CMD_POLLING, BIT(7), 0}, \
249 /*. 0x29[7:6] = 2b'00 enable BB clock*/\
252 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
256 PWR_CMD_WRITE, BIT(1), BIT(1)},\
264 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\