68 	if (bitmask != MASKDWORD) {  in rtl92ee_phy_set_bb_reg()
151 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
155 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
158 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in _rtl92ee_phy_rf_serial_read()
160 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in _rtl92ee_phy_rf_serial_read()
197 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in _rtl92ee_phy_rf_serial_write()
287 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
296 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
306 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
318 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
362 		rtl_set_bbreg(hw, addr, MASKDWORD , data);  in _rtl92ee_config_bb_reg()
725 				rtl_set_bbreg(hw, array[i], MASKDWORD,  in phy_config_bb_with_hdr_file()
755 							      MASKDWORD,  in phy_config_bb_with_hdr_file()
1026 					      ROFDM0_RXDETECTOR2, MASKDWORD);  in rtl92ee_phy_get_hw_reg_originalvalue()
1934 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_iqk()
1936 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_iqk()
1938 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_iqk()
1939 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1940 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1941 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1943 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);  in _rtl92ee_phy_path_a_iqk()
1944 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_a_iqk()
1947 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_a_iqk()
1950 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl92ee_phy_path_a_iqk()
1951 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_iqk()
1955 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1956 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1957 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1975 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
1977 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
1979 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
1980 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
1982 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
1983 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
1984 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_iqk()
1985 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
1987 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);  in _rtl92ee_phy_path_b_iqk()
1988 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_b_iqk()
1991 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_b_iqk()
1994 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_iqk()
1995 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_iqk()
1999 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2000 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2001 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2020 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2032 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2035 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_a_rx_iqk()
2036 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2039 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2040 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2041 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2042 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2044 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2045 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2048 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_a_rx_iqk()
2051 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2052 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2057 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2058 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2059 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2067 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2074 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_a_rx_iqk()
2077 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2090 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2093 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2096 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2097 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2098 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2099 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2101 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2102 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2105 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_a_rx_iqk()
2107 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2108 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2112 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2113 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2117 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2136 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2147 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2150 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_b_rx_iqk()
2151 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2154 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2155 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2156 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2157 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2159 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2160 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2163 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_b_rx_iqk()
2166 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2167 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2172 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2173 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2174 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2182 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2189 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_b_rx_iqk()
2192 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2204 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2207 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2210 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2211 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2212 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2213 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2215 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2216 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2219 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_b_rx_iqk()
2221 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2222 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2226 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2227 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2228 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2231 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2256 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_a_fill_iqk_matrix()
2301 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_b_fill_iqk_matrix()
2341 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl92ee_phy_save_adda_registers()
2363 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);  in _rtl92ee_phy_reload_adda_registers()
2383 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616);  in _rtl92ee_phy_path_adda_on()
2394 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);  in _rtl92ee_phy_path_a_standby()
2396 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_standby()
2515 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);  in _rtl92ee_phy_iq_calibrate()
2516 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);  in _rtl92ee_phy_iq_calibrate()
2517 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);  in _rtl92ee_phy_iq_calibrate()
2528 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2529 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2530 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2540 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2543 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2560 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2564 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2582 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2583 		rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2584 		rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2593 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2597 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2613 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2617 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2633 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl92ee_phy_iq_calibrate()
2658 		rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()
2659 		rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()