Lines Matching refs:MASKDWORD
195 if (bitmask != MASKDWORD) {
295 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
306 MASKDWORD, agctab_array_table[i + 1]);
970 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
971 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
973 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22);
974 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22);
976 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102);
977 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD,
981 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22);
982 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22);
983 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102);
984 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206);
989 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
993 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1002 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1004 rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1006 rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1008 regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1049 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1050 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1051 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307);
1052 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960);
1055 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1056 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1057 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1058 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000);
1063 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1066 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1067 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1073 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1074 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1095 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1097 rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1099 rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1101 regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1123 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1125 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1129 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1132 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
1133 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1137 rtl_get_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD));
1151 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002);
1152 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000);
1159 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1161 regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);
1163 regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);
1165 regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);
1167 regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);
1199 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1200 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f);
1201 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1202 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000);
1205 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1206 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f);
1207 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307);
1208 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960);
1212 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1215 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1216 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
1223 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1243 regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1245 regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);
1247 regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);
1249 regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);
1251 regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);
1270 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1272 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1276 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1279 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
1280 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1284 rtl_get_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD));
1303 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50);
1305 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1328 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1340 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, MASKDWORD, mode);
1341 rtl_set_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, MASKDWORD, mode);
1372 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1389 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
1400 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1401 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1402 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1405 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1407 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1416 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
1418 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000);
1423 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1424 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1518 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1519 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);
1560 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1599 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1600 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1604 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0);
1605 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
1608 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0);
1609 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000);
1615 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00);
1616 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1640 rtl_get_bbreg(hw, RRX_WAIT_CCA, MASKDWORD));
1692 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8);
1694 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8);
1820 rtl_get_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD));
1837 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1838 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
1839 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00);
1903 MASKDWORD));
1954 rtl_get_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD));
1971 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00);
1972 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
1973 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00);
2478 MASKDWORD);
2773 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100);
2774 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100);
2788 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
2789 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
2813 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
2814 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038);
2815 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
2816 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000);
2839 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
2842 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
2848 MASKDWORD, 0x2d4000b5);
2851 MASKDWORD, 0x20000080);
2865 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098);
2866 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
2882 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098);
2883 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098);
2884 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000);
2885 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000);
2890 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
2891 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);