Lines Matching +full:efuse +full:- +full:settings
1 // SPDX-License-Identifier: GPL-2.0
7 #include "../efuse.h"
84 /* channels 1-14. */
89 /* channels 36-64 */
95 /* channels 100-165 */
165 if (rtlhal->during_mac1init_radioa)
167 else if (rtlhal->during_mac0init_radiob)
190 if (rtlhal->during_mac1init_radioa)
192 else if (rtlhal->during_mac0init_radiob)
245 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
246 /* improve 2-stream TX EVM */
269 if (rtlhal->interfaceindex == 0) {
275 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
351 struct rtl_phy *rtlphy = &rtlpriv->phy;
361 if (!rtlefuse->autoload_failflag) {
362 rtlphy->pwrgroup_cnt = 0;
376 rtlphy->cck_high_power = (bool)rtl_get_bbreg(hw,
407 if (rtlhal->interface == INTF_PCI)
409 else if (rtlhal->interface == INTF_USB)
422 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)) &&
423 rtlhal->interface == INTF_PCI) {
432 rtlpriv->efuse.crystalcap & 0x0f);
434 (rtlpriv->efuse.crystalcap & 0xf0) >> 4);
458 if (rtlpriv->efuse.internal_pa_5g[0]) {
462 if (rtlpriv->efuse.internal_pa_5g[1]) {
512 struct rtl_phy *rtlphy = &rtlpriv->phy;
517 if (rtlphy->set_bwmode_inprogress)
526 rtlphy->set_bwmode_inprogress = true;
529 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
535 switch (rtlphy->current_chan_bw) {
545 (mac->cur_40_prime_sc << 5);
550 rtlphy->current_chan_bw);
554 switch (rtlphy->current_chan_bw) {
565 * These settings are required only for 40MHz
567 if (rtlhal->current_bandtype == BAND_ON_2_4G)
569 mac->cur_40_prime_sc >> 1);
570 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
575 mac->cur_40_prime_sc ==
580 rtlphy->current_chan_bw);
584 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
586 rtlphy->set_bwmode_inprogress = false;
606 rtlhal->bandset = band;
607 rtlhal->current_bandtype = band;
608 if (IS_92D_SINGLEPHY(rtlhal->version))
609 rtlhal->bandset = BAND_ON_BOTH;
615 if (rtlhal->current_bandtype == BAND_ON_2_4G)
622 if (rtlhal->interfaceindex == 1)
628 if (rtlhal->current_bandtype == BAND_ON_2_4G)
630 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
637 rtlhal->reloadtxpowerindex = true;
639 reg_mac = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1;
642 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
662 if (rtlusb->udev->speed != USB_SPEED_HIGH)
666 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
680 /* leave 0 for channel1-14. */
695 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
698 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
727 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
728 struct rtl_phy *rtlphy = &rtlpriv->phy;
729 u8 path = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A
736 if (rtlusb->udev->speed != USB_SPEED_HIGH)
741 if (rtlhal->current_bandtype == BAND_ON_5G) {
743 u4tmp = rtlpriv->curveindex_5g[channel - 1];
745 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
763 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
764 rtlhal->interfaceindex == 1) {
766 rtlhal->during_mac1init_radioa = true;
774 if (regb30 && rtlhal->interfaceindex == 0) {
776 rtlhal->during_mac0init_radiob = true;
783 if (i == 0 && rtlhal->macphymode == DUALMAC_DUALPHY) {
810 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
811 rtlhal->interfaceindex == 1) {
818 if (regb30 && rtlhal->interfaceindex == 0) {
836 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
838 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
839 rtlhal->interfaceindex == 1) /* MAC 1 5G */
840 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
843 rtlpriv->efuse.internal_pa_5g[rfpath];
871 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
873 u4tmp = rtlpriv->curveindex_2g[channel - 1];
875 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
886 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
888 if (rtlhal->interfaceindex == 0) {
891 rtlhal->during_mac0init_radiob = true;
899 if (regb30 && rtlhal->interfaceindex == 1) {
902 rtlhal->during_mac1init_radioa = true;
934 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
941 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
942 rtlhal->interfaceindex == 0) {
949 if (regb30 && rtlhal->interfaceindex == 1) {
967 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
969 if (rtlhal->interfaceindex == 0) {
979 /* path-B IQK setting */
1035 struct rtl_phy *rtlphy = &rtlpriv->phy;
1043 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1048 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1053 /* path-B IQK setting */
1065 /* path-A PA on */
1124 rtlphy->iqk_bb_backup[0]);
1126 rtlphy->iqk_bb_backup[1]);
1191 struct rtl_phy *rtlphy = &rtlpriv->phy;
1198 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-B IQK setting!\n");
1204 /* path-B IQK setting */
1214 /* path-B PA on */
1271 rtlphy->iqk_bb_backup[0]);
1273 rtlphy->iqk_bb_backup[2]);
1300 /* path-A/B BB to initial gain */
1316 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1325 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1364 struct rtl_phy *rtlphy = &rtlpriv->phy;
1379 rtlphy->adda_backup,
1382 rtlphy->iqk_mac_backup);
1384 rtlphy->iqk_bb_backup,
1392 rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw,
1396 if (!rtlphy->rfpi_enable)
1411 /* MAC settings */
1413 rtlphy->iqk_mac_backup);
1440 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1473 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1496 if (!rtlphy->rfpi_enable)
1501 rtlphy->adda_backup,
1506 rtlphy->iqk_mac_backup);
1510 rtlphy->iqk_bb_backup,
1514 rtlphy->iqk_bb_backup,
1515 IQK_BB_REG_NUM - 1);
1544 struct rtl_phy *rtlphy = &rtlpriv->phy;
1545 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1546 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1567 rtlphy->adda_backup,
1570 rtlphy->iqk_mac_backup);
1573 rtlphy->iqk_bb_backup,
1577 rtlphy->iqk_bb_backup,
1578 IQK_BB_REG_NUM - 1);
1585 rtlphy->rfpi_enable = rtl_get_bbreg(hw,
1590 if (!rtlphy->rfpi_enable)
1593 /* MAC settings */
1595 rtlphy->iqk_mac_backup);
1684 rtlphy->iqk_bb_backup,
1688 rtlphy->iqk_bb_backup,
1689 IQK_BB_REG_NUM - 1);
1698 rtlphy->iqk_mac_backup);
1701 if (!rtlphy->rfpi_enable)
1706 rtlphy->adda_backup,
1716 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1719 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1749 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1791 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1811 if (rtlhal->current_bandtype == BAND_ON_5G)
1848 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1851 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
1852 rtlhal->macphymode == DUALMAC_DUALPHY;
1854 if (rtlhal->current_bandtype == BAND_ON_5G) {
1886 if (rtlhal->interfaceindex == 1 &&
1887 rtlhal->current_bandtype == BAND_ON_5G)
1925 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1945 if (rtlhal->current_bandtype == BAND_ON_5G)
1982 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
1986 if (rtlhal->current_bandtype == BAND_ON_5G) {
2016 if (rtlhal->current_bandtype == BAND_ON_5G)
2044 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2046 struct rtl_phy *rtlphy = &rtlpriv->phy;
2052 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2061 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2064 if (rtlhal->current_bandtype == BAND_ON_5G) {
2066 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2067 if (IS_92D_SINGLEPHY(rtlhal->version))
2123 rtlphy->reg_e94 = rege94;
2125 rtlphy->reg_e9c = rege9c;
2129 rtlphy->reg_eb4 = regeb4;
2131 rtlphy->reg_ebc = regebc;
2145 rtlphy->reg_e94 = 0x100;
2146 rtlphy->reg_eb4 = 0x100; /* X default value */
2147 rtlphy->reg_e9c = 0x0;
2148 rtlphy->reg_ebc = 0x0; /* Y default value */
2154 if (IS_92D_SINGLEPHY(rtlhal->version) &&
2162 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
2165 rtlphy->iqk_matrix[indexforchannel].value[0][i] =
2168 rtlphy->iqk_matrix[indexforchannel].iqk_done = true;
2178 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2179 struct rtl_phy *rtlphy = &rtlpriv->phy;
2185 /*------Do IQK for normal chip and test chip 5G band------- */
2190 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2196 need_iqk = !mac->act_scanning;
2198 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done && need_iqk) {
2207 if ((!rtlhal->load_imrandiqk_setting_for2g && indexforchannel == 0) ||
2213 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0)
2215 rtlphy->iqk_matrix[indexforchannel].value, 0,
2216 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0);
2218 if (IS_92D_SINGLEPHY(rtlhal->version) &&
2219 rtlphy->iqk_matrix[indexforchannel].value[0][4] != 0)
2221 rtlphy->iqk_matrix[indexforchannel].value, 0,
2222 rtlphy->iqk_matrix[indexforchannel].value[0][6] == 0);
2230 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2231 u8 erfpath = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A :
2232 IS_92D_SINGLEPHY(rtlhal->version) ? RF90_PATH_B : RF90_PATH_A;
2238 rtlpriv->rtlhal.current_bandtype);
2241 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2242 u4tmp = rtlpriv->curveindex_5g[channel - 1];
2244 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
2246 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2247 rtlpriv->rtlhal.interfaceindex == 1) {
2250 rtlpriv->rtlhal.during_mac1init_radioa = true;
2263 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2264 u4tmp = rtlpriv->curveindex_2g[channel - 1];
2266 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2268 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2269 rtlpriv->rtlhal.interfaceindex == 0) {
2272 rtlpriv->rtlhal.during_mac0init_radiob = true;
2281 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2295 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2327 /* switch CV-curve control by LC-calibration */
2360 if (index == 0 && rtlhal->interfaceindex == 0) {
2362 "path-A / 5G LCK\n");
2365 "path-B / 2.4G LCK\n");
2376 /* save Curve-counting number */
2398 if (index == 0 && rtlhal->interfaceindex == 0)
2401 true, rtlpriv->curveindex_5g);
2405 false, rtlpriv->curveindex_2g);
2407 /* switch CV-curve control mode */
2422 _rtl92du_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2428 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2429 struct rtl_phy *rtlphy = &rtlpriv->phy;
2432 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2437 rtlphy->lck_inprogress = true;
2440 rtlhal->current_bandtype, timecount);
2444 rtlphy->lck_inprogress = false;
2452 struct rtl_phy *rtlphy = &rtlpriv->phy;
2453 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2454 u8 channel = rtlphy->current_channel;
2459 if (rtlphy->sw_chnl_inprogress)
2461 if (rtlphy->set_bwmode_inprogress)
2470 while (rtlphy->lck_inprogress && timecount < timeout) {
2475 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2476 rtlhal->bandset == BAND_ON_BOTH) {
2479 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2481 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2485 switch (rtlhal->current_bandtype) {
2502 rtlpriv->mac80211.mode);
2506 rtlphy->sw_chnl_inprogress = true;
2509 "switch to channel%d\n", rtlphy->current_channel);
2514 u32p_replace_bits(&rtlphy->rfreg_chnlval[rfpath],
2517 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
2519 rtlphy->rfreg_chnlval[rfpath] |= (BIT(18));
2521 rtlphy->rfreg_chnlval[rfpath] &= ~BIT(18);
2522 rtlphy->rfreg_chnlval[rfpath] |= (BIT(16) | BIT(8));
2524 rtlphy->rfreg_chnlval[rfpath] &=
2528 rtlphy->rfreg_chnlval[rfpath]);
2539 rtlphy->sw_chnl_inprogress = false;
2549 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2594 retry--;
2612 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2624 if (rfpwr_state == ppsc->rfpwr_state)
2629 if (ppsc->rfpwr_state == ERFOFF &&
2646 jiffies_to_msecs(jiffies -
2647 ppsc->last_sleep_jiffies),
2648 rtlpriv->psc.state_inap);
2649 ppsc->last_awake_jiffies = jiffies;
2653 if (mac->link_state == MAC80211_LINKED)
2654 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
2656 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2659 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2665 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
2666 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2668 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2672 if (ppsc->rfpwr_state == ERFOFF)
2677 jiffies_to_msecs(jiffies -
2678 ppsc->last_awake_jiffies),
2679 rtlpriv->psc.state_inap);
2680 ppsc->last_sleep_jiffies = jiffies;
2690 ppsc->rfpwr_state = rfpwr_state;
2699 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
2704 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2714 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
2718 mutex_lock(rtlpriv->mutex_for_power_on_off);
2719 if (rtlhal->interfaceindex == 0) {
2727 mutex_unlock(rtlpriv->mutex_for_power_on_off);
2734 mutex_lock(rtlpriv->mutex_for_power_on_off);
2737 mutex_unlock(rtlpriv->mutex_for_power_on_off);
2749 struct rtl_phy *rtlphy = &rtlpriv->phy;
2754 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2758 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
2775 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
2778 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
2779 (rtlefuse->eeprom_c9 & BIT(1)) |
2780 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
2783 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
2784 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
2785 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
2794 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
2795 (rtlefuse->eeprom_c9 & BIT(1)) |
2796 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
2797 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
2798 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
2799 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
2802 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
2803 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
2804 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
2807 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
2808 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
2809 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
2823 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
2838 if (rtlefuse->internal_pa_5g[rtlhal->interfaceindex])
2845 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
2846 if (rtlefuse->internal_pa_5g[1])
2856 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
2859 (rtlefuse->eeprom_cc & BIT(5)));
2861 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
2863 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
2871 (rtlefuse->eeprom_cc & BIT(5)) |
2872 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
2874 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
2876 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
2879 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
2880 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
2889 /* update IQK related settings */
2900 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
2902 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2917 if (rtlhal->interfaceindex == 0 && rtlhal->bandset == BAND_ON_2_4G) {
2921 rtlhal->during_mac0init_radiob = true;
2926 } else if (rtlhal->interfaceindex == 1 && rtlhal->bandset == BAND_ON_5G) {
2930 rtlhal->during_mac1init_radioa = true;
2940 if (rtlphy->rf_type == RF_1T1R) {
2945 /* enable ad/da clock1 for dual-phy reg0x888 */
2946 if (rtlhal->interfaceindex == 0) {
2950 rtlhal->during_mac1init_radioa = true;
2968 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
2970 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
2973 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
2979 rtlphy->rfreg_chnlval[i]);
2990 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
2996 mutex_lock(rtlpriv->mutex_for_power_on_off);
2997 if (rtlhal->interfaceindex == 0) {
3009 mutex_unlock(rtlpriv->mutex_for_power_on_off);
3015 mutex_unlock(rtlpriv->mutex_for_power_on_off);
3024 bool is_single_mac = rtlhal->macphymode == SINGLEMAC_SINGLEPHY;
3033 if (!(val8 & BIT(0)) && (is_single_mac || rtlhal->interfaceindex == 0)) {
3046 if (!(val8 & BIT(1)) && (is_single_mac || rtlhal->interfaceindex == 1)) {
3047 rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B;
3061 if (!(val8 & BIT(2)) && (is_single_mac || rtlhal->interfaceindex == 0)) {
3089 if (!(val8 & BIT(3)) && (is_single_mac || rtlhal->interfaceindex == 1)) {
3090 rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B;