Lines Matching +full:channel +full:- +full:spacing
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
7 /* ----------------------------------------------------- */
9 /* ----------------------------------------------------- */
76 /* ----------------------------------------------------- */
78 /* ----------------------------------------------------- */
123 /* ----------------------------------------------------- */
125 /* ----------------------------------------------------- */
133 /* ----------------------------------------------------- */
135 /* ----------------------------------------------------- */
140 /* ----------------------------------------------------- */
142 /* ----------------------------------------------------- */
166 /* ----------------------------------------------------- */
168 /* ----------------------------------------------------- */
221 /* ----------------------------------------------------- */
223 /* ----------------------------------------------------- */
269 /* Dual MAC Co-Existence Register */
272 /* ----------------------------------------------------- */
274 /* ----------------------------------------------------- */
333 /* ----------------------------------------------------- */
335 /* ----------------------------------------------------- */
349 /* ----------------------------------------------------- */
351 /* ----------------------------------------------------- */
358 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
359 /* ----------------------------------------------------- */
361 /* ----------------------------------------------------- */
390 /* ----------------------------------------------------- */
392 /* ----------------------------------------------------- */
472 /* ----------------------------------------------------- */
474 /* ----------------------------------------------------- */
480 /* ----------------------------------------------------- */
482 /* ----------------------------------------------------- */
502 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
508 /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
509 /* ----------------------------------------------------- */
511 /* ----------------------------------------------------- */
553 /* ----------------------------------------------------- */
555 /* ----------------------------------------------------- */
560 /* ----------------------------------------------------- */
562 /* ----------------------------------------------------- */
571 /* HT20<->40 default Tx Power Index Difference */
603 #define RTL8190_EEPROM_ID 0x8129 /* 0-1 */
604 #define EEPROM_HPON 0x02 /* LDO settings.2-5 */
605 #define EEPROM_CLK 0x06 /* Clock settings.6-7 */
608 #define EEPROM_VID 0x28 /* SE Vendor ID.A-B */
609 #define EEPROM_DID 0x2A /* SE Device ID. C-D */
610 #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
611 #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
616 #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
630 /*5GL channel 32-64 */
638 /* 5GM channel 100-140 */
646 /* 5GH channel 149-165 */
690 /* ----------------------------------------------------- */
692 /* ----------------------------------------------------- */
718 /* ----------------------------------------------------- */
720 /* ----------------------------------------------------- */
721 /* ----------------------------------------------------- */
723 /* ----------------------------------------------------- */
979 /* ----------------------------------------------------- */
981 /* ----------------------------------------------------- */
990 /* ----------------------------------------------------- */
992 /* ----------------------------------------------------- */
1012 /* ----------------------------------------------------- */
1014 /* ----------------------------------------------------- */
1043 /* Min Spacing related settings. */
1048 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
1050 /* RF_Mode, TRxRN, NumOf L-STF */
1052 /* 3. RF register 0x00-2E */