Lines Matching refs:val32
294 u32 val32, sys_cfg, vendor; in rtl8723bu_identify_chip() local
311 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723bu_identify_chip()
312 if (val32 & MULTI_WIFI_FUNC_EN) in rtl8723bu_identify_chip()
314 if (val32 & MULTI_BT_FUNC_EN) in rtl8723bu_identify_chip()
316 if (val32 & MULTI_GPS_FUNC_EN) in rtl8723bu_identify_chip()
323 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723bu_identify_chip()
324 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723bu_identify_chip()
391 u32 val32, ofdm, mcs; in rtl8723b_set_tx_power() local
399 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
400 val32 &= 0xffff00ff; in rtl8723b_set_tx_power()
401 val32 |= (cck << 8); in rtl8723b_set_tx_power()
402 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
404 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
405 val32 &= 0xff; in rtl8723b_set_tx_power()
406 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8723b_set_tx_power()
407 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
539 u32 val32; in rtl8723bu_phy_init_antenna_selection() local
541 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
542 val32 &= ~(BIT(20) | BIT(24)); in rtl8723bu_phy_init_antenna_selection()
543 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
545 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
546 val32 &= ~BIT(4); in rtl8723bu_phy_init_antenna_selection()
547 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
549 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
550 val32 |= BIT(3); in rtl8723bu_phy_init_antenna_selection()
551 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
553 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
554 val32 |= BIT(24); in rtl8723bu_phy_init_antenna_selection()
555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
557 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
558 val32 &= ~BIT(23); in rtl8723bu_phy_init_antenna_selection()
559 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
561 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723bu_phy_init_antenna_selection()
562 val32 |= (BIT(0) | BIT(1)); in rtl8723bu_phy_init_antenna_selection()
563 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
565 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); in rtl8723bu_phy_init_antenna_selection()
566 val32 &= 0xffffff00; in rtl8723bu_phy_init_antenna_selection()
567 val32 |= 0x77; in rtl8723bu_phy_init_antenna_selection()
568 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
570 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723bu_phy_init_antenna_selection()
571 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8723bu_phy_init_antenna_selection()
572 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
577 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; in rtl8723bu_iqk_path_a() local
585 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
586 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
587 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
592 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_iqk_path_a()
593 val32 |= 0x80000; in rtl8723bu_iqk_path_a()
594 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_iqk_path_a()
622 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
623 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
624 val32 |= 0x80800000; in rtl8723bu_iqk_path_a()
625 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
658 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
659 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
660 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
667 val32 = (reg_e9c >> 16) & 0x3ff; in rtl8723bu_iqk_path_a()
668 if (val32 & 0x200) in rtl8723bu_iqk_path_a()
669 val32 = 0x400 - val32; in rtl8723bu_iqk_path_a()
676 val32 < 0xf) in rtl8723bu_iqk_path_a()
687 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; in rtl8723bu_rx_iqk_path_a() local
695 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
696 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
702 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
703 val32 |= 0x80000; in rtl8723bu_rx_iqk_path_a()
704 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
733 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
734 val32 |= 0x80800000; in rtl8723bu_rx_iqk_path_a()
735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
768 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
769 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
770 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
777 val32 = (reg_e9c >> 16) & 0x3ff; in rtl8723bu_rx_iqk_path_a()
778 if (val32 & 0x200) in rtl8723bu_rx_iqk_path_a()
779 val32 = 0x400 - val32; in rtl8723bu_rx_iqk_path_a()
786 val32 < 0xf) in rtl8723bu_rx_iqk_path_a()
791 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | in rtl8723bu_rx_iqk_path_a()
793 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
798 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
799 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
800 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
801 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
802 val32 |= 0x80000; in rtl8723bu_rx_iqk_path_a()
803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
836 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
837 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
838 val32 |= 0x80800000; in rtl8723bu_rx_iqk_path_a()
839 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
867 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
868 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
869 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
877 val32 = (reg_eac >> 16) & 0x3ff; in rtl8723bu_rx_iqk_path_a()
878 if (val32 & 0x200) in rtl8723bu_rx_iqk_path_a()
879 val32 = 0x400 - val32; in rtl8723bu_rx_iqk_path_a()
886 val32 < 0xf) in rtl8723bu_rx_iqk_path_a()
898 u32 i, val32; in rtl8723bu_phy_iqcalibrate() local
943 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8723bu_phy_iqcalibrate()
944 val32 |= 0x0f000000; in rtl8723bu_phy_iqcalibrate()
945 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
955 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
956 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
957 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
959 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iqcalibrate()
960 val32 |= 0x80000; in rtl8723bu_phy_iqcalibrate()
961 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iqcalibrate()
967 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iqcalibrate()
968 val32 |= 0x20; in rtl8723bu_phy_iqcalibrate()
969 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iqcalibrate()
976 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
977 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
978 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
980 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
982 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
983 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
985 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
997 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
999 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1000 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1002 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1019 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1020 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1021 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1024 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1025 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1026 val32 |= 0x80800000; in rtl8723bu_phy_iqcalibrate()
1027 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1035 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8723bu_phy_iqcalibrate()
1036 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1037 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8723bu_phy_iqcalibrate()
1038 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1049 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1051 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1052 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1054 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1065 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1066 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1067 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1082 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1083 val32 &= 0xffffff00; in rtl8723bu_phy_iqcalibrate()
1084 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1085 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1088 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1089 val32 &= 0xffffff00; in rtl8723bu_phy_iqcalibrate()
1091 val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1093 val32 | xb_agc); in rtl8723bu_phy_iqcalibrate()
1110 u32 val32, bt_control; in rtl8723bu_phy_iq_calibrate() local
1209 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iq_calibrate()
1210 val32 |= 0x80000; in rtl8723bu_phy_iq_calibrate()
1211 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iq_calibrate()
1215 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iq_calibrate()
1216 val32 |= 0x20; in rtl8723bu_phy_iq_calibrate()
1217 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iq_calibrate()
1230 u32 val32; in rtl8723bu_active_to_emu() local
1242 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723bu_active_to_emu()
1243 val32 |= APS_FSMCO_WLON_RESET; in rtl8723bu_active_to_emu()
1244 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1287 u32 val32; in rtl8723b_emu_to_active() local
1308 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1309 val32 &= ~APS_FSMCO_SW_LPS; in rtl8723b_emu_to_active()
1310 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1314 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1315 if (val32 & BIT(17)) in rtl8723b_emu_to_active()
1329 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1330 val32 |= APS_FSMCO_WLON_RESET; in rtl8723b_emu_to_active()
1331 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1334 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1335 val32 &= ~APS_FSMCO_HW_POWERDOWN; in rtl8723b_emu_to_active()
1336 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1339 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1340 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); in rtl8723b_emu_to_active()
1341 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1344 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1345 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8723b_emu_to_active()
1346 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1349 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1350 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8723b_emu_to_active()
1409 u32 val32; in rtl8723bu_power_on() local
1450 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_power_on()
1451 val32 |= LEDCFG0_DPDT_SELECT; in rtl8723bu_power_on()
1452 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1506 u32 val32; in rtl8723b_enable_rf() local
1509 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8723b_enable_rf()
1510 val32 |= (BIT(22) | BIT(23)); in rtl8723b_enable_rf()
1511 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1553 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723b_enable_rf()
1554 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8723b_enable_rf()
1555 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1562 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723b_enable_rf()
1563 val32 |= (BIT(0) | BIT(1)); in rtl8723b_enable_rf()
1564 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1568 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723b_enable_rf()
1569 val32 &= ~BIT(24); in rtl8723b_enable_rf()
1570 val32 |= BIT(23); in rtl8723b_enable_rf()
1571 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1638 u32 val32; in rtl8723bu_init_statistics() local
1646 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_init_statistics()
1647 val32 |= 0xff; in rtl8723bu_init_statistics()
1648 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1650 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8723bu_init_statistics()
1651 val32 |= BIT(8) | BIT(9) | BIT(10); in rtl8723bu_init_statistics()
1652 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1654 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8723bu_init_statistics()
1655 val32 |= BIT(7); in rtl8723bu_init_statistics()
1656 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()