Lines Matching +full:0 +full:x000fc000

20 	.reg_0e00 = 0x0a0c0c0c,
21 .reg_0e04 = 0x02040608,
22 .reg_0e08 = 0x00000000,
23 .reg_086c = 0x00000000,
25 .reg_0e10 = 0x0a0c0d0e,
26 .reg_0e14 = 0x02040608,
27 .reg_0e18 = 0x0a0c0d0e,
28 .reg_0e1c = 0x02040608,
30 .reg_0830 = 0x0a0c0c0c,
31 .reg_0834 = 0x02040608,
32 .reg_0838 = 0x00000000,
33 .reg_086c_2 = 0x00000000,
35 .reg_083c = 0x0a0c0d0e,
36 .reg_0848 = 0x02040608,
37 .reg_084c = 0x0a0c0d0e,
38 .reg_0868 = 0x02040608,
42 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
43 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
44 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
45 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
46 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
47 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
48 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
49 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
50 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
51 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
52 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
53 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
54 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
55 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
56 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
57 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
58 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
59 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
60 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
61 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
62 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
63 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
67 {0x00, 0x00030159}, {0x01, 0x00031284},
68 {0x02, 0x00098000}, {0x03, 0x00039c63},
69 {0x04, 0x000210e7}, {0x09, 0x0002044f},
70 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
71 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
72 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
73 {0x19, 0x00000000}, {0x1a, 0x00030355},
74 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
75 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
76 {0x1f, 0x00000000}, {0x20, 0x0000b614},
77 {0x21, 0x0006c000}, {0x22, 0x00000000},
78 {0x23, 0x00001558}, {0x24, 0x00000060},
79 {0x25, 0x00000483}, {0x26, 0x0004f000},
80 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
81 {0x29, 0x00004783}, {0x2a, 0x00000001},
82 {0x2b, 0x00021334}, {0x2a, 0x00000000},
83 {0x2b, 0x00000054}, {0x2a, 0x00000001},
84 {0x2b, 0x00000808}, {0x2b, 0x00053333},
85 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
86 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
87 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
88 {0x2b, 0x00000808}, {0x2b, 0x00063333},
89 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
90 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
91 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
92 {0x2b, 0x00000808}, {0x2b, 0x00073333},
93 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
94 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
95 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
96 {0x2b, 0x00000709}, {0x2b, 0x00063333},
97 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
98 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
99 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
100 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
101 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
102 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
103 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
104 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
105 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
106 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
107 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
108 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
109 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
110 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
111 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
112 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
113 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
114 {0x10, 0x0002000f}, {0x11, 0x000203f9},
115 {0x10, 0x0003000f}, {0x11, 0x000ff500},
116 {0x10, 0x00000000}, {0x11, 0x00000000},
117 {0x10, 0x0008000f}, {0x11, 0x0003f100},
118 {0x10, 0x0009000f}, {0x11, 0x00023100},
119 {0x12, 0x00032000}, {0x12, 0x00071000},
120 {0x12, 0x000b0000}, {0x12, 0x000fc000},
121 {0x13, 0x000287b3}, {0x13, 0x000244b7},
122 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
123 {0x13, 0x00018493}, {0x13, 0x0001429b},
124 {0x13, 0x00010299}, {0x13, 0x0000c29c},
125 {0x13, 0x000081a0}, {0x13, 0x000040ac},
126 {0x13, 0x00000020}, {0x14, 0x0001944c},
127 {0x14, 0x00059444}, {0x14, 0x0009944c},
128 {0x14, 0x000d9444}, {0x15, 0x0000f474},
129 {0x15, 0x0004f477}, {0x15, 0x0008f455},
130 {0x15, 0x000cf455}, {0x16, 0x00000339},
131 {0x16, 0x00040339}, {0x16, 0x00080339},
132 {0x16, 0x000c0366}, {0x00, 0x00010159},
133 {0x18, 0x0000f401}, {0xfe, 0x00000000},
134 {0xfe, 0x00000000}, {0x1f, 0x00000003},
135 {0xfe, 0x00000000}, {0xfe, 0x00000000},
136 {0x1e, 0x00000247}, {0x1f, 0x00000000},
137 {0x00, 0x00030159},
138 {0xff, 0xffffffff}
145 int ret = 0; in rtl8723au_identify_chip()
194 if (efuse->rtl_id != cpu_to_le16(0x8129)) in rtl8723au_parse_efuse()
227 if (priv->efuse_wifi.efuse8723.version >= 0x01) in rtl8723au_parse_efuse()
228 priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; in rtl8723au_parse_efuse()
234 return 0; in rtl8723au_parse_efuse()
243 case 0: in rtl8723au_load_firmware()
268 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); in rtl8723au_init_phy_rf()
269 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
270 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); in rtl8723au_init_phy_rf()
271 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
280 int count, ret = 0; in rtl8723a_emu_to_active()
282 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ in rtl8723a_emu_to_active()
287 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ in rtl8723a_emu_to_active()
288 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723a_emu_to_active()
290 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723a_emu_to_active()
294 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ in rtl8723a_emu_to_active()
299 /* disable SW LPS 0x04[10]= 0 */ in rtl8723a_emu_to_active()
304 /* wait till 0x04[17] = 1 power ready*/ in rtl8723a_emu_to_active()
320 /* release WLON reset 0x04[16]= 1*/ in rtl8723a_emu_to_active()
322 val8 |= BIT(0); in rtl8723a_emu_to_active()
325 /* disable HWPDN 0x04[15]= 0*/ in rtl8723a_emu_to_active()
335 /* set, then poll until 0 */ in rtl8723a_emu_to_active()
342 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8723a_emu_to_active()
343 ret = 0; in rtl8723a_emu_to_active()
354 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ in rtl8723a_emu_to_active()
376 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register in rtl8723au_power_on()
378 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); in rtl8723au_power_on()
387 * 0x0004[19] = 1, reset 8051 in rtl8723au_power_on()
408 val32 |= (0x06 << 28); in rtl8723au_power_on()
428 "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", in rtl8723a_set_crystal_cap()
446 s8 rx_pwr_all = 0x00; in rtl8723a_cck_rssi()
448 switch (cck_agc_rpt & 0xc0) { in rtl8723a_cck_rssi()
449 case 0xc0: in rtl8723a_cck_rssi()
450 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); in rtl8723a_cck_rssi()
452 case 0x80: in rtl8723a_cck_rssi()
453 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); in rtl8723a_cck_rssi()
455 case 0x40: in rtl8723a_cck_rssi()
456 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); in rtl8723a_cck_rssi()
458 case 0x00: in rtl8723a_cck_rssi()
459 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); in rtl8723a_cck_rssi()
487 return 0; in rtl8723au_led_brightness_set()
523 .adda_1t_init = 0x0b1b25a0,
524 .adda_1t_path_on = 0x0bdb25a0,
525 .adda_2t_path_on_a = 0x04db25a4,
526 .adda_2t_path_on_b = 0x0b1b25a4,
527 .trxff_boundary = 0x27ff,