Lines Matching refs:val32
395 u32 sys_cfg, vendor, val32; in rtl8192fu_identify_chip() local
410 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8192fu_identify_chip()
411 priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); in rtl8192fu_identify_chip()
412 priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); in rtl8192fu_identify_chip()
413 priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); in rtl8192fu_identify_chip()
419 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192fu_identify_chip()
420 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192fu_identify_chip()
429 u32 val32, ofdm, mcs; in rtl8192f_set_tx_power() local
438 val32 = (cck << 16) | (cck << 8) | cck; in rtl8192f_set_tx_power()
440 0x7f7f7f00, val32); in rtl8192f_set_tx_power()
466 val32 = (cck << 16) | (cck << 8) | cck; in rtl8192f_set_tx_power()
468 0x7f7f7f00, val32); in rtl8192f_set_tx_power()
590 u32 val32; in rtl8192fu_config_channel() local
604 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8192fu_config_channel()
609 val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */ in rtl8192fu_config_channel()
610 u32p_replace_bits(&val32, channel, 0xff); in rtl8192fu_config_channel()
611 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
613 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
643 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8192fu_config_channel()
644 val32 &= ~MODE_AG_BW_MASK; in rtl8192fu_config_channel()
646 val32 |= MODE_AG_BW_40MHZ_8723B; in rtl8192fu_config_channel()
648 val32 |= MODE_AG_BW_20MHZ_8723B; in rtl8192fu_config_channel()
649 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
651 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
659 val32 = 0x3; in rtl8192fu_config_channel()
661 val32 = 0x1a3; in rtl8192fu_config_channel()
662 rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32); in rtl8192fu_config_channel()
778 u32 val32; in rtl8192f_phy_lc_calibrate() local
781 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8192f_phy_lc_calibrate()
782 backup = u32_get_bits(val32, backup_mask); in rtl8192f_phy_lc_calibrate()
784 u32p_replace_bits(&val32, 0, backup_mask); in rtl8192f_phy_lc_calibrate()
785 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8192f_phy_lc_calibrate()
790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8192f_phy_lc_calibrate()
791 u32p_replace_bits(&val32, backup, backup_mask); in rtl8192f_phy_lc_calibrate()
792 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8192f_phy_lc_calibrate()
801 u32 reg_eac, reg_e94, reg_e9c, val32; in rtl8192fu_iqk_path_a() local
821 val32 = 0x30; in rtl8192fu_iqk_path_a()
823 val32 = 0xe9; in rtl8192fu_iqk_path_a()
824 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32); in rtl8192fu_iqk_path_a()
865 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD); in rtl8192fu_iqk_path_a()
866 rf_0x58_i = u32_get_bits(val32, 0xfc000); in rtl8192fu_iqk_path_a()
867 rf_0x58_q = u32_get_bits(val32, 0x003f0); in rtl8192fu_iqk_path_a()
892 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8192fu_rx_iqk_path_a() local
955 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); in rtl8192fu_rx_iqk_path_a()
956 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_a()
1025 u32 reg_eac, reg_eb4, reg_ebc, val32; in rtl8192fu_iqk_path_b() local
1090 val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD); in rtl8192fu_iqk_path_b()
1091 rf_0x58_i = u32_get_bits(val32, 0xfc000); in rtl8192fu_iqk_path_b()
1092 rf_0x58_q = u32_get_bits(val32, 0x003f0); in rtl8192fu_iqk_path_b()
1120 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; in rtl8192fu_rx_iqk_path_b() local
1185 val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); in rtl8192fu_rx_iqk_path_b()
1186 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_b()
1276 u32 i, val32; in rtl8192fu_phy_iqcalibrate() local
1338 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192fu_phy_iqcalibrate()
1339 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192fu_phy_iqcalibrate()
1342 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1354 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192fu_phy_iqcalibrate()
1355 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1357 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_phy_iqcalibrate()
1358 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1374 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192fu_phy_iqcalibrate()
1375 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1377 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192fu_phy_iqcalibrate()
1378 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1390 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192fu_phy_iqcalibrate()
1391 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1393 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192fu_phy_iqcalibrate()
1394 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8192fu_phy_iqcalibrate()
1455 u32 val32; in rtl8192fu_phy_iq_calibrate() local
1557 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192fu_phy_iq_calibrate()
1558 val32 &= ~BIT(11); in rtl8192fu_phy_iq_calibrate()
1559 val32 |= 0x1f; in rtl8192fu_phy_iq_calibrate()
1560 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192fu_phy_iq_calibrate()
1604 u32 val32; in rtl8192fu_emu_to_active() local
1624 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1625 if (val32 & BIT(17)) in rtl8192fu_emu_to_active()
1637 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1638 if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0) in rtl8192fu_emu_to_active()
1661 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1662 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) in rtl8192fu_emu_to_active()
1730 u32 val32; in rtl8192fu_active_to_emu() local
1746 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_active_to_emu()
1747 if ((val32 & APS_FSMCO_MAC_OFF) == 0) in rtl8192fu_active_to_emu()
1788 u32 val32; in rtl8192fu_active_to_lps() local
1798 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192fu_active_to_lps()
1799 if (!val32) in rtl8192fu_active_to_lps()
1901 u32 val32; in rtl8192f_enable_rf() local
1905 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8192f_enable_rf()
1906 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); in rtl8192f_enable_rf()
1907 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | in rtl8192f_enable_rf()
1909 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8192f_enable_rf()
1916 u32 val32; in rtl8192f_disable_rf() local
1918 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8192f_disable_rf()
1919 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8192f_disable_rf()
1920 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8192f_disable_rf()