Lines Matching refs:val32
468 u32 val32, bonding, sys_cfg, vendor; in rtl8192eu_identify_chip() local
497 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
498 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
515 u32 val32, ofdm, mcs; in rtl8192e_set_tx_power() local
524 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
525 val32 &= 0xffff00ff; in rtl8192e_set_tx_power()
526 val32 |= (cck << 8); in rtl8192e_set_tx_power()
527 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
529 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
530 val32 &= 0xff; in rtl8192e_set_tx_power()
531 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8192e_set_tx_power()
532 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
556 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
557 val32 &= 0xff; in rtl8192e_set_tx_power()
558 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8192e_set_tx_power()
559 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
561 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
562 val32 &= 0xffffff00; in rtl8192e_set_tx_power()
563 val32 |= cck; in rtl8192e_set_tx_power()
564 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
745 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8192eu_rx_iqk_path_a() local
807 val32 = 0x80007c00 | in rtl8192eu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
921 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; in rtl8192eu_rx_iqk_path_b() local
986 val32 = 0x80007c00 | in rtl8192eu_rx_iqk_path_b()
988 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1054 u32 i, val32; in rtl8192eu_phy_iqcalibrate() local
1099 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1100 val32 |= 0x0f000000; in rtl8192eu_phy_iqcalibrate()
1101 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1107 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1108 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); in rtl8192eu_phy_iqcalibrate()
1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1112 val32 |= BIT(10); in rtl8192eu_phy_iqcalibrate()
1113 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1114 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1115 val32 |= BIT(10); in rtl8192eu_phy_iqcalibrate()
1116 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1125 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1127 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1128 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1130 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1142 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1144 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1145 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1147 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1172 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1173 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1174 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1175 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1186 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1188 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1189 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1191 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1216 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1217 val32 &= 0xffffff00; in rtl8192eu_phy_iqcalibrate()
1218 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1219 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1222 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1223 val32 &= 0xffffff00; in rtl8192eu_phy_iqcalibrate()
1225 val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1227 val32 | xb_agc); in rtl8192eu_phy_iqcalibrate()
1333 u32 val32; in rtl8192e_crystal_afe_adjust() local
1342 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1343 val32 &= 0xfffffc7f; in rtl8192e_crystal_afe_adjust()
1344 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1357 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1358 val32 &= 0xffdfffff; in rtl8192e_crystal_afe_adjust()
1359 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1375 u32 val32; in rtl8192e_emu_to_active() local
1395 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1396 if (val32 & BIT(17)) in rtl8192e_emu_to_active()
1415 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1416 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8192e_emu_to_active()
1417 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1420 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1421 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8192e_emu_to_active()
1442 u32 val32; in rtl8192eu_active_to_lps() local
1453 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1454 if (!val32) { in rtl8192eu_active_to_lps()
1550 u32 val32; in rtl8192eu_power_on() local
1553 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1554 if (val32 & SYS_CFG_SPS_LDO_SEL) { in rtl8192eu_power_on()
1560 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1561 val32 &= 0xff0fffff; in rtl8192eu_power_on()
1562 val32 |= 0x00500000; in rtl8192eu_power_on()
1563 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1631 u32 val32; in rtl8192e_enable_rf() local
1634 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1635 val32 |= (BIT(22) | BIT(23)); in rtl8192e_enable_rf()
1636 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1647 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1648 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8192e_enable_rf()
1649 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1651 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1652 val32 |= (BIT(0) | BIT(1)); in rtl8192e_enable_rf()
1653 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1657 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1658 val32 &= ~BIT(24); in rtl8192e_enable_rf()
1659 val32 |= BIT(23); in rtl8192e_enable_rf()
1660 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()